diff --git a/alloc/src/alloc.rs b/alloc/src/alloc.rs index cd1c2ea8fcd1e..8fbd4b612bde0 100644 --- a/alloc/src/alloc.rs +++ b/alloc/src/alloc.rs @@ -5,7 +5,7 @@ #[stable(feature = "alloc_module", since = "1.28.0")] #[doc(inline)] pub use core::alloc::*; -use core::ptr::{self, NonNull}; +use core::ptr::{self, Alignment, NonNull}; use core::{cmp, hint}; unsafe extern "Rust" { @@ -18,19 +18,19 @@ unsafe extern "Rust" { #[rustc_nounwind] #[rustc_std_internal_symbol] #[rustc_allocator_zeroed_variant = "__rust_alloc_zeroed"] - fn __rust_alloc(size: usize, align: usize) -> *mut u8; + fn __rust_alloc(size: usize, align: Alignment) -> *mut u8; #[rustc_deallocator] #[rustc_nounwind] #[rustc_std_internal_symbol] - fn __rust_dealloc(ptr: *mut u8, size: usize, align: usize); + fn __rust_dealloc(ptr: *mut u8, size: usize, align: Alignment); #[rustc_reallocator] #[rustc_nounwind] #[rustc_std_internal_symbol] - fn __rust_realloc(ptr: *mut u8, old_size: usize, align: usize, new_size: usize) -> *mut u8; + fn __rust_realloc(ptr: *mut u8, old_size: usize, align: Alignment, new_size: usize) -> *mut u8; #[rustc_allocator_zeroed] #[rustc_nounwind] #[rustc_std_internal_symbol] - fn __rust_alloc_zeroed(size: usize, align: usize) -> *mut u8; + fn __rust_alloc_zeroed(size: usize, align: Alignment) -> *mut u8; #[rustc_nounwind] #[rustc_std_internal_symbol] @@ -92,7 +92,7 @@ pub unsafe fn alloc(layout: Layout) -> *mut u8 { // stable code until it is actually stabilized. __rust_no_alloc_shim_is_unstable_v2(); - __rust_alloc(layout.size(), layout.align()) + __rust_alloc(layout.size(), layout.alignment()) } } @@ -112,7 +112,7 @@ pub unsafe fn alloc(layout: Layout) -> *mut u8 { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { - unsafe { __rust_dealloc(ptr, layout.size(), layout.align()) } + unsafe { __rust_dealloc(ptr, layout.size(), layout.alignment()) } } /// Reallocates memory with the global allocator. @@ -132,7 +132,7 @@ pub unsafe fn dealloc(ptr: *mut u8, layout: Layout) { #[inline] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub unsafe fn realloc(ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - unsafe { __rust_realloc(ptr, layout.size(), layout.align(), new_size) } + unsafe { __rust_realloc(ptr, layout.size(), layout.alignment(), new_size) } } /// Allocates zero-initialized memory with the global allocator. @@ -175,7 +175,7 @@ pub unsafe fn alloc_zeroed(layout: Layout) -> *mut u8 { // stable code until it is actually stabilized. __rust_no_alloc_shim_is_unstable_v2(); - __rust_alloc_zeroed(layout.size(), layout.align()) + __rust_alloc_zeroed(layout.size(), layout.alignment()) } } @@ -479,19 +479,6 @@ unsafe impl const Allocator for Global { } } -/// The allocator for `Box`. -#[cfg(not(no_global_oom_handling))] -#[lang = "exchange_malloc"] -#[inline] -#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces -unsafe fn exchange_malloc(size: usize, align: usize) -> *mut u8 { - let layout = unsafe { Layout::from_size_align_unchecked(size, align) }; - match Global.allocate(layout) { - Ok(ptr) => ptr.as_mut_ptr(), - Err(_) => handle_alloc_error(layout), - } -} - // # Allocation error handler #[cfg(not(no_global_oom_handling))] diff --git a/alloc/src/boxed.rs b/alloc/src/boxed.rs index 0844239826bf5..ae16a8401552d 100644 --- a/alloc/src/boxed.rs +++ b/alloc/src/boxed.rs @@ -236,14 +236,34 @@ pub struct Box< #[unstable(feature = "allocator_api", issue = "32838")] A: Allocator = Global, >(Unique, A); -/// Constructs a `Box` by calling the `exchange_malloc` lang item and moving the argument into -/// the newly allocated memory. This is an intrinsic to avoid unnecessary copies. +/// Monomorphic function for allocating an uninit `Box`. +#[inline] +// The is a separate function to avoid doing it in every generic version, but it +// looks small to the mir inliner (particularly in panic=abort) so leave it to +// the backend to decide whether pulling it in everywhere is worth doing. +#[rustc_no_mir_inline] +#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces +#[cfg(not(no_global_oom_handling))] +fn box_new_uninit(layout: Layout) -> *mut u8 { + match Global.allocate(layout) { + Ok(ptr) => ptr.as_mut_ptr(), + Err(_) => handle_alloc_error(layout), + } +} + +/// Helper for `vec!`. /// -/// This is the surface syntax for `box ` expressions. +/// This is unsafe, but has to be marked as safe or else we couldn't use it in `vec!`. #[doc(hidden)] -#[rustc_intrinsic] #[unstable(feature = "liballoc_internals", issue = "none")] -pub fn box_new(x: T) -> Box; +#[inline(always)] +#[cfg(not(no_global_oom_handling))] +#[rustc_diagnostic_item = "box_assume_init_into_vec_unsafe"] +pub fn box_assume_init_into_vec_unsafe( + b: Box>, +) -> crate::vec::Vec { + unsafe { (b.assume_init() as Box<[T]>).into_vec() } +} impl Box { /// Allocates memory on the heap and then places `x` into it. @@ -262,7 +282,13 @@ impl Box { #[rustc_diagnostic_item = "box_new"] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub fn new(x: T) -> Self { - return box_new(x); + // This is `Box::new_uninit` but inlined to avoid build time regressions. + let ptr = box_new_uninit(::LAYOUT) as *mut T; + // Nothing below can panic so we do not have to worry about deallocating `ptr`. + // SAFETY: we just allocated the box to store `x`. + unsafe { core::intrinsics::write_via_move(ptr, x) }; + // SAFETY: we just initialized `b`. + unsafe { mem::transmute(ptr) } } /// Constructs a new box with uninitialized contents. @@ -280,9 +306,15 @@ impl Box { #[cfg(not(no_global_oom_handling))] #[stable(feature = "new_uninit", since = "1.82.0")] #[must_use] - #[inline] + #[inline(always)] + #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub fn new_uninit() -> Box> { - Self::new_uninit_in(Global) + // This is the same as `Self::new_uninit_in(Global)`, but manually inlined (just like + // `Box::new`). + + // SAFETY: + // - If `allocate` succeeds, the returned pointer exactly matches what `Box` needs. + unsafe { mem::transmute(box_new_uninit(::LAYOUT)) } } /// Constructs a new `Box` with uninitialized contents, with the memory @@ -1142,10 +1174,12 @@ impl Box, A> { /// assert_eq!(*five, 5) /// ``` #[stable(feature = "new_uninit", since = "1.82.0")] - #[inline] + #[inline(always)] pub unsafe fn assume_init(self) -> Box { - let (raw, alloc) = Box::into_raw_with_allocator(self); - unsafe { Box::from_raw_in(raw as *mut T, alloc) } + // This is used in the `vec!` macro, so we optimize for minimal IR generation + // even in debug builds. + // SAFETY: `Box` and `Box>` have the same layout. + unsafe { core::intrinsics::transmute_unchecked(self) } } /// Writes the value and converts to `Box`. @@ -1514,7 +1548,7 @@ impl Box { /// Recreate a `Box` which was previously converted to a `NonNull` pointer /// using [`Box::into_non_null_with_allocator`]: /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1524,7 +1558,7 @@ impl Box { /// ``` /// Manually create a `Box` from scratch by using the system allocator: /// ``` - /// #![feature(allocator_api, box_vec_non_null, slice_ptr_get)] + /// #![feature(allocator_api)] /// /// use std::alloc::{Allocator, Layout, System}; /// @@ -1629,7 +1663,7 @@ impl Box { /// Converting the `NonNull` pointer back into a `Box` with /// [`Box::from_non_null_in`] for automatic cleanup: /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1640,7 +1674,7 @@ impl Box { /// Manual cleanup by explicitly running the destructor and deallocating /// the memory: /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::{Allocator, Layout, System}; /// diff --git a/alloc/src/bstr.rs b/alloc/src/bstr.rs index 338c7ac7f8876..e0d88b27672e0 100644 --- a/alloc/src/bstr.rs +++ b/alloc/src/bstr.rs @@ -477,9 +477,8 @@ impl PartialEq for ByteString { macro_rules! impl_partial_eq_ord_cow { ($lhs:ty, $rhs:ty) => { - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { let other: &[u8] = (&**other).as_ref(); @@ -487,9 +486,8 @@ macro_rules! impl_partial_eq_ord_cow { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { let this: &[u8] = (&**self).as_ref(); @@ -497,9 +495,8 @@ macro_rules! impl_partial_eq_ord_cow { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { let other: &[u8] = (&**other).as_ref(); @@ -507,9 +504,8 @@ macro_rules! impl_partial_eq_ord_cow { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { let this: &[u8] = (&**self).as_ref(); @@ -667,9 +663,9 @@ impl From> for Arc<[u8]> { impl_partial_eq!(ByteStr, Vec); // PartialOrd with `String` omitted to avoid inference failures impl_partial_eq!(ByteStr, String); -impl_partial_eq_ord_cow!(&'a ByteStr, Cow<'a, ByteStr>); -impl_partial_eq_ord_cow!(&'a ByteStr, Cow<'a, str>); -impl_partial_eq_ord_cow!(&'a ByteStr, Cow<'a, [u8]>); +impl_partial_eq_ord_cow!(&ByteStr, Cow<'_, ByteStr>); +impl_partial_eq_ord_cow!(&ByteStr, Cow<'_, str>); +impl_partial_eq_ord_cow!(&ByteStr, Cow<'_, [u8]>); #[unstable(feature = "bstr", issue = "134915")] impl<'a> TryFrom<&'a ByteStr> for String { diff --git a/alloc/src/collections/binary_heap/mod.rs b/alloc/src/collections/binary_heap/mod.rs index 97aafbc7b6994..4ddfcde57280e 100644 --- a/alloc/src/collections/binary_heap/mod.rs +++ b/alloc/src/collections/binary_heap/mod.rs @@ -581,6 +581,40 @@ impl BinaryHeap { pub fn with_capacity_in(capacity: usize, alloc: A) -> BinaryHeap { BinaryHeap { data: Vec::with_capacity_in(capacity, alloc) } } + + /// Creates a `BinaryHeap` using the supplied `vec`. This does not rebuild the heap, + /// so `vec` must already be a max-heap. + /// + /// # Safety + /// + /// The supplied `vec` must be a max-heap, i.e. for all indices `0 < i < vec.len()`, + /// `vec[(i - 1) / 2] >= vec[i]`. + /// + /// # Examples + /// + /// Basic usage: + /// + /// ``` + /// #![feature(binary_heap_from_raw_vec)] + /// + /// use std::collections::BinaryHeap; + /// let heap = BinaryHeap::from([1, 2, 3]); + /// let vec = heap.into_vec(); + /// + /// // Safety: vec is the output of heap.from_vec(), so is a max-heap. + /// let mut new_heap = unsafe { + /// BinaryHeap::from_raw_vec(vec) + /// }; + /// assert_eq!(new_heap.pop(), Some(3)); + /// assert_eq!(new_heap.pop(), Some(2)); + /// assert_eq!(new_heap.pop(), Some(1)); + /// assert_eq!(new_heap.pop(), None); + /// ``` + #[unstable(feature = "binary_heap_from_raw_vec", issue = "152500")] + #[must_use] + pub unsafe fn from_raw_vec(vec: Vec) -> BinaryHeap { + BinaryHeap { data: vec } + } } impl BinaryHeap { diff --git a/alloc/src/collections/btree/map.rs b/alloc/src/collections/btree/map.rs index 426be364a56b0..d69dad70a44e9 100644 --- a/alloc/src/collections/btree/map.rs +++ b/alloc/src/collections/btree/map.rs @@ -1240,6 +1240,162 @@ impl BTreeMap { ) } + /// Moves all elements from `other` into `self`, leaving `other` empty. + /// + /// If a key from `other` is already present in `self`, then the `conflict` + /// closure is used to return a value to `self`. The `conflict` + /// closure takes in a borrow of `self`'s key, `self`'s value, and `other`'s value + /// in that order. + /// + /// An example of why one might use this method over [`append`] + /// is to combine `self`'s value with `other`'s value when their keys conflict. + /// + /// Similar to [`insert`], though, the key is not overwritten, + /// which matters for types that can be `==` without being identical. + /// + /// [`insert`]: BTreeMap::insert + /// [`append`]: BTreeMap::append + /// + /// # Examples + /// + /// ``` + /// #![feature(btree_merge)] + /// use std::collections::BTreeMap; + /// + /// let mut a = BTreeMap::new(); + /// a.insert(1, String::from("a")); + /// a.insert(2, String::from("b")); + /// a.insert(3, String::from("c")); // Note: Key (3) also present in b. + /// + /// let mut b = BTreeMap::new(); + /// b.insert(3, String::from("d")); // Note: Key (3) also present in a. + /// b.insert(4, String::from("e")); + /// b.insert(5, String::from("f")); + /// + /// // concatenate a's value and b's value + /// a.merge(b, |_, a_val, b_val| { + /// format!("{a_val}{b_val}") + /// }); + /// + /// assert_eq!(a.len(), 5); // all of b's keys in a + /// + /// assert_eq!(a[&1], "a"); + /// assert_eq!(a[&2], "b"); + /// assert_eq!(a[&3], "cd"); // Note: "c" has been combined with "d". + /// assert_eq!(a[&4], "e"); + /// assert_eq!(a[&5], "f"); + /// ``` + #[unstable(feature = "btree_merge", issue = "152152")] + pub fn merge(&mut self, mut other: Self, mut conflict: impl FnMut(&K, V, V) -> V) + where + K: Ord, + A: Clone, + { + // Do we have to append anything at all? + if other.is_empty() { + return; + } + + // We can just swap `self` and `other` if `self` is empty. + if self.is_empty() { + mem::swap(self, &mut other); + return; + } + + let mut other_iter = other.into_iter(); + let (first_other_key, first_other_val) = other_iter.next().unwrap(); + + // find the first gap that has the smallest key greater than or equal to + // the first key from other + let mut self_cursor = self.lower_bound_mut(Bound::Included(&first_other_key)); + + if let Some((self_key, _)) = self_cursor.peek_next() { + match K::cmp(self_key, &first_other_key) { + Ordering::Equal => { + // if `f` unwinds, the next entry is already removed leaving + // the tree in valid state. + // FIXME: Once `MaybeDangling` is implemented, we can optimize + // this through using a drop handler and transmutating CursorMutKey + // to CursorMutKey, ManuallyDrop> (see PR #152418) + if let Some((k, v)) = self_cursor.remove_next() { + // SAFETY: we remove the K, V out of the next entry, + // apply 'f' to get a new (K, V), and insert it back + // into the next entry that the cursor is pointing at + let v = conflict(&k, v, first_other_val); + unsafe { self_cursor.insert_after_unchecked(k, v) }; + } + } + Ordering::Greater => + // SAFETY: we know our other_key's ordering is less than self_key, + // so inserting before will guarantee sorted order + unsafe { + self_cursor.insert_before_unchecked(first_other_key, first_other_val); + }, + Ordering::Less => { + unreachable!("Cursor's peek_next should return None."); + } + } + } else { + // SAFETY: reaching here means our cursor is at the end + // self BTreeMap so we just insert other_key here + unsafe { + self_cursor.insert_before_unchecked(first_other_key, first_other_val); + } + } + + for (other_key, other_val) in other_iter { + loop { + if let Some((self_key, _)) = self_cursor.peek_next() { + match K::cmp(self_key, &other_key) { + Ordering::Equal => { + // if `f` unwinds, the next entry is already removed leaving + // the tree in valid state. + // FIXME: Once `MaybeDangling` is implemented, we can optimize + // this through using a drop handler and transmutating CursorMutKey + // to CursorMutKey, ManuallyDrop> (see PR #152418) + if let Some((k, v)) = self_cursor.remove_next() { + // SAFETY: we remove the K, V out of the next entry, + // apply 'f' to get a new (K, V), and insert it back + // into the next entry that the cursor is pointing at + let v = conflict(&k, v, other_val); + unsafe { self_cursor.insert_after_unchecked(k, v) }; + } + break; + } + Ordering::Greater => { + // SAFETY: we know our self_key's ordering is greater than other_key, + // so inserting before will guarantee sorted order + unsafe { + self_cursor.insert_before_unchecked(other_key, other_val); + } + break; + } + Ordering::Less => { + // FIXME: instead of doing a linear search here, + // this can be optimized to search the tree by starting + // from self_cursor and going towards the root and then + // back down to the proper node -- that should probably + // be a new method on Cursor*. + self_cursor.next(); + } + } + } else { + // FIXME: If we get here, that means all of other's keys are greater than + // self's keys. For performance, this should really do a bulk insertion of items + // from other_iter into the end of self `BTreeMap`. Maybe this should be + // a method for Cursor*? + + // SAFETY: reaching here means our cursor is at the end + // self BTreeMap so we just insert other_key here + unsafe { + self_cursor.insert_before_unchecked(other_key, other_val); + } + break; + } + } + } + } + /// Constructs a double-ended iterator over a sub-range of elements in the map. /// The simplest way is to use the range syntax `min..max`, thus `range(min..max)` will /// yield elements from min (inclusive) to max (exclusive). diff --git a/alloc/src/collections/btree/map/tests.rs b/alloc/src/collections/btree/map/tests.rs index 938e867b85812..73546caa05eac 100644 --- a/alloc/src/collections/btree/map/tests.rs +++ b/alloc/src/collections/btree/map/tests.rs @@ -1,9 +1,9 @@ use core::assert_matches; -use std::iter; use std::ops::Bound::{Excluded, Included, Unbounded}; use std::panic::{AssertUnwindSafe, catch_unwind}; use std::sync::atomic::AtomicUsize; use std::sync::atomic::Ordering::SeqCst; +use std::{cmp, iter}; use super::*; use crate::boxed::Box; @@ -2128,6 +2128,86 @@ create_append_test!(test_append_239, 239); #[cfg(not(miri))] // Miri is too slow create_append_test!(test_append_1700, 1700); +// a inserts (0, 0)..(8, 8) to its own tree +// b inserts (5, 5 * 2)..($len, 2 * $len) to its own tree +// note that between a and b, there are duplicate keys +// between 5..min($len, 8), so on merge we add the values +// of these keys together +// we check that: +// - the merged tree 'a' has a length of max(8, $len) +// - all keys in 'a' have the correct value associated +// - removing and inserting an element into the merged +// tree 'a' still keeps it in valid tree form +macro_rules! create_merge_test { + ($name:ident, $len:expr) => { + #[test] + fn $name() { + let mut a = BTreeMap::new(); + for i in 0..8 { + a.insert(i, i); + } + + let mut b = BTreeMap::new(); + for i in 5..$len { + b.insert(i, 2 * i); + } + + a.merge(b, |_, a_val, b_val| a_val + b_val); + + assert_eq!(a.len(), cmp::max($len, 8)); + + for i in 0..cmp::max($len, 8) { + if i < 5 { + assert_eq!(a[&i], i); + } else { + if i < cmp::min($len, 8) { + assert_eq!(a[&i], i + 2 * i); + } else if i >= $len { + assert_eq!(a[&i], i); + } else { + assert_eq!(a[&i], 2 * i); + } + } + } + + a.check(); + assert_eq!( + a.remove(&($len - 1)), + if $len >= 5 && $len < 8 { + Some(($len - 1) + 2 * ($len - 1)) + } else { + Some(2 * ($len - 1)) + } + ); + assert_eq!(a.insert($len - 1, 20), None); + a.check(); + } + }; +} + +// These are mostly for testing the algorithm that "fixes" the right edge after insertion. +// Single node, merge conflicting key values. +create_merge_test!(test_merge_7, 7); +// Single node. +create_merge_test!(test_merge_9, 9); +// Two leafs that don't need fixing. +create_merge_test!(test_merge_17, 17); +// Two leafs where the second one ends up underfull and needs stealing at the end. +create_merge_test!(test_merge_14, 14); +// Two leafs where the second one ends up empty because the insertion finished at the root. +create_merge_test!(test_merge_12, 12); +// Three levels; insertion finished at the root. +create_merge_test!(test_merge_144, 144); +// Three levels; insertion finished at leaf while there is an empty node on the second level. +create_merge_test!(test_merge_145, 145); +// Tests for several randomly chosen sizes. +create_merge_test!(test_merge_170, 170); +create_merge_test!(test_merge_181, 181); +#[cfg(not(miri))] // Miri is too slow +create_merge_test!(test_merge_239, 239); +#[cfg(not(miri))] // Miri is too slow +create_merge_test!(test_merge_1700, 1700); + #[test] #[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] fn test_append_drop_leak() { @@ -2169,6 +2249,84 @@ fn test_append_ord_chaos() { map2.check(); } +#[test] +#[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] +fn test_merge_drop_leak() { + let a = CrashTestDummy::new(0); + let b = CrashTestDummy::new(1); + let c = CrashTestDummy::new(2); + let mut left = BTreeMap::new(); + let mut right = BTreeMap::new(); + left.insert(a.spawn(Panic::Never), ()); + left.insert(b.spawn(Panic::Never), ()); + left.insert(c.spawn(Panic::Never), ()); + right.insert(b.spawn(Panic::InDrop), ()); // first duplicate key, dropped during merge + right.insert(c.spawn(Panic::Never), ()); + + catch_unwind(move || left.merge(right, |_, _, _| ())).unwrap_err(); + assert_eq!(a.dropped(), 1); // this should not be dropped + assert_eq!(b.dropped(), 2); // key is dropped on panic + assert_eq!(c.dropped(), 2); // key is dropped on panic +} + +#[test] +#[cfg_attr(not(panic = "unwind"), ignore = "test requires unwinding support")] +fn test_merge_conflict_drop_leak() { + let a = CrashTestDummy::new(0); + let a_val_left = CrashTestDummy::new(0); + + let b = CrashTestDummy::new(1); + let b_val_left = CrashTestDummy::new(1); + let b_val_right = CrashTestDummy::new(1); + + let c = CrashTestDummy::new(2); + let c_val_left = CrashTestDummy::new(2); + let c_val_right = CrashTestDummy::new(2); + + let mut left = BTreeMap::new(); + let mut right = BTreeMap::new(); + + left.insert(a.spawn(Panic::Never), a_val_left.spawn(Panic::Never)); + left.insert(b.spawn(Panic::Never), b_val_left.spawn(Panic::Never)); + left.insert(c.spawn(Panic::Never), c_val_left.spawn(Panic::Never)); + right.insert(b.spawn(Panic::Never), b_val_right.spawn(Panic::Never)); + right.insert(c.spawn(Panic::Never), c_val_right.spawn(Panic::Never)); + + // First key that conflicts should + catch_unwind(move || { + left.merge(right, |_, _, _| panic!("Panic in conflict function")); + assert_eq!(left.len(), 1); // only 1 entry should be left + }) + .unwrap_err(); + assert_eq!(a.dropped(), 1); // should not panic + assert_eq!(a_val_left.dropped(), 1); // should not panic + assert_eq!(b.dropped(), 2); // should drop from panic (conflict) + assert_eq!(b_val_left.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(b_val_right.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(c.dropped(), 2); // should drop from panic (conflict) + assert_eq!(c_val_left.dropped(), 1); // should be 2 were it not for Rust issue #47949 + assert_eq!(c_val_right.dropped(), 1); // should be 2 were it not for Rust issue #47949 +} + +#[test] +fn test_merge_ord_chaos() { + let mut map1 = BTreeMap::new(); + map1.insert(Cyclic3::A, ()); + map1.insert(Cyclic3::B, ()); + let mut map2 = BTreeMap::new(); + map2.insert(Cyclic3::A, ()); + map2.insert(Cyclic3::B, ()); + map2.insert(Cyclic3::C, ()); // lands first, before A + map2.insert(Cyclic3::B, ()); // lands first, before C + map1.check(); + map2.check(); // keys are not unique but still strictly ascending + assert_eq!(map1.len(), 2); + assert_eq!(map2.len(), 4); + map1.merge(map2, |_, _, _| ()); + assert_eq!(map1.len(), 5); + map1.check(); +} + fn rand_data(len: usize) -> Vec<(u32, u32)> { let mut rng = DeterministicRng::new(); Vec::from_iter((0..len).map(|_| (rng.next(), rng.next()))) @@ -2615,3 +2773,25 @@ fn test_id_based_append() { assert_eq!(lhs.pop_first().unwrap().0.name, "lhs_k".to_string()); } + +#[test] +fn test_id_based_merge() { + let mut lhs = BTreeMap::new(); + let mut rhs = BTreeMap::new(); + + lhs.insert(IdBased { id: 0, name: "lhs_k".to_string() }, "1".to_string()); + rhs.insert(IdBased { id: 0, name: "rhs_k".to_string() }, "2".to_string()); + + lhs.merge(rhs, |_, mut lhs_val, rhs_val| { + // confirming that lhs_val comes from lhs tree, + // rhs_val comes from rhs tree + assert_eq!(lhs_val, String::from("1")); + assert_eq!(rhs_val, String::from("2")); + lhs_val.push_str(&rhs_val); + lhs_val + }); + + let merged_kv_pair = lhs.pop_first().unwrap(); + assert_eq!(merged_kv_pair.0.id, 0); + assert_eq!(merged_kv_pair.0.name, "lhs_k".to_string()); +} diff --git a/alloc/src/ffi/c_str.rs b/alloc/src/ffi/c_str.rs index d6dcba7107a9c..fba967c04895a 100644 --- a/alloc/src/ffi/c_str.rs +++ b/alloc/src/ffi/c_str.rs @@ -103,6 +103,7 @@ use crate::vec::Vec; /// and other memory errors. #[derive(PartialEq, PartialOrd, Eq, Ord, Hash, Clone)] #[rustc_diagnostic_item = "cstring_type"] +#[rustc_insignificant_dtor] #[stable(feature = "alloc_c_string", since = "1.64.0")] pub struct CString { // Invariant 1: the slice ends with a zero byte and has a length of at least one. @@ -694,7 +695,6 @@ impl CString { // memory-unsafe code from working by accident. Inline // to prevent LLVM from optimizing it away in debug builds. #[stable(feature = "cstring_drop", since = "1.13.0")] -#[rustc_insignificant_dtor] impl Drop for CString { #[inline] fn drop(&mut self) { diff --git a/alloc/src/intrinsics.rs b/alloc/src/intrinsics.rs new file mode 100644 index 0000000000000..a1e358e077cb6 --- /dev/null +++ b/alloc/src/intrinsics.rs @@ -0,0 +1,15 @@ +//! Intrinsics that cannot be moved to `core` because they depend on `alloc` types. +#![unstable(feature = "liballoc_internals", issue = "none")] + +use core::mem::MaybeUninit; + +use crate::boxed::Box; + +/// Writes `x` into `b`. +/// +/// This is needed for `vec!`, which can't afford any extra copies of the argument (or else debug +/// builds regress), has to be written fully as a call chain without `let` (or else this breaks inference +/// of e.g. unsizing coercions), and can't use an `unsafe` block as that would then also +/// include the user-provided `$x`. +#[rustc_intrinsic] +pub fn write_box_via_move(b: Box>, x: T) -> Box>; diff --git a/alloc/src/lib.rs b/alloc/src/lib.rs index f7167650635d3..73e93657b02f7 100644 --- a/alloc/src/lib.rs +++ b/alloc/src/lib.rs @@ -56,6 +56,7 @@ //! [`Rc`]: rc //! [`RefCell`]: core::cell +#![allow(unused_features)] #![allow(incomplete_features)] #![allow(unused_attributes)] #![stable(feature = "alloc", since = "1.36.0")] @@ -85,14 +86,11 @@ // // Library features: // tidy-alphabetical-start -#![cfg_attr(not(no_global_oom_handling), feature(string_replace_in_place))] #![feature(allocator_api)] #![feature(array_into_iter_constructors)] #![feature(ascii_char)] -#![feature(assert_matches)] #![feature(async_fn_traits)] #![feature(async_iterator)] -#![feature(box_vec_non_null)] #![feature(bstr)] #![feature(bstr_internals)] #![feature(cast_maybe_uninit)] @@ -149,7 +147,6 @@ #![feature(slice_ptr_get)] #![feature(slice_range)] #![feature(std_internals)] -#![feature(str_internals)] #![feature(temporary_niche_types)] #![feature(transmutability)] #![feature(trivial_clone)] @@ -159,7 +156,6 @@ #![feature(try_blocks)] #![feature(try_trait_v2)] #![feature(try_trait_v2_residual)] -#![feature(try_with_capacity)] #![feature(tuple_trait)] #![feature(ub_checks)] #![feature(unicode_internals)] @@ -177,10 +173,8 @@ #![feature(const_trait_impl)] #![feature(coroutine_trait)] #![feature(decl_macro)] -#![feature(derive_const)] #![feature(dropck_eyepatch)] #![feature(fundamental)] -#![feature(hashmap_internals)] #![feature(intrinsics)] #![feature(lang_items)] #![feature(min_specialization)] @@ -188,7 +182,6 @@ #![feature(negative_impls)] #![feature(never_type)] #![feature(optimize_attribute)] -#![feature(rustc_allow_const_fn_unstable)] #![feature(rustc_attrs)] #![feature(slice_internals)] #![feature(staged_api)] @@ -230,6 +223,7 @@ pub mod collections; #[cfg(all(not(no_rc), not(no_sync), not(no_global_oom_handling)))] pub mod ffi; pub mod fmt; +pub mod intrinsics; #[cfg(not(no_rc))] pub mod rc; pub mod slice; diff --git a/alloc/src/macros.rs b/alloc/src/macros.rs index 1e6e2ae8c3675..b99107fb345a4 100644 --- a/alloc/src/macros.rs +++ b/alloc/src/macros.rs @@ -47,10 +47,16 @@ macro_rules! vec { $crate::vec::from_elem($elem, $n) ); ($($x:expr),+ $(,)?) => ( - <[_]>::into_vec( - // Using the intrinsic produces a dramatic improvement in stack usage for - // unoptimized programs using this code path to construct large Vecs. - $crate::boxed::box_new([$($x),+]) + // Using `write_box_via_move` produces a dramatic improvement in stack usage for unoptimized + // programs using this code path to construct large Vecs. We can't use `write_via_move` + // because this entire invocation has to remain a call chain without `let` bindings, or else + // inference and temporary lifetimes change and things break (see `vec-macro-rvalue-scope`, + // `vec-macro-coercions`, and `autoderef-vec-box-fn-36786` tests). + // + // `box_assume_init_into_vec_unsafe` isn't actually safe but the way we use it here is. We + // can't use an unsafe block as that would also wrap `$x`. + $crate::boxed::box_assume_init_into_vec_unsafe( + $crate::intrinsics::write_box_via_move($crate::boxed::Box::new_uninit(), [$($x),+]) ) ); } diff --git a/alloc/src/raw_vec/mod.rs b/alloc/src/raw_vec/mod.rs index ff996ba93cd7f..27a41369d4e5e 100644 --- a/alloc/src/raw_vec/mod.rs +++ b/alloc/src/raw_vec/mod.rs @@ -399,6 +399,21 @@ impl RawVec { // SAFETY: All calls on self.inner pass T::LAYOUT as the elem_layout unsafe { self.inner.shrink_to_fit(cap, T::LAYOUT) } } + + /// Shrinks the buffer down to the specified capacity. If the given amount + /// is 0, actually completely deallocates. + /// + /// # Errors + /// + /// This function returns an error if the allocator cannot shrink the allocation. + /// + /// # Panics + /// + /// Panics if the given amount is *larger* than the current capacity. + #[inline] + pub(crate) fn try_shrink_to_fit(&mut self, cap: usize) -> Result<(), TryReserveError> { + unsafe { self.inner.try_shrink_to_fit(cap, T::LAYOUT) } + } } unsafe impl<#[may_dangle] T, A: Allocator> Drop for RawVec { @@ -731,6 +746,20 @@ impl RawVecInner { } } + /// # Safety + /// + /// - `elem_layout` must be valid for `self`, i.e. it must be the same `elem_layout` used to + /// initially construct `self` + /// - `elem_layout`'s size must be a multiple of its alignment + /// - `cap` must be less than or equal to `self.capacity(elem_layout.size())` + unsafe fn try_shrink_to_fit( + &mut self, + cap: usize, + elem_layout: Layout, + ) -> Result<(), TryReserveError> { + unsafe { self.shrink(cap, elem_layout) } + } + #[inline] const fn needs_to_grow(&self, len: usize, additional: usize, elem_layout: Layout) -> bool { additional > self.capacity(elem_layout.size()).wrapping_sub(len) @@ -778,7 +807,6 @@ impl RawVecInner { /// initially construct `self` /// - `elem_layout`'s size must be a multiple of its alignment /// - `cap` must be less than or equal to `self.capacity(elem_layout.size())` - #[cfg(not(no_global_oom_handling))] #[inline] unsafe fn shrink(&mut self, cap: usize, elem_layout: Layout) -> Result<(), TryReserveError> { assert!(cap <= self.capacity(elem_layout.size()), "Tried to shrink to a larger capacity"); @@ -796,7 +824,6 @@ impl RawVecInner { /// /// # Safety /// `cap <= self.capacity()` - #[cfg(not(no_global_oom_handling))] unsafe fn shrink_unchecked( &mut self, cap: usize, diff --git a/alloc/src/slice.rs b/alloc/src/slice.rs index cc8d80aee4569..39e72e383eacb 100644 --- a/alloc/src/slice.rs +++ b/alloc/src/slice.rs @@ -477,7 +477,6 @@ impl [T] { #[rustc_allow_incoherent_impl] #[stable(feature = "rust1", since = "1.0.0")] #[inline] - #[rustc_diagnostic_item = "slice_into_vec"] pub fn into_vec(self: Box) -> Vec { unsafe { let len = self.len(); diff --git a/alloc/src/str.rs b/alloc/src/str.rs index e772ac25a95c2..8a3326c7d76a7 100644 --- a/alloc/src/str.rs +++ b/alloc/src/str.rs @@ -411,9 +411,8 @@ impl str { fn map_uppercase_sigma(from: &str, i: usize) -> char { // See https://www.unicode.org/versions/Unicode7.0.0/ch03.pdf#G33992 // for the definition of `Final_Sigma`. - debug_assert!('Σ'.len_utf8() == 2); let is_word_final = case_ignorable_then_cased(from[..i].chars().rev()) - && !case_ignorable_then_cased(from[i + 2..].chars()); + && !case_ignorable_then_cased(from[i + const { 'Σ'.len_utf8() }..].chars()); if is_word_final { 'ς' } else { 'σ' } } diff --git a/alloc/src/string.rs b/alloc/src/string.rs index 4100ee55a4c7b..30e52f3e1be46 100644 --- a/alloc/src/string.rs +++ b/alloc/src/string.rs @@ -2661,8 +2661,7 @@ impl<'b> Pattern for &'b String { macro_rules! impl_eq { ($lhs:ty, $rhs: ty) => { #[stable(feature = "rust1", since = "1.0.0")] - #[allow(unused_lifetimes)] - impl<'a, 'b> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { PartialEq::eq(&self[..], &other[..]) @@ -2674,8 +2673,7 @@ macro_rules! impl_eq { } #[stable(feature = "rust1", since = "1.0.0")] - #[allow(unused_lifetimes)] - impl<'a, 'b> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { PartialEq::eq(&self[..], &other[..]) @@ -2689,13 +2687,13 @@ macro_rules! impl_eq { } impl_eq! { String, str } -impl_eq! { String, &'a str } +impl_eq! { String, &str } #[cfg(not(no_global_oom_handling))] -impl_eq! { Cow<'a, str>, str } +impl_eq! { Cow<'_, str>, str } #[cfg(not(no_global_oom_handling))] -impl_eq! { Cow<'a, str>, &'b str } +impl_eq! { Cow<'_, str>, &'_ str } #[cfg(not(no_global_oom_handling))] -impl_eq! { Cow<'a, str>, String } +impl_eq! { Cow<'_, str>, String } #[stable(feature = "rust1", since = "1.0.0")] #[rustc_const_unstable(feature = "const_default", issue = "143894")] diff --git a/alloc/src/sync.rs b/alloc/src/sync.rs index a5e4fab916aba..dc82357dd146b 100644 --- a/alloc/src/sync.rs +++ b/alloc/src/sync.rs @@ -3270,7 +3270,7 @@ impl Weak { // Acquire is necessary for the success case to synchronise with `Arc::new_cyclic`, when the inner // value can be initialized after `Weak` references have already been created. In that case, we // expect to observe the fully initialized value. - if self.inner()?.strong.fetch_update(Acquire, Relaxed, checked_increment).is_ok() { + if self.inner()?.strong.try_update(Acquire, Relaxed, checked_increment).is_ok() { // SAFETY: pointer is not null, verified in checked_increment unsafe { Some(Arc::from_inner_in(self.ptr, self.alloc.clone())) } } else { diff --git a/alloc/src/vec/drain.rs b/alloc/src/vec/drain.rs index 8705a9c3d2679..9a6bfa823f2a5 100644 --- a/alloc/src/vec/drain.rs +++ b/alloc/src/vec/drain.rs @@ -1,8 +1,7 @@ -use core::fmt; use core::iter::{FusedIterator, TrustedLen}; use core::mem::{self, ManuallyDrop, SizedTypeProperties}; use core::ptr::{self, NonNull}; -use core::slice::{self}; +use core::{fmt, slice}; use super::Vec; use crate::alloc::{Allocator, Global}; diff --git a/alloc/src/vec/into_iter.rs b/alloc/src/vec/into_iter.rs index af1bd53179739..4f67a2c04fefc 100644 --- a/alloc/src/vec/into_iter.rs +++ b/alloc/src/vec/into_iter.rs @@ -9,8 +9,7 @@ use core::num::NonZero; use core::ops::Deref; use core::panic::UnwindSafe; use core::ptr::{self, NonNull}; -use core::slice::{self}; -use core::{array, fmt}; +use core::{array, fmt, slice}; #[cfg(not(no_global_oom_handling))] use super::AsVecIntoIter; diff --git a/alloc/src/vec/mod.rs b/alloc/src/vec/mod.rs index 6cbe89d9da4f2..4e3a5a7325b4f 100644 --- a/alloc/src/vec/mod.rs +++ b/alloc/src/vec/mod.rs @@ -75,8 +75,6 @@ #[cfg(not(no_global_oom_handling))] use core::clone::TrivialClone; -#[cfg(not(no_global_oom_handling))] -use core::cmp; use core::cmp::Ordering; use core::hash::{Hash, Hasher}; #[cfg(not(no_global_oom_handling))] @@ -88,7 +86,7 @@ use core::mem::{self, Assume, ManuallyDrop, MaybeUninit, SizedTypeProperties, Tr use core::ops::{self, Index, IndexMut, Range, RangeBounds}; use core::ptr::{self, NonNull}; use core::slice::{self, SliceIndex}; -use core::{fmt, hint, intrinsics, ub_checks}; +use core::{cmp, fmt, hint, intrinsics, ub_checks}; #[stable(feature = "extract_if", since = "1.87.0")] pub use self::extract_if::ExtractIf; @@ -1238,7 +1236,7 @@ impl Vec { /// # Examples /// /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1265,7 +1263,7 @@ impl Vec { /// Using memory that was allocated elsewhere: /// /// ```rust - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::{AllocError, Allocator, Global, Layout}; /// @@ -1365,7 +1363,7 @@ impl Vec { /// # Examples /// /// ``` - /// #![feature(allocator_api, box_vec_non_null)] + /// #![feature(allocator_api)] /// /// use std::alloc::System; /// @@ -1613,6 +1611,73 @@ impl Vec { } } + /// Tries to shrink the capacity of the vector as much as possible + /// + /// The behavior of this method depends on the allocator, which may either shrink the vector + /// in-place or reallocate. The resulting vector might still have some excess capacity, just as + /// is the case for [`with_capacity`]. See [`Allocator::shrink`] for more details. + /// + /// [`with_capacity`]: Vec::with_capacity + /// + /// # Errors + /// + /// This function returns an error if the allocator fails to shrink the allocation, + /// the vector thereafter is still safe to use, the capacity remains unchanged + /// however. See [`Allocator::shrink`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(vec_fallible_shrink)] + /// + /// let mut vec = Vec::with_capacity(10); + /// vec.extend([1, 2, 3]); + /// assert!(vec.capacity() >= 10); + /// vec.try_shrink_to_fit().expect("why is the test harness failing to shrink to 12 bytes"); + /// assert!(vec.capacity() >= 3); + /// ``` + #[unstable(feature = "vec_fallible_shrink", issue = "152350")] + #[inline] + pub fn try_shrink_to_fit(&mut self) -> Result<(), TryReserveError> { + if self.capacity() > self.len { self.buf.try_shrink_to_fit(self.len) } else { Ok(()) } + } + + /// Shrinks the capacity of the vector with a lower bound. + /// + /// The capacity will remain at least as large as both the length + /// and the supplied value. + /// + /// If the current capacity is less than the lower limit, this is a no-op. + /// + /// # Errors + /// + /// This function returns an error if the allocator fails to shrink the allocation, + /// the vector thereafter is still safe to use, the capacity remains unchanged + /// however. See [`Allocator::shrink`]. + /// + /// # Examples + /// + /// ``` + /// #![feature(vec_fallible_shrink)] + /// + /// let mut vec = Vec::with_capacity(10); + /// vec.extend([1, 2, 3]); + /// assert!(vec.capacity() >= 10); + /// vec.try_shrink_to(4).expect("why is the test harness failing to shrink to 12 bytes"); + /// assert!(vec.capacity() >= 4); + /// vec.try_shrink_to(0).expect("this is a no-op and thus the allocator isn't involved."); + /// assert!(vec.capacity() >= 3); + /// ``` + #[unstable(feature = "vec_fallible_shrink", issue = "152350")] + #[inline] + pub fn try_shrink_to(&mut self, min_capacity: usize) -> Result<(), TryReserveError> { + if self.capacity() > min_capacity { + self.buf.try_shrink_to_fit(cmp::max(self.len, min_capacity)) + } else { + Ok(()) + } + } + /// Converts the vector into [`Box<[T]>`][owned slice]. /// /// Before doing the conversion, this method discards excess capacity like [`shrink_to_fit`]. diff --git a/alloc/src/vec/spec_extend.rs b/alloc/src/vec/spec_extend.rs index 7c908841c90ec..de6ef3d803263 100644 --- a/alloc/src/vec/spec_extend.rs +++ b/alloc/src/vec/spec_extend.rs @@ -1,6 +1,6 @@ use core::clone::TrivialClone; use core::iter::TrustedLen; -use core::slice::{self}; +use core::slice; use super::{IntoIter, Vec}; use crate::alloc::Allocator; diff --git a/alloc/src/vec/spec_from_iter.rs b/alloc/src/vec/spec_from_iter.rs index e1f0b639bdfd6..ccbc2936fb4e8 100644 --- a/alloc/src/vec/spec_from_iter.rs +++ b/alloc/src/vec/spec_from_iter.rs @@ -1,5 +1,5 @@ use core::mem::ManuallyDrop; -use core::ptr::{self}; +use core::ptr; use super::{IntoIter, SpecExtend, SpecFromIterNested, Vec}; diff --git a/alloc/src/vec/splice.rs b/alloc/src/vec/splice.rs index 46611f611dc2c..3eb8ca44a9d14 100644 --- a/alloc/src/vec/splice.rs +++ b/alloc/src/vec/splice.rs @@ -1,5 +1,4 @@ -use core::ptr::{self}; -use core::slice::{self}; +use core::{ptr, slice}; use super::{Drain, Vec}; use crate::alloc::{Allocator, Global}; diff --git a/alloctests/lib.rs b/alloctests/lib.rs index fe14480102e32..e09d8495fdeac 100644 --- a/alloctests/lib.rs +++ b/alloctests/lib.rs @@ -16,8 +16,6 @@ // tidy-alphabetical-start #![feature(allocator_api)] #![feature(array_into_iter_constructors)] -#![feature(assert_matches)] -#![feature(box_vec_non_null)] #![feature(char_internals)] #![feature(const_alloc_error)] #![feature(const_cmp)] @@ -56,16 +54,12 @@ // // Language features: // tidy-alphabetical-start -#![feature(cfg_sanitize)] #![feature(const_trait_impl)] #![feature(dropck_eyepatch)] -#![feature(lang_items)] #![feature(min_specialization)] -#![feature(negative_impls)] #![feature(never_type)] #![feature(optimize_attribute)] #![feature(prelude_import)] -#![feature(rustc_allow_const_fn_unstable)] #![feature(rustc_attrs)] #![feature(staged_api)] #![feature(test)] diff --git a/alloctests/tests/lib.rs b/alloctests/tests/lib.rs index e15c86496cf1b..60b26126cf6be 100644 --- a/alloctests/tests/lib.rs +++ b/alloctests/tests/lib.rs @@ -1,10 +1,9 @@ #![feature(allocator_api)] #![feature(binary_heap_pop_if)] +#![feature(btree_merge)] #![feature(const_heap)] #![feature(deque_extend_front)] #![feature(iter_array_chunks)] -#![feature(assert_matches)] -#![feature(wtf8_internals)] #![feature(cow_is_borrowed)] #![feature(core_intrinsics)] #![feature(downcast_unchecked)] @@ -31,8 +30,6 @@ #![feature(string_remove_matches)] #![feature(const_btree_len)] #![feature(const_trait_impl)] -#![feature(panic_update_hook)] -#![feature(pointer_is_aligned_to)] #![feature(test)] #![feature(thin_box)] #![feature(drain_keep_rest)] diff --git a/alloctests/tests/str.rs b/alloctests/tests/str.rs index fcc4aaaa1dcd1..52cc8afeee903 100644 --- a/alloctests/tests/str.rs +++ b/alloctests/tests/str.rs @@ -612,14 +612,14 @@ mod slice_index { data: "abcdef"; good: data[4..4] == ""; bad: data[4..3]; - message: "begin <= end (4 <= 3)"; + message: "begin > end (4 > 3)"; } in mod rangeinclusive_neg_width { data: "abcdef"; good: data[4..=3] == ""; bad: data[4..=2]; - message: "begin <= end (4 <= 3)"; + message: "begin > end (4 > 3)"; } } @@ -630,13 +630,13 @@ mod slice_index { // note: using 0 specifically ensures that the result of overflowing is 0..0, // so that `get` doesn't simply return None for the wrong reason. bad: data[0..=usize::MAX]; - message: "maximum usize"; + message: "out of bounds"; } in mod rangetoinclusive { data: "hello"; bad: data[..=usize::MAX]; - message: "maximum usize"; + message: "out of bounds"; } } } @@ -659,49 +659,49 @@ mod slice_index { data: super::DATA; bad: data[super::BAD_START..super::GOOD_END]; message: - "byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; + "start byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; } in mod range_2 { data: super::DATA; bad: data[super::GOOD_START..super::BAD_END]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; } in mod rangefrom { data: super::DATA; bad: data[super::BAD_START..]; message: - "byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; + "start byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; } in mod rangeto { data: super::DATA; bad: data[..super::BAD_END]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; } in mod rangeinclusive_1 { data: super::DATA; bad: data[super::BAD_START..=super::GOOD_END_INCL]; message: - "byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; + "start byte index 4 is not a char boundary; it is inside 'α' (bytes 3..5) of"; } in mod rangeinclusive_2 { data: super::DATA; bad: data[super::GOOD_START..=super::BAD_END_INCL]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; } in mod rangetoinclusive { data: super::DATA; bad: data[..=super::BAD_END_INCL]; message: - "byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; + "end byte index 6 is not a char boundary; it is inside 'β' (bytes 5..7) of"; } } } @@ -716,7 +716,9 @@ mod slice_index { // check the panic includes the prefix of the sliced string #[test] - #[should_panic(expected = "byte index 1024 is out of bounds of `Lorem ipsum dolor sit amet")] + #[should_panic( + expected = "end byte index 1024 is out of bounds of `Lorem ipsum dolor sit amet" + )] fn test_slice_fail_truncated_1() { let _ = &LOREM_PARAGRAPH[..1024]; } diff --git a/compiler-builtins/.github/workflows/main.yaml b/compiler-builtins/.github/workflows/main.yaml index 699a9c417ddef..3fed58f2a207d 100644 --- a/compiler-builtins/.github/workflows/main.yaml +++ b/compiler-builtins/.github/workflows/main.yaml @@ -70,12 +70,14 @@ jobs: os: ubuntu-24.04 - target: powerpc64le-unknown-linux-gnu os: ubuntu-24.04 - - target: powerpc64le-unknown-linux-gnu - os: ubuntu-24.04-ppc64le + # - target: powerpc64le-unknown-linux-gnu + # os: ubuntu-24.04-ppc64le + # # FIXME(rust#151807): remove once PPC builds work again. + # channel: nightly-2026-01-23 - target: riscv64gc-unknown-linux-gnu os: ubuntu-24.04 - - target: s390x-unknown-linux-gnu - os: ubuntu-24.04-s390x + # - target: s390x-unknown-linux-gnu + # os: ubuntu-24.04-s390x - target: thumbv6m-none-eabi os: ubuntu-24.04 - target: thumbv7em-none-eabi @@ -228,7 +230,27 @@ jobs: # poorly with build scripts) cargo build -p compiler_builtins -p libm \ --target etc/thumbv7em-none-eabi-renamed.json \ - -Zbuild-std=core + -Zbuild-std=core \ + -Zjson-target-spec + + # FIXME: move this target to test job once https://github.com/rust-lang/rust/pull/150138 merged. + build-thumbv6k: + name: Build thumbv6k + runs-on: ubuntu-24.04 + timeout-minutes: 10 + steps: + - uses: actions/checkout@v4 + - name: Install Rust + run: | + rustup update nightly --no-self-update + rustup default nightly + rustup component add rust-src + - uses: Swatinem/rust-cache@v2 + - run: | + cargo build -p compiler_builtins -p libm \ + --target etc/thumbv6-none-eabi.json \ + -Zbuild-std=core \ + -Zjson-target-spec benchmarks: name: Benchmarks @@ -354,6 +376,7 @@ jobs: needs: - benchmarks - build-custom + - build-thumbv6k - clippy - extensive - miri diff --git a/compiler-builtins/.github/workflows/rustc-pull.yml b/compiler-builtins/.github/workflows/rustc-pull.yml index 617db14f46eea..8e88213332de4 100644 --- a/compiler-builtins/.github/workflows/rustc-pull.yml +++ b/compiler-builtins/.github/workflows/rustc-pull.yml @@ -7,6 +7,9 @@ on: # Run at 04:00 UTC every Monday and Thursday - cron: '0 4 * * 1,4' +env: + JOSH_SYNC_VERBOSE: true + jobs: pull: if: github.repository == 'rust-lang/compiler-builtins' diff --git a/compiler-builtins/Cargo.toml b/compiler-builtins/Cargo.toml index 8501f4e630b55..26f67e02fc520 100644 --- a/compiler-builtins/Cargo.toml +++ b/compiler-builtins/Cargo.toml @@ -31,6 +31,39 @@ exclude = [ "compiler-builtins", ] +[workspace.dependencies] +anyhow = "1.0.101" +assert_cmd = "2.1.2" +cc = "1.2.55" +compiler_builtins = { path = "builtins-shim", default-features = false } +criterion = { version = "0.6.0", default-features = false, features = ["cargo_bench_support"] } +getrandom = "0.3.4" +gmp-mpfr-sys = { version = "1.6.8", default-features = false } +gungraun = "0.17.0" +heck = "0.5.0" +indicatif = { version = "0.18.3", default-features = false } +libm = { path = "libm", default-features = false } +libm-macros = { path = "crates/libm-macros" } +libm-test = { path = "libm-test", default-features = false } +libtest-mimic = "0.8.1" +musl-math-sys = { path = "crates/musl-math-sys" } +no-panic = "0.1.35" +object = { version = "0.37.3", features = ["wasm"] } +panic-handler = { path = "crates/panic-handler" } +paste = "1.0.15" +proc-macro2 = "1.0.106" +quote = "1.0.44" +rand = "0.9.2" +rand_chacha = "0.9.0" +rand_xoshiro = "0.7" +rayon = "1.11.0" +regex = "1.12.3" +rug = { version = "1.28.1", default-features = false, features = ["float", "integer", "std"] } +rustc_apfloat = "0.2.3" +serde_json = "1.0.149" +syn = "2.0.114" +tempfile = "3.24.0" + [profile.release] panic = "abort" @@ -51,6 +84,7 @@ codegen-units = 1 lto = "fat" [profile.bench] +codegen-units = 1 # Required for gungraun debug = true strip = false diff --git a/compiler-builtins/builtins-shim/Cargo.toml b/compiler-builtins/builtins-shim/Cargo.toml index 746d5b21dc3f1..37d3407e9f668 100644 --- a/compiler-builtins/builtins-shim/Cargo.toml +++ b/compiler-builtins/builtins-shim/Cargo.toml @@ -7,6 +7,9 @@ # manifest that is identical except for the `core` dependency and forwards # to the same sources, which acts as the `compiler-builtins` Cargo entrypoint # for out of tree testing +# +# Ideally we can eventually replace this with a patch in the workspace +# manifest . [package] name = "compiler_builtins" @@ -33,7 +36,7 @@ doctest = false test = false [build-dependencies] -cc = { optional = true, version = "1.2" } +cc = { version = "1.2", optional = true } [features] default = ["compiler-builtins"] diff --git a/compiler-builtins/builtins-test/Cargo.toml b/compiler-builtins/builtins-test/Cargo.toml index 550f736a76dbb..9395ab1a985e5 100644 --- a/compiler-builtins/builtins-test/Cargo.toml +++ b/compiler-builtins/builtins-test/Cargo.toml @@ -6,23 +6,22 @@ publish = false license = "MIT AND Apache-2.0 WITH LLVM-exception AND (MIT OR Apache-2.0)" [dependencies] +compiler_builtins = { workspace = true, features = ["unstable-public-internals"] } + # For fuzzing tests we want a deterministic seedable RNG. We also eliminate potential # problems with system RNGs on the variety of platforms this crate is tested on. # `xoshiro128**` is used for its quality, size, and speed at generating `u32` shift amounts. -rand_xoshiro = "0.7" +rand_xoshiro.workspace = true + # To compare float builtins against -rustc_apfloat = "0.2.3" -# Really a dev dependency, but dev dependencies can't be optional -gungraun = { version = "0.17.0", optional = true } +rustc_apfloat.workspace = true -[dependencies.compiler_builtins] -path = "../builtins-shim" -default-features = false -features = ["unstable-public-internals"] +# Really a dev dependency, but dev dependencies can't be optional +gungraun = { workspace = true, optional = true } [dev-dependencies] -criterion = { version = "0.6.0", default-features = false, features = ["cargo_bench_support"] } -paste = "1.0.15" +criterion.workspace = true +paste.workspace = true [target.'cfg(all(target_arch = "arm", not(any(target_env = "gnu", target_env = "musl")), target_os = "linux"))'.dev-dependencies] test = { git = "https://github.com/japaric/utest" } diff --git a/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile index 69b99f5b6b328..683bd07fd47ef 100644 --- a/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/aarch64-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-aarch64-linux-gnu m4 make libc6-dev-arm64-cross \ - qemu-user-static + qemu-user ENV TOOLCHAIN_PREFIX=aarch64-linux-gnu- ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-aarch64-static \ + CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-aarch64 \ AR_aarch64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_aarch64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/aarch64-linux-gnu \ diff --git a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile index 2fa6f85205206..781abd1b6e888 100644 --- a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile +++ b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabi/Dockerfile @@ -1,14 +1,14 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ - gcc-arm-linux-gnueabi libc6-dev-armel-cross qemu-user-static + gcc-arm-linux-gnueabi libc6-dev-armel-cross qemu-user ENV TOOLCHAIN_PREFIX=arm-linux-gnueabi- ENV CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABI_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABI_RUNNER=qemu-arm-static \ + CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABI_RUNNER=qemu-arm \ AR_arm_unknown_linux_gnueabi="$TOOLCHAIN_PREFIX"ar \ CC_arm_unknown_linux_gnueabi="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/arm-linux-gnueabi \ diff --git a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile index 85f7335f5a85b..36ea4827dc52f 100644 --- a/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile +++ b/compiler-builtins/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile @@ -1,14 +1,14 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ - gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user-static + gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user ENV TOOLCHAIN_PREFIX=arm-linux-gnueabihf- ENV CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm-static \ + CARGO_TARGET_ARM_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm \ AR_arm_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"ar \ CC_arm_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/arm-linux-gnueabihf \ diff --git a/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile b/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile index 42511479f36ff..8b76693b2799e 100644 --- a/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile +++ b/compiler-builtins/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile @@ -1,14 +1,14 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ - gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user-static + gcc-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user ENV TOOLCHAIN_PREFIX=arm-linux-gnueabihf- ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm-static \ + CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER=qemu-arm \ AR_armv7_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"ar \ CC_armv7_unknown_linux_gnueabihf="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/arm-linux-gnueabihf \ diff --git a/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile index 35488c4774933..9125038acbde5 100644 --- a/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/i586-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile index 35488c4774933..9125038acbde5 100644 --- a/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/i686-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile index e95a1b9163ff9..a652235958777 100644 --- a/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile @@ -1,13 +1,13 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-14-loongarch64-linux-gnu libc6-dev-loong64-cross ENV CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_LINKER=loongarch64-linux-gnu-gcc-14 \ - CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-loongarch64-static \ + CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_RUNNER=qemu-loongarch64 \ AR_loongarch64_unknown_linux_gnu=loongarch64-linux-gnu-ar \ CC_loongarch64_unknown_linux_gnu=loongarch64-linux-gnu-gcc-14 \ QEMU_LD_PREFIX=/usr/loongarch64-linux-gnu \ diff --git a/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile index fd1877603100a..0913f33c05ce4 100644 --- a/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/mips-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-mips-linux-gnu libc6-dev-mips-cross \ - binfmt-support qemu-user-static qemu-system-mips + binfmt-support qemu-user qemu-system-mips ENV TOOLCHAIN_PREFIX=mips-linux-gnu- ENV CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_RUNNER=qemu-mips-static \ + CARGO_TARGET_MIPS_UNKNOWN_LINUX_GNU_RUNNER=qemu-mips \ AR_mips_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_mips_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mips-linux-gnu \ diff --git a/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile b/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile index 4e542ce6858c3..d2f4e484b1aab 100644 --- a/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile +++ b/compiler-builtins/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ @@ -8,12 +8,12 @@ RUN apt-get update && \ gcc-mips64-linux-gnuabi64 \ libc6-dev \ libc6-dev-mips64-cross \ - qemu-user-static \ + qemu-user \ qemu-system-mips ENV TOOLCHAIN_PREFIX=mips64-linux-gnuabi64- ENV CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64-static \ + CARGO_TARGET_MIPS64_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64 \ AR_mips64_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"ar \ CC_mips64_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mips64-linux-gnuabi64 \ diff --git a/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile b/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile index 528dfd8940d5e..873754b2793e9 100644 --- a/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile +++ b/compiler-builtins/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ @@ -8,11 +8,11 @@ RUN apt-get update && \ gcc-mips64el-linux-gnuabi64 \ libc6-dev \ libc6-dev-mips64el-cross \ - qemu-user-static + qemu-user ENV TOOLCHAIN_PREFIX=mips64el-linux-gnuabi64- ENV CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64el-static \ + CARGO_TARGET_MIPS64EL_UNKNOWN_LINUX_GNUABI64_RUNNER=qemu-mips64el \ AR_mips64el_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"ar \ CC_mips64el_unknown_linux_gnuabi64="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mips64el-linux-gnuabi64 \ diff --git a/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile index 2572180238e23..5768b68d6c950 100644 --- a/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/mipsel-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-mipsel-linux-gnu libc6-dev-mipsel-cross \ - binfmt-support qemu-user-static + binfmt-support qemu-user ENV TOOLCHAIN_PREFIX=mipsel-linux-gnu- ENV CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_GNU_RUNNER=qemu-mipsel-static \ + CARGO_TARGET_MIPSEL_UNKNOWN_LINUX_GNU_RUNNER=qemu-mipsel \ AR_mipsel_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_mipsel_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/mipsel-linux-gnu \ diff --git a/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile index cac1f23610aa9..c625a4bcd5d7c 100644 --- a/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/powerpc-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-powerpc-linux-gnu libc6-dev-powerpc-cross \ qemu-system-ppc ENV TOOLCHAIN_PREFIX=powerpc-linux-gnu- ENV CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc-static \ + CARGO_TARGET_POWERPC_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc \ AR_powerpc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_powerpc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/powerpc-linux-gnu \ diff --git a/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile index 76127b7dbb8c1..86a7a8cd46e4e 100644 --- a/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ gcc libc6-dev ca-certificates \ gcc-powerpc64-linux-gnu libc6-dev-ppc64-cross \ - binfmt-support qemu-user-static qemu-system-ppc + binfmt-support qemu-user qemu-system-ppc ENV TOOLCHAIN_PREFIX=powerpc64-linux-gnu- ENV CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64-static \ + CARGO_TARGET_POWERPC64_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64 \ AR_powerpc64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_powerpc64_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/powerpc64-linux-gnu \ diff --git a/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile index da1d56ca66f27..722b10b0a7349 100644 --- a/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-powerpc64le-linux-gnu libc6-dev-ppc64el-cross \ qemu-system-ppc ENV TOOLCHAIN_PREFIX=powerpc64le-linux-gnu- ENV CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64le-static \ + CARGO_TARGET_POWERPC64LE_UNKNOWN_LINUX_GNU_RUNNER=qemu-ppc64le \ AR_powerpc64le_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_powerpc64le_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/powerpc64le-linux-gnu \ diff --git a/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile index 513efacd6d968..7a721ba05416e 100644 --- a/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile @@ -1,15 +1,15 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ apt-get install -y --no-install-recommends \ - gcc libc6-dev qemu-user-static ca-certificates \ + gcc libc6-dev qemu-user ca-certificates \ gcc-riscv64-linux-gnu libc6-dev-riscv64-cross \ qemu-system-riscv64 ENV TOOLCHAIN_PREFIX=riscv64-linux-gnu- ENV CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_LINKER="$TOOLCHAIN_PREFIX"gcc \ - CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUNNER=qemu-riscv64-static \ + CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_RUNNER=qemu-riscv64 \ AR_riscv64gc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"ar \ CC_riscv64gc_unknown_linux_gnu="$TOOLCHAIN_PREFIX"gcc \ QEMU_LD_PREFIX=/usr/riscv64-linux-gnu \ diff --git a/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile b/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile index a9a172a21137d..a1a6b3cf5cfd2 100644 --- a/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv6m-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile b/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile index a9a172a21137d..a1a6b3cf5cfd2 100644 --- a/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv7em-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile b/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile index a9a172a21137d..a1a6b3cf5cfd2 100644 --- a/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv7em-none-eabihf/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile b/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile index a9a172a21137d..a1a6b3cf5cfd2 100644 --- a/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile +++ b/compiler-builtins/ci/docker/thumbv7m-none-eabi/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile b/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile index 2813d318670ea..b646a72bb37cc 100644 --- a/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile +++ b/compiler-builtins/ci/docker/wasm32-unknown-unknown/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:20.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile b/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile index 2ef800129d675..927515f90f329 100644 --- a/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile +++ b/compiler-builtins/ci/docker/x86_64-unknown-linux-gnu/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE=ubuntu:25.04 +ARG IMAGE=ubuntu:25.10 FROM $IMAGE RUN apt-get update && \ diff --git a/compiler-builtins/ci/run-docker.sh b/compiler-builtins/ci/run-docker.sh index 4c1fe0fe26445..e65ada271904f 100755 --- a/compiler-builtins/ci/run-docker.sh +++ b/compiler-builtins/ci/run-docker.sh @@ -97,7 +97,7 @@ if [ "${1:-}" = "--help" ] || [ "$#" -gt 1 ]; then usage: ./ci/run-docker.sh [target] you can also set DOCKER_BASE_IMAGE to use something other than the default - ubuntu:25.04 (or rustlang/rust:nightly). + ubuntu:25.10 (or rustlang/rust:nightly). " exit fi diff --git a/compiler-builtins/ci/run.sh b/compiler-builtins/ci/run.sh index 0c07b32c74b93..12b3f37889c99 100755 --- a/compiler-builtins/ci/run.sh +++ b/compiler-builtins/ci/run.sh @@ -13,11 +13,6 @@ if [ -z "$target" ]; then target="$host_target" fi -if [[ "$target" = *"wasm"* ]]; then - # Enable the random backend - export RUSTFLAGS="${RUSTFLAGS:-} --cfg getrandom_backend=\"wasm_js\"" -fi - if [ "${USING_CONTAINER_RUSTC:-}" = 1 ]; then # Install nonstandard components if we have control of the environment rustup target list --installed | @@ -51,8 +46,8 @@ fi # Ensure there are no duplicate symbols or references to `core` when # `compiler-builtins` is built with various features. Symcheck invokes Cargo to # build with the arguments we provide it, then validates the built artifacts. +SYMCHECK_TEST_TARGET="$target" cargo test -p symbol-check --release symcheck=(cargo run -p symbol-check --release) -[[ "$target" = "wasm"* ]] && symcheck+=(--features wasm) symcheck+=(-- build-and-check) "${symcheck[@]}" "$target" -- -p compiler_builtins @@ -157,7 +152,8 @@ if [ "${BUILD_ONLY:-}" = "1" ]; then echo "can't run tests on $target; skipping" else - mflags+=(--workspace --target "$target") + # symcheck tests need specific env setup, and is already tested above + mflags+=(--workspace --exclude symbol-check --target "$target") cmd=(cargo test "${mflags[@]}") profile_flag="--profile" diff --git a/compiler-builtins/compiler-builtins/Cargo.toml b/compiler-builtins/compiler-builtins/Cargo.toml index 496dde2d4cf25..a8b8920421b3e 100644 --- a/compiler-builtins/compiler-builtins/Cargo.toml +++ b/compiler-builtins/compiler-builtins/Cargo.toml @@ -31,7 +31,7 @@ doc = false core = { path = "../../core", optional = true } [build-dependencies] -cc = { optional = true, version = "1.2" } +cc = { version = "1.2", optional = true } [features] default = ["compiler-builtins"] diff --git a/compiler-builtins/compiler-builtins/src/hexagon/dffma.s b/compiler-builtins/compiler-builtins/src/hexagon/dffma.s index 97d05eb1839ee..6cd1f1b79f87a 100644 --- a/compiler-builtins/compiler-builtins/src/hexagon/dffma.s +++ b/compiler-builtins/compiler-builtins/src/hexagon/dffma.s @@ -7,7 +7,7 @@ .p2align 5 __hexagon_fmadf4: __hexagon_fmadf5: -fma: +.Lfma: { p0 = dfclass(r1:0,#2) p0 = dfclass(r3:2,#2) @@ -400,7 +400,7 @@ fma: r3:2 = insert(r11:10,#63,#0) r1 -= asl(r28,#20) } - jump fma + jump .Lfma .Lfma_ab_tiny: r9:8 = combine(##0x00100000,#0) @@ -408,7 +408,7 @@ fma: r1:0 = insert(r9:8,#63,#0) r3:2 = insert(r9:8,#63,#0) } - jump fma + jump .Lfma .Lab_inf: { @@ -531,4 +531,3 @@ fma: r5 = insert(r28,#11,#20) jump .Lfma_abnormal_c_restart } -.size fma,.-fma diff --git a/compiler-builtins/compiler-builtins/src/lib.rs b/compiler-builtins/compiler-builtins/src/lib.rs index 342427aca9c7d..80395a4738eb2 100644 --- a/compiler-builtins/compiler-builtins/src/lib.rs +++ b/compiler-builtins/compiler-builtins/src/lib.rs @@ -11,11 +11,11 @@ #![feature(repr_simd)] #![feature(macro_metavar_expr_concat)] #![feature(rustc_attrs)] -#![feature(float_bits_const)] #![cfg_attr(f16_enabled, feature(f16))] #![cfg_attr(f128_enabled, feature(f128))] #![no_builtins] #![no_std] +#![allow(unstable_name_collisions)] // FIXME(float_bits_const): remove when stable #![allow(unused_features)] #![allow(internal_features)] // `mem::swap` cannot be used because it may generate references to memcpy in unoptimized code. @@ -46,6 +46,7 @@ pub mod float; pub mod int; pub mod math; pub mod mem; +pub mod sync; // `libm` expects its `support` module to be available in the crate root. use math::libm_math::support; @@ -59,13 +60,6 @@ pub mod aarch64; #[cfg(all(target_arch = "aarch64", target_feature = "outline-atomics"))] pub mod aarch64_outline_atomics; -#[cfg(all( - kernel_user_helpers, - any(target_os = "linux", target_os = "android"), - target_arch = "arm" -))] -pub mod arm_linux; - #[cfg(target_arch = "avr")] pub mod avr; diff --git a/compiler-builtins/compiler-builtins/src/arm_linux.rs b/compiler-builtins/compiler-builtins/src/sync/arm_linux.rs similarity index 59% rename from compiler-builtins/compiler-builtins/src/arm_linux.rs rename to compiler-builtins/compiler-builtins/src/sync/arm_linux.rs index ab9f868073908..7edd76c0b8b7c 100644 --- a/compiler-builtins/compiler-builtins/src/arm_linux.rs +++ b/compiler-builtins/compiler-builtins/src/sync/arm_linux.rs @@ -125,14 +125,16 @@ unsafe fn atomic_cmpxchg(ptr: *mut T, oldval: u32, newval: u32) -> u32 { let (shift, mask) = get_shift_mask(ptr); loop { - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. let curval_aligned = unsafe { atomic_load_aligned::(aligned_ptr) }; let curval = extract_aligned(curval_aligned, shift, mask); if curval != oldval { return curval; } let newval_aligned = insert_aligned(curval_aligned, newval, shift, mask); - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. if unsafe { __kuser_cmpxchg(curval_aligned, newval_aligned, aligned_ptr) } { return oldval; } @@ -143,7 +145,8 @@ macro_rules! atomic_rmw { ($name:ident, $ty:ty, $op:expr, $fetch:expr) => { intrinsics! { pub unsafe extern "C" fn $name(ptr: *mut $ty, val: $ty) -> $ty { - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. unsafe { atomic_rmw( ptr, @@ -167,140 +170,15 @@ macro_rules! atomic_cmpxchg { ($name:ident, $ty:ty) => { intrinsics! { pub unsafe extern "C" fn $name(ptr: *mut $ty, oldval: $ty, newval: $ty) -> $ty { - // FIXME(safety): preconditions review needed + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. unsafe { atomic_cmpxchg(ptr, oldval as u32, newval as u32) as $ty } } } }; } -atomic_rmw!(@old __sync_fetch_and_add_1, u8, |a: u8, b: u8| a.wrapping_add(b)); -atomic_rmw!(@old __sync_fetch_and_add_2, u16, |a: u16, b: u16| a - .wrapping_add(b)); -atomic_rmw!(@old __sync_fetch_and_add_4, u32, |a: u32, b: u32| a - .wrapping_add(b)); - -atomic_rmw!(@new __sync_add_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_add(b)); -atomic_rmw!(@new __sync_add_and_fetch_2, u16, |a: u16, b: u16| a - .wrapping_add(b)); -atomic_rmw!(@new __sync_add_and_fetch_4, u32, |a: u32, b: u32| a - .wrapping_add(b)); - -atomic_rmw!(@old __sync_fetch_and_sub_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); -atomic_rmw!(@old __sync_fetch_and_sub_2, u16, |a: u16, b: u16| a - .wrapping_sub(b)); -atomic_rmw!(@old __sync_fetch_and_sub_4, u32, |a: u32, b: u32| a - .wrapping_sub(b)); - -atomic_rmw!(@new __sync_sub_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); -atomic_rmw!(@new __sync_sub_and_fetch_2, u16, |a: u16, b: u16| a - .wrapping_sub(b)); -atomic_rmw!(@new __sync_sub_and_fetch_4, u32, |a: u32, b: u32| a - .wrapping_sub(b)); - -atomic_rmw!(@old __sync_fetch_and_and_1, u8, |a: u8, b: u8| a & b); -atomic_rmw!(@old __sync_fetch_and_and_2, u16, |a: u16, b: u16| a & b); -atomic_rmw!(@old __sync_fetch_and_and_4, u32, |a: u32, b: u32| a & b); - -atomic_rmw!(@new __sync_and_and_fetch_1, u8, |a: u8, b: u8| a & b); -atomic_rmw!(@new __sync_and_and_fetch_2, u16, |a: u16, b: u16| a & b); -atomic_rmw!(@new __sync_and_and_fetch_4, u32, |a: u32, b: u32| a & b); - -atomic_rmw!(@old __sync_fetch_and_or_1, u8, |a: u8, b: u8| a | b); -atomic_rmw!(@old __sync_fetch_and_or_2, u16, |a: u16, b: u16| a | b); -atomic_rmw!(@old __sync_fetch_and_or_4, u32, |a: u32, b: u32| a | b); - -atomic_rmw!(@new __sync_or_and_fetch_1, u8, |a: u8, b: u8| a | b); -atomic_rmw!(@new __sync_or_and_fetch_2, u16, |a: u16, b: u16| a | b); -atomic_rmw!(@new __sync_or_and_fetch_4, u32, |a: u32, b: u32| a | b); - -atomic_rmw!(@old __sync_fetch_and_xor_1, u8, |a: u8, b: u8| a ^ b); -atomic_rmw!(@old __sync_fetch_and_xor_2, u16, |a: u16, b: u16| a ^ b); -atomic_rmw!(@old __sync_fetch_and_xor_4, u32, |a: u32, b: u32| a ^ b); - -atomic_rmw!(@new __sync_xor_and_fetch_1, u8, |a: u8, b: u8| a ^ b); -atomic_rmw!(@new __sync_xor_and_fetch_2, u16, |a: u16, b: u16| a ^ b); -atomic_rmw!(@new __sync_xor_and_fetch_4, u32, |a: u32, b: u32| a ^ b); - -atomic_rmw!(@old __sync_fetch_and_nand_1, u8, |a: u8, b: u8| !(a & b)); -atomic_rmw!(@old __sync_fetch_and_nand_2, u16, |a: u16, b: u16| !(a & b)); -atomic_rmw!(@old __sync_fetch_and_nand_4, u32, |a: u32, b: u32| !(a & b)); - -atomic_rmw!(@new __sync_nand_and_fetch_1, u8, |a: u8, b: u8| !(a & b)); -atomic_rmw!(@new __sync_nand_and_fetch_2, u16, |a: u16, b: u16| !(a & b)); -atomic_rmw!(@new __sync_nand_and_fetch_4, u32, |a: u32, b: u32| !(a & b)); - -atomic_rmw!(@old __sync_fetch_and_max_1, i8, |a: i8, b: i8| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_max_2, i16, |a: i16, b: i16| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_max_4, i32, |a: i32, b: i32| if a > b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_fetch_and_umax_1, u8, |a: u8, b: u8| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umax_2, u16, |a: u16, b: u16| if a > b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umax_4, u32, |a: u32, b: u32| if a > b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_fetch_and_min_1, i8, |a: i8, b: i8| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_min_2, i16, |a: i16, b: i16| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_min_4, i32, |a: i32, b: i32| if a < b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_fetch_and_umin_1, u8, |a: u8, b: u8| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umin_2, u16, |a: u16, b: u16| if a < b { - a -} else { - b -}); -atomic_rmw!(@old __sync_fetch_and_umin_4, u32, |a: u32, b: u32| if a < b { - a -} else { - b -}); - -atomic_rmw!(@old __sync_lock_test_and_set_1, u8, |_: u8, b: u8| b); -atomic_rmw!(@old __sync_lock_test_and_set_2, u16, |_: u16, b: u16| b); -atomic_rmw!(@old __sync_lock_test_and_set_4, u32, |_: u32, b: u32| b); - -atomic_cmpxchg!(__sync_val_compare_and_swap_1, u8); -atomic_cmpxchg!(__sync_val_compare_and_swap_2, u16); -atomic_cmpxchg!(__sync_val_compare_and_swap_4, u32); +include!("arm_thumb_shared.rs"); intrinsics! { pub unsafe extern "C" fn __sync_synchronize() { diff --git a/compiler-builtins/compiler-builtins/src/sync/arm_thumb_shared.rs b/compiler-builtins/compiler-builtins/src/sync/arm_thumb_shared.rs new file mode 100644 index 0000000000000..812989c7bc85a --- /dev/null +++ b/compiler-builtins/compiler-builtins/src/sync/arm_thumb_shared.rs @@ -0,0 +1,134 @@ +// Used by both arm_linux.rs and thumbv6k.rs. + +// References: +// - https://llvm.org/docs/Atomics.html#libcalls-sync +// - https://gcc.gnu.org/onlinedocs/gcc/_005f_005fsync-Builtins.html +// - https://refspecs.linuxfoundation.org/elf/IA64-SysV-psABI.pdf#page=58 + +atomic_rmw!(@old __sync_fetch_and_add_1, u8, |a: u8, b: u8| a.wrapping_add(b)); +atomic_rmw!(@old __sync_fetch_and_add_2, u16, |a: u16, b: u16| a + .wrapping_add(b)); +atomic_rmw!(@old __sync_fetch_and_add_4, u32, |a: u32, b: u32| a + .wrapping_add(b)); + +atomic_rmw!(@new __sync_add_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_add(b)); +atomic_rmw!(@new __sync_add_and_fetch_2, u16, |a: u16, b: u16| a + .wrapping_add(b)); +atomic_rmw!(@new __sync_add_and_fetch_4, u32, |a: u32, b: u32| a + .wrapping_add(b)); + +atomic_rmw!(@old __sync_fetch_and_sub_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); +atomic_rmw!(@old __sync_fetch_and_sub_2, u16, |a: u16, b: u16| a + .wrapping_sub(b)); +atomic_rmw!(@old __sync_fetch_and_sub_4, u32, |a: u32, b: u32| a + .wrapping_sub(b)); + +atomic_rmw!(@new __sync_sub_and_fetch_1, u8, |a: u8, b: u8| a.wrapping_sub(b)); +atomic_rmw!(@new __sync_sub_and_fetch_2, u16, |a: u16, b: u16| a + .wrapping_sub(b)); +atomic_rmw!(@new __sync_sub_and_fetch_4, u32, |a: u32, b: u32| a + .wrapping_sub(b)); + +atomic_rmw!(@old __sync_fetch_and_and_1, u8, |a: u8, b: u8| a & b); +atomic_rmw!(@old __sync_fetch_and_and_2, u16, |a: u16, b: u16| a & b); +atomic_rmw!(@old __sync_fetch_and_and_4, u32, |a: u32, b: u32| a & b); + +atomic_rmw!(@new __sync_and_and_fetch_1, u8, |a: u8, b: u8| a & b); +atomic_rmw!(@new __sync_and_and_fetch_2, u16, |a: u16, b: u16| a & b); +atomic_rmw!(@new __sync_and_and_fetch_4, u32, |a: u32, b: u32| a & b); + +atomic_rmw!(@old __sync_fetch_and_or_1, u8, |a: u8, b: u8| a | b); +atomic_rmw!(@old __sync_fetch_and_or_2, u16, |a: u16, b: u16| a | b); +atomic_rmw!(@old __sync_fetch_and_or_4, u32, |a: u32, b: u32| a | b); + +atomic_rmw!(@new __sync_or_and_fetch_1, u8, |a: u8, b: u8| a | b); +atomic_rmw!(@new __sync_or_and_fetch_2, u16, |a: u16, b: u16| a | b); +atomic_rmw!(@new __sync_or_and_fetch_4, u32, |a: u32, b: u32| a | b); + +atomic_rmw!(@old __sync_fetch_and_xor_1, u8, |a: u8, b: u8| a ^ b); +atomic_rmw!(@old __sync_fetch_and_xor_2, u16, |a: u16, b: u16| a ^ b); +atomic_rmw!(@old __sync_fetch_and_xor_4, u32, |a: u32, b: u32| a ^ b); + +atomic_rmw!(@new __sync_xor_and_fetch_1, u8, |a: u8, b: u8| a ^ b); +atomic_rmw!(@new __sync_xor_and_fetch_2, u16, |a: u16, b: u16| a ^ b); +atomic_rmw!(@new __sync_xor_and_fetch_4, u32, |a: u32, b: u32| a ^ b); + +atomic_rmw!(@old __sync_fetch_and_nand_1, u8, |a: u8, b: u8| !(a & b)); +atomic_rmw!(@old __sync_fetch_and_nand_2, u16, |a: u16, b: u16| !(a & b)); +atomic_rmw!(@old __sync_fetch_and_nand_4, u32, |a: u32, b: u32| !(a & b)); + +atomic_rmw!(@new __sync_nand_and_fetch_1, u8, |a: u8, b: u8| !(a & b)); +atomic_rmw!(@new __sync_nand_and_fetch_2, u16, |a: u16, b: u16| !(a & b)); +atomic_rmw!(@new __sync_nand_and_fetch_4, u32, |a: u32, b: u32| !(a & b)); + +atomic_rmw!(@old __sync_fetch_and_max_1, i8, |a: i8, b: i8| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_max_2, i16, |a: i16, b: i16| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_max_4, i32, |a: i32, b: i32| if a > b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_fetch_and_umax_1, u8, |a: u8, b: u8| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umax_2, u16, |a: u16, b: u16| if a > b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umax_4, u32, |a: u32, b: u32| if a > b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_fetch_and_min_1, i8, |a: i8, b: i8| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_min_2, i16, |a: i16, b: i16| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_min_4, i32, |a: i32, b: i32| if a < b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_fetch_and_umin_1, u8, |a: u8, b: u8| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umin_2, u16, |a: u16, b: u16| if a < b { + a +} else { + b +}); +atomic_rmw!(@old __sync_fetch_and_umin_4, u32, |a: u32, b: u32| if a < b { + a +} else { + b +}); + +atomic_rmw!(@old __sync_lock_test_and_set_1, u8, |_: u8, b: u8| b); +atomic_rmw!(@old __sync_lock_test_and_set_2, u16, |_: u16, b: u16| b); +atomic_rmw!(@old __sync_lock_test_and_set_4, u32, |_: u32, b: u32| b); + +atomic_cmpxchg!(__sync_val_compare_and_swap_1, u8); +atomic_cmpxchg!(__sync_val_compare_and_swap_2, u16); +atomic_cmpxchg!(__sync_val_compare_and_swap_4, u32); diff --git a/compiler-builtins/compiler-builtins/src/sync/mod.rs b/compiler-builtins/compiler-builtins/src/sync/mod.rs new file mode 100644 index 0000000000000..590db14bb23b3 --- /dev/null +++ b/compiler-builtins/compiler-builtins/src/sync/mod.rs @@ -0,0 +1,20 @@ +#[cfg(all( + kernel_user_helpers, + any(target_os = "linux", target_os = "android"), + target_arch = "arm" +))] +pub mod arm_linux; + +// Armv6k supports atomic instructions, but they are unavailable in Thumb mode +// unless Thumb-2 instructions available (v6t2). +// Using Thumb interworking allows us to use these instructions even from Thumb mode +// without Thumb-2 instructions, but LLVM does not implement that processing (as of LLVM 21), +// so we implement it here at this time. +// (`not(target_feature = "mclass")` is unneeded because v6k is not set on thumbv6m.) +#[cfg(all( + target_arch = "arm", + target_feature = "thumb-mode", + target_feature = "v6k", + not(target_feature = "v6t2"), +))] +pub mod thumbv6k; diff --git a/compiler-builtins/compiler-builtins/src/sync/thumbv6k.rs b/compiler-builtins/compiler-builtins/src/sync/thumbv6k.rs new file mode 100644 index 0000000000000..c47b4c2ec6b00 --- /dev/null +++ b/compiler-builtins/compiler-builtins/src/sync/thumbv6k.rs @@ -0,0 +1,213 @@ +// Armv6k supports atomic instructions, but they are unavailable in Thumb mode +// unless Thumb-2 instructions available (v6t2). +// Using Thumb interworking allows us to use these instructions even from Thumb mode +// without Thumb-2 instructions, but LLVM does not implement that processing (as of LLVM 21), +// so we implement it here at this time. + +use core::arch::asm; +use core::mem; + +// Data Memory Barrier (DMB) operation. +// +// Armv6 does not support DMB instruction, so use use special instruction equivalent to it. +// +// Refs: https://developer.arm.com/documentation/ddi0360/f/control-coprocessor-cp15/register-descriptions/c7--cache-operations-register +macro_rules! cp15_barrier { + () => { + "mcr p15, #0, {zero}, c7, c10, #5" + }; +} + +#[instruction_set(arm::a32)] +unsafe fn fence() { + unsafe { + asm!( + cp15_barrier!(), + // cp15_barrier! calls `mcr p15, 0, {zero}, c7, c10, 5`, and + // the value in the {zero} register should be zero (SBZ). + zero = inout(reg) 0_u32 => _, + options(nostack, preserves_flags), + ); + } +} + +trait Atomic: Copy + Eq { + unsafe fn load_relaxed(src: *const Self) -> Self; + unsafe fn cmpxchg(dst: *mut Self, current: Self, new: Self) -> Self; +} + +macro_rules! atomic { + ($ty:ident, $suffix:tt) => { + impl Atomic for $ty { + // #[instruction_set(arm::a32)] is unneeded for ldr. + #[inline] + unsafe fn load_relaxed( + src: *const Self, + ) -> Self { + let out: Self; + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + unsafe { + asm!( + concat!("ldr", $suffix, " {out}, [{src}]"), // atomic { out = *src } + src = in(reg) src, + out = lateout(reg) out, + options(nostack, preserves_flags), + ); + } + out + } + #[inline] + #[instruction_set(arm::a32)] + unsafe fn cmpxchg( + dst: *mut Self, + old: Self, + new: Self, + ) -> Self { + let mut out: Self; + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + // + // Instead of the common `fence; ll/sc loop; fence` form, we use the form used by + // LLVM, which omits the preceding fence if no write operation is performed. + unsafe { + asm!( + concat!("ldrex", $suffix, " {out}, [{dst}]"), // atomic { out = *dst; EXCLUSIVE = dst } + "cmp {out}, {old}", // if out == old { Z = 1 } else { Z = 0 } + "bne 3f", // if Z == 0 { jump 'cmp-fail } + cp15_barrier!(), // fence + "2:", // 'retry: + concat!("strex", $suffix, " {r}, {new}, [{dst}]"), // atomic { if EXCLUSIVE == dst { *dst = new; r = 0 } else { r = 1 }; EXCLUSIVE = None } + "cmp {r}, #0", // if r == 0 { Z = 1 } else { Z = 0 } + "beq 3f", // if Z == 1 { jump 'success } + concat!("ldrex", $suffix, " {out}, [{dst}]"), // atomic { out = *dst; EXCLUSIVE = dst } + "cmp {out}, {old}", // if out == old { Z = 1 } else { Z = 0 } + "beq 2b", // if Z == 1 { jump 'retry } + "3:", // 'cmp-fail | 'success: + cp15_barrier!(), // fence + dst = in(reg) dst, + // Note: this cast must be a zero-extend since loaded value + // which compared to it is zero-extended. + old = in(reg) u32::from(old), + new = in(reg) new, + out = out(reg) out, + r = out(reg) _, + // cp15_barrier! calls `mcr p15, 0, {zero}, c7, c10, 5`, and + // the value in the {zero} register should be zero (SBZ). + zero = inout(reg) 0_u32 => _, + // Do not use `preserves_flags` because CMP modifies the condition flags. + options(nostack), + ); + out + } + } + } + }; +} +atomic!(u8, "b"); +atomic!(u16, "h"); +atomic!(u32, ""); + +// To avoid the annoyance of sign extension, we implement signed CAS using +// unsigned CAS. (See note in cmpxchg impl in atomic! macro) +macro_rules! delegate_signed { + ($ty:ident, $base:ident) => { + const _: () = { + assert!(mem::size_of::<$ty>() == mem::size_of::<$base>()); + assert!(mem::align_of::<$ty>() == mem::align_of::<$base>()); + }; + impl Atomic for $ty { + #[inline] + unsafe fn load_relaxed(src: *const Self) -> Self { + // SAFETY: the caller must uphold the safety contract. + // casts are okay because $ty and $base implement the same layout. + unsafe { <$base as Atomic>::load_relaxed(src.cast::<$base>()).cast_signed() } + } + #[inline] + unsafe fn cmpxchg(dst: *mut Self, old: Self, new: Self) -> Self { + // SAFETY: the caller must uphold the safety contract. + // casts are okay because $ty and $base implement the same layout. + unsafe { + <$base as Atomic>::cmpxchg( + dst.cast::<$base>(), + old.cast_unsigned(), + new.cast_unsigned(), + ) + .cast_signed() + } + } + } + }; +} +delegate_signed!(i8, u8); +delegate_signed!(i16, u16); +delegate_signed!(i32, u32); + +// Generic atomic read-modify-write operation +// +// We could implement RMW more efficiently as an assembly LL/SC loop per operation, +// but we won't do that for now because it would make the implementation more complex. +// +// We also do not implement LL and SC as separate functions. This is because it +// is theoretically possible for the compiler to insert operations that might +// clear the reservation between LL and SC. See https://github.com/taiki-e/portable-atomic/blob/58ef7f27c9e20da4cc1ef0abf8b8ce9ac5219ec3/src/imp/atomic128/aarch64.rs#L44-L55 +// for more details. +unsafe fn atomic_rmw T, G: Fn(T, T) -> T>(ptr: *mut T, f: F, g: G) -> T { + loop { + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + let curval = unsafe { T::load_relaxed(ptr) }; + let newval = f(curval); + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + if unsafe { T::cmpxchg(ptr, curval, newval) } == curval { + return g(curval, newval); + } + } +} + +macro_rules! atomic_rmw { + ($name:ident, $ty:ty, $op:expr, $fetch:expr) => { + intrinsics! { + pub unsafe extern "C" fn $name(ptr: *mut $ty, val: $ty) -> $ty { + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + unsafe { + atomic_rmw( + ptr, + |x| $op(x as $ty, val), + |old, new| $fetch(old, new) + ) as $ty + } + } + } + }; + + (@old $name:ident, $ty:ty, $op:expr) => { + atomic_rmw!($name, $ty, $op, |old, _| old); + }; + + (@new $name:ident, $ty:ty, $op:expr) => { + atomic_rmw!($name, $ty, $op, |_, new| new); + }; +} +macro_rules! atomic_cmpxchg { + ($name:ident, $ty:ty) => { + intrinsics! { + pub unsafe extern "C" fn $name(ptr: *mut $ty, oldval: $ty, newval: $ty) -> $ty { + // SAFETY: the caller must guarantee that the pointer is valid for read and write + // and aligned to the element size. + unsafe { <$ty as Atomic>::cmpxchg(ptr, oldval, newval) } + } + } + }; +} + +include!("arm_thumb_shared.rs"); + +intrinsics! { + pub unsafe extern "C" fn __sync_synchronize() { + // SAFETY: preconditions are the same as the calling function. + unsafe { fence() }; + } +} diff --git a/compiler-builtins/crates/libm-macros/Cargo.toml b/compiler-builtins/crates/libm-macros/Cargo.toml index 100a8d0ec30e4..f99a92e21c709 100644 --- a/compiler-builtins/crates/libm-macros/Cargo.toml +++ b/compiler-builtins/crates/libm-macros/Cargo.toml @@ -9,10 +9,10 @@ license = "MIT OR Apache-2.0" proc-macro = true [dependencies] -heck = "0.5.0" -proc-macro2 = "1.0.95" -quote = "1.0.40" -syn = { version = "2.0.104", features = ["full", "extra-traits", "visit-mut"] } +heck.workspace = true +proc-macro2.workspace = true +quote.workspace = true +syn = { workspace = true, features = ["full", "extra-traits", "visit-mut"] } [lints.rust] # Values used during testing diff --git a/compiler-builtins/crates/musl-math-sys/Cargo.toml b/compiler-builtins/crates/musl-math-sys/Cargo.toml index 39f6fa9065bd9..eb97ffbc86693 100644 --- a/compiler-builtins/crates/musl-math-sys/Cargo.toml +++ b/compiler-builtins/crates/musl-math-sys/Cargo.toml @@ -5,10 +5,8 @@ edition = "2024" publish = false license = "MIT OR Apache-2.0" -[dependencies] - [dev-dependencies] -libm = { path = "../../libm" } +libm.workspace = true [build-dependencies] -cc = "1.2.29" +cc.workspace = true diff --git a/compiler-builtins/crates/symbol-check/Cargo.toml b/compiler-builtins/crates/symbol-check/Cargo.toml index e2218b4917200..5bc13d337c274 100644 --- a/compiler-builtins/crates/symbol-check/Cargo.toml +++ b/compiler-builtins/crates/symbol-check/Cargo.toml @@ -5,8 +5,11 @@ edition = "2024" publish = false [dependencies] -object = "0.37.1" -serde_json = "1.0.140" +object.workspace = true +regex.workspace = true +serde_json.workspace = true -[features] -wasm = ["object/wasm"] +[dev-dependencies] +assert_cmd.workspace = true +cc.workspace = true +tempfile.workspace = true diff --git a/compiler-builtins/crates/symbol-check/build.rs b/compiler-builtins/crates/symbol-check/build.rs new file mode 100644 index 0000000000000..b3e53c38b0bd4 --- /dev/null +++ b/compiler-builtins/crates/symbol-check/build.rs @@ -0,0 +1,6 @@ +use std::env; + +fn main() { + println!("cargo::rustc-env=HOST={}", env::var("HOST").unwrap()); + println!("cargo::rustc-env=TARGET={}", env::var("TARGET").unwrap()); +} diff --git a/compiler-builtins/crates/symbol-check/src/main.rs b/compiler-builtins/crates/symbol-check/src/main.rs index 7d0b7e90addb5..733d9f4e8befb 100644 --- a/compiler-builtins/crates/symbol-check/src/main.rs +++ b/compiler-builtins/crates/symbol-check/src/main.rs @@ -1,17 +1,22 @@ //! Tool used by CI to inspect compiler-builtins archives and help ensure we won't run into any //! linking errors. +//! +//! Note that symcheck is a "hostprog", i.e. is built and run on the host target even when the +//! actual target is cross compiled. -use std::collections::{BTreeMap, BTreeSet}; +use std::collections::{BTreeMap, BTreeSet, HashSet}; use std::fs; use std::io::{BufRead, BufReader}; use std::path::{Path, PathBuf}; use std::process::{Command, Stdio}; +use std::sync::LazyLock; use object::read::archive::ArchiveFile; use object::{ File as ObjFile, Object, ObjectSection, ObjectSymbol, Result as ObjResult, Symbol, SymbolKind, SymbolScope, }; +use regex::Regex; use serde_json::Value; const CHECK_LIBRARIES: &[&str] = &["compiler_builtins", "builtins_test_intrinsics"]; @@ -42,8 +47,7 @@ fn main() { run_build_and_check(target, args); } ["build-and-check", "--", args @ ..] if !args.is_empty() => { - let target = &host_target(); - run_build_and_check(target, args); + run_build_and_check(env!("HOST"), args); } ["check", paths @ ..] if !paths.is_empty() => { check_paths(paths); @@ -80,20 +84,6 @@ fn check_paths>(paths: &[P]) { } } -fn host_target() -> String { - let out = Command::new("rustc") - .arg("--version") - .arg("--verbose") - .output() - .unwrap(); - assert!(out.status.success()); - let out = String::from_utf8(out.stdout).unwrap(); - out.lines() - .find_map(|s| s.strip_prefix("host: ")) - .unwrap() - .to_owned() -} - /// Run `cargo build` with the provided additional arguments, collecting the list of created /// libraries. fn exec_cargo_with_args(target: &str, args: &[&str]) -> Vec { @@ -257,8 +247,9 @@ fn verify_no_duplicates(archive: &BinFile) { assert!(found_any, "no symbols found"); if !dups.is_empty() { + let count = dups.iter().map(|x| &x.name).collect::>().len(); dups.sort_unstable_by(|a, b| a.name.cmp(&b.name)); - panic!("found duplicate symbols: {dups:#?}"); + panic!("found {count} duplicate symbols: {dups:#?}"); } println!(" success: no duplicate symbols found"); @@ -266,6 +257,14 @@ fn verify_no_duplicates(archive: &BinFile) { /// Ensure that there are no references to symbols from `core` that aren't also (somehow) defined. fn verify_core_symbols(archive: &BinFile) { + // Match both mangling styles: + // + // * `_ZN4core3str8converts9from_utf817hd4454ac14cbbb790E` (old) + // * `_RNvNtNtCscK9O3IwVk7N_4core3str8converts9from_utf8` (v0) + // + // Also account for the Apple leading `_`. + static RE: LazyLock = LazyLock::new(|| Regex::new(r"^_?_[RZ].*4core").unwrap()); + let mut defined = BTreeSet::new(); let mut undefined = Vec::new(); let mut has_symbols = false; @@ -274,7 +273,7 @@ fn verify_core_symbols(archive: &BinFile) { has_symbols = true; // Find only symbols from `core` - if !symbol.name().unwrap().contains("_ZN4core") { + if !RE.is_match(symbol.name().unwrap()) { return; } @@ -293,7 +292,10 @@ fn verify_core_symbols(archive: &BinFile) { if !undefined.is_empty() { undefined.sort_unstable_by(|a, b| a.name.cmp(&b.name)); - panic!("found undefined symbols from core: {undefined:#?}"); + panic!( + "found {} undefined symbols from core: {undefined:#?}", + undefined.len() + ); } println!(" success: no undefined references to core found"); diff --git a/compiler-builtins/crates/symbol-check/tests/all.rs b/compiler-builtins/crates/symbol-check/tests/all.rs new file mode 100644 index 0000000000000..400469a49e2a5 --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/all.rs @@ -0,0 +1,126 @@ +use std::env; +use std::ffi::OsString; +use std::path::{Path, PathBuf}; +use std::process::{Command, Stdio}; +use std::sync::LazyLock; + +use assert_cmd::assert::Assert; +use assert_cmd::cargo::cargo_bin_cmd; +use tempfile::tempdir; + +trait AssertExt { + fn stderr_contains(self, s: &str) -> Self; +} + +impl AssertExt for Assert { + fn stderr_contains(self, s: &str) -> Self { + let out = String::from_utf8_lossy(&self.get_output().stderr); + assert!(out.contains(s), "looking for: `{s}`\nout:\n```\n{out}\n```"); + self + } +} + +#[test] +fn test_duplicates() { + let dir = tempdir().unwrap(); + let dup_out = dir.path().join("dup.o"); + let lib_out = dir.path().join("libfoo.rlib"); + + // For the "bad" file, we need duplicate symbols from different object files in the archive. Do + // this reliably by building an archive and a separate object file then merging them. + rustc_build(&input_dir().join("duplicates.rs"), &lib_out, |cmd| cmd); + rustc_build(&input_dir().join("duplicates.rs"), &dup_out, |cmd| { + cmd.arg("--emit=obj") + }); + + let mut ar = cc_build().get_archiver(); + + if ar.get_program().to_string_lossy().contains("lib.exe") { + let mut out_arg = OsString::from("-out:"); + out_arg.push(&lib_out); + ar.arg(&out_arg); + // Repeating the same file as the first arg makes lib.exe append (taken from the + // `cc` implementation). + ar.arg(&lib_out); + } else { + ar.arg("rs") + // Eat an `libfoo.rlib(lib.rmeta) has no symbols` info message on MacOS + .stderr(Stdio::null()) + .arg(&lib_out); + } + let status = ar.arg(&dup_out).status().unwrap(); + assert!(status.success()); + + let assert = cargo_bin_cmd!().arg("check").arg(&lib_out).assert(); + assert + .failure() + .stderr_contains("duplicate symbols") + .stderr_contains("FDUP") + .stderr_contains("IDUP") + .stderr_contains("fndup"); +} + +#[test] +fn test_core_symbols() { + let dir = tempdir().unwrap(); + let lib_out = dir.path().join("libfoo.rlib"); + rustc_build(&input_dir().join("core_symbols.rs"), &lib_out, |cmd| cmd); + let assert = cargo_bin_cmd!().arg("check").arg(&lib_out).assert(); + assert + .failure() + .stderr_contains("found 1 undefined symbols from core") + .stderr_contains("from_utf8"); +} + +#[test] +fn test_good() { + let dir = tempdir().unwrap(); + let lib_out = dir.path().join("libfoo.rlib"); + rustc_build(&input_dir().join("good.rs"), &lib_out, |cmd| cmd); + let assert = cargo_bin_cmd!().arg("check").arg(&lib_out).assert(); + assert.success(); +} + +/// Build i -> o with optional additional configuration. +fn rustc_build(i: &Path, o: &Path, mut f: impl FnMut(&mut Command) -> &mut Command) { + let mut cmd = Command::new("rustc"); + cmd.arg(i) + .arg("--target") + .arg(target()) + .arg("--crate-type=lib") + .arg("-o") + .arg(o); + f(&mut cmd); + let status = cmd.status().unwrap(); + assert!(status.success()); +} + +/// Configure `cc` with the host and target. +fn cc_build() -> cc::Build { + let mut b = cc::Build::new(); + b.host(env!("HOST")).target(&target()); + b +} + +/// Symcheck runs on the host but we want to verify that we find issues on all targets, so +/// the cross target may be specified. +fn target() -> String { + static TARGET: LazyLock = LazyLock::new(|| { + let target = match env::var("SYMCHECK_TEST_TARGET") { + Ok(t) => t, + // Require on CI so we don't accidentally always test the native target + _ if env::var("CI").is_ok() => panic!("SYMCHECK_TEST_TARGET must be set in CI"), + // Fall back to native for local convenience. + Err(_) => env!("HOST").to_string(), + }; + + println!("using target {target}"); + target + }); + + TARGET.clone() +} + +fn input_dir() -> PathBuf { + Path::new(env!("CARGO_MANIFEST_DIR")).join("tests/input") +} diff --git a/compiler-builtins/crates/symbol-check/tests/input/core_symbols.rs b/compiler-builtins/crates/symbol-check/tests/input/core_symbols.rs new file mode 100644 index 0000000000000..cf74f97796612 --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/input/core_symbols.rs @@ -0,0 +1,11 @@ +//! Ensure we catch calls to `core`. + +#![no_std] + +#[unsafe(no_mangle)] +pub fn call_from_core(s: &[u8]) -> &str { + match core::str::from_utf8(&s) { + Ok(s) => s, + Err(_) => "", + } +} diff --git a/compiler-builtins/crates/symbol-check/tests/input/duplicates.rs b/compiler-builtins/crates/symbol-check/tests/input/duplicates.rs new file mode 100644 index 0000000000000..92623a0b2e1a5 --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/input/duplicates.rs @@ -0,0 +1,12 @@ +//! Ensure we catch duplicate symbols (the duplicates are in the aux file). Gets built twice +//! as separate object files. + +#![no_std] + +#[unsafe(no_mangle)] +static IDUP: i32 = 0; +#[unsafe(no_mangle)] +static FDUP: f32 = 0.0; + +#[unsafe(no_mangle)] +pub fn fndup() {} diff --git a/compiler-builtins/crates/symbol-check/tests/input/good.rs b/compiler-builtins/crates/symbol-check/tests/input/good.rs new file mode 100644 index 0000000000000..6679ee1dd30cf --- /dev/null +++ b/compiler-builtins/crates/symbol-check/tests/input/good.rs @@ -0,0 +1,4 @@ +#![no_std] + +#[unsafe(no_mangle)] +pub fn good() {} diff --git a/compiler-builtins/crates/util/Cargo.toml b/compiler-builtins/crates/util/Cargo.toml index 614c54bd83557..c56e2cc12ea58 100644 --- a/compiler-builtins/crates/util/Cargo.toml +++ b/compiler-builtins/crates/util/Cargo.toml @@ -5,15 +5,15 @@ edition = "2024" publish = false license = "MIT OR Apache-2.0" +[dependencies] +libm.workspace = true +libm-macros.workspace = true +libm-test.workspace = true +musl-math-sys = { workspace = true, optional = true } +rug = { workspace = true, optional = true } + [features] default = ["build-musl", "build-mpfr", "unstable-float"] build-musl = ["libm-test/build-musl", "dep:musl-math-sys"] build-mpfr = ["libm-test/build-mpfr", "dep:rug"] unstable-float = ["libm/unstable-float", "libm-test/unstable-float", "rug?/nightly-float"] - -[dependencies] -libm = { path = "../../libm", default-features = false } -libm-macros = { path = "../libm-macros" } -libm-test = { path = "../../libm-test", default-features = false } -musl-math-sys = { path = "../musl-math-sys", optional = true } -rug = { version = "1.27.0", optional = true, default-features = false, features = ["float", "std"] } diff --git a/compiler-builtins/etc/thumbv6-none-eabi.json b/compiler-builtins/etc/thumbv6-none-eabi.json new file mode 100644 index 0000000000000..4c1f760ac3e03 --- /dev/null +++ b/compiler-builtins/etc/thumbv6-none-eabi.json @@ -0,0 +1,20 @@ +{ + "abi": "eabi", + "arch": "arm", + "asm-args": ["-mthumb-interwork", "-march=armv6", "-mlittle-endian"], + "c-enum-min-bits": 8, + "crt-objects-fallback": "false", + "data-layout": "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64", + "emit-debug-gdb-scripts": false, + "features": "+soft-float,+strict-align,+v6k", + "frame-pointer": "always", + "has-thumb-interworking": true, + "linker": "rust-lld", + "linker-flavor": "gnu-lld", + "llvm-floatabi": "soft", + "llvm-target": "thumbv6-none-eabi", + "max-atomic-width": 32, + "panic-strategy": "abort", + "relocation-model": "static", + "target-pointer-width": 32 +} diff --git a/compiler-builtins/libm-test/Cargo.toml b/compiler-builtins/libm-test/Cargo.toml index adecfc1af6b87..4f65504bd584f 100644 --- a/compiler-builtins/libm-test/Cargo.toml +++ b/compiler-builtins/libm-test/Cargo.toml @@ -5,6 +5,31 @@ edition = "2024" publish = false license = "MIT OR Apache-2.0" +[dependencies] +anyhow.workspace = true +# This is not directly used but is required so we can enable `gmp-mpfr-sys/force-cross`. +gmp-mpfr-sys = { workspace = true, optional = true } +gungraun = { workspace = true, optional = true } +indicatif.workspace = true +libm = { workspace = true, default-features = true, features = ["unstable-public-internals"] } +libm-macros.workspace = true +musl-math-sys = { workspace = true, optional = true } +paste.workspace = true +rand.workspace = true +rand_chacha.workspace = true +rayon.workspace = true +rug = { workspace = true, optional = true } + +[target.'cfg(target_family = "wasm")'.dependencies] +getrandom = { workspace = true, features = ["wasm_js"] } + +[build-dependencies] +rand = { workspace = true, optional = true } + +[dev-dependencies] +criterion.workspace = true +libtest-mimic.workspace = true + [features] default = ["build-mpfr", "unstable-float"] @@ -27,31 +52,6 @@ icount = ["dep:gungraun"] # Run with a reduced set of benchmarks, such as for CI short-benchmarks = [] -[dependencies] -anyhow = "1.0.98" -# This is not directly used but is required so we can enable `gmp-mpfr-sys/force-cross`. -gmp-mpfr-sys = { version = "1.6.5", optional = true, default-features = false } -gungraun = { version = "0.17.0", optional = true } -indicatif = { version = "0.18.0", default-features = false } -libm = { path = "../libm", features = ["unstable-public-internals"] } -libm-macros = { path = "../crates/libm-macros" } -musl-math-sys = { path = "../crates/musl-math-sys", optional = true } -paste = "1.0.15" -rand = "0.9.1" -rand_chacha = "0.9.0" -rayon = "1.10.0" -rug = { version = "1.27.0", optional = true, default-features = false, features = ["float", "integer", "std"] } - -[target.'cfg(target_family = "wasm")'.dependencies] -getrandom = { version = "0.3.3", features = ["wasm_js"] } - -[build-dependencies] -rand = { version = "0.9.1", optional = true } - -[dev-dependencies] -criterion = { version = "0.6.0", default-features = false, features = ["cargo_bench_support"] } -libtest-mimic = "0.8.1" - [[bench]] name = "icount" harness = false diff --git a/compiler-builtins/libm-test/src/domain.rs b/compiler-builtins/libm-test/src/domain.rs index 94641be9b5483..eb009bfa093f4 100644 --- a/compiler-builtins/libm-test/src/domain.rs +++ b/compiler-builtins/libm-test/src/domain.rs @@ -207,7 +207,7 @@ impl EitherPrim, Domain> { .into_prim_float()]; /// Domain for `loggamma` - const LGAMMA: [Self; 1] = Self::STRICTLY_POSITIVE; + const LGAMMA: [Self; 1] = Self::UNBOUNDED1; /// Domain for `jn` and `yn`. // FIXME: the domain should provide some sort of "reasonable range" so we don't actually test diff --git a/compiler-builtins/libm-test/src/lib.rs b/compiler-builtins/libm-test/src/lib.rs index accb39654d15a..60d96ae9bceee 100644 --- a/compiler-builtins/libm-test/src/lib.rs +++ b/compiler-builtins/libm-test/src/lib.rs @@ -1,6 +1,7 @@ #![cfg_attr(f16_enabled, feature(f16))] #![cfg_attr(f128_enabled, feature(f128))] #![allow(clippy::unusual_byte_groupings)] // sometimes we group by sign_exp_sig +#![allow(unstable_name_collisions)] // FIXME(float_bits_const): remove when stable pub mod domain; mod f8_impl; diff --git a/compiler-builtins/libm-test/src/mpfloat.rs b/compiler-builtins/libm-test/src/mpfloat.rs index 9b51dc6051d03..85f0a4da4a6e2 100644 --- a/compiler-builtins/libm-test/src/mpfloat.rs +++ b/compiler-builtins/libm-test/src/mpfloat.rs @@ -170,7 +170,9 @@ libm_macros::for_each_function! { ldexpf, ldexpf128, ldexpf16, + lgamma, lgamma_r, + lgammaf, lgammaf_r, modf, modff, @@ -213,7 +215,6 @@ libm_macros::for_each_function! { fmaximum_num | fmaximum_numf | fmaximum_numf16 | fmaximum_numf128 => max, fmin | fminf | fminf16 | fminf128 | fminimum_num | fminimum_numf | fminimum_numf16 | fminimum_numf128 => min, - lgamma | lgammaf => ln_gamma, log | logf => ln, log1p | log1pf => ln_1p, tgamma | tgammaf => gamma, @@ -576,6 +577,30 @@ impl MpOp for crate::op::lgammaf_r::Routine { } } +impl MpOp for crate::op::lgamma::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + ::run(this, input).0 + } +} + +impl MpOp for crate::op::lgammaf::Routine { + type MpTy = MpFloat; + + fn new_mp() -> Self::MpTy { + new_mpfloat::() + } + + fn run(this: &mut Self::MpTy, input: Self::RustArgs) -> Self::RustRet { + ::run(this, input).0 + } +} + /* stub implementations so we don't need to special case them */ impl MpOp for crate::op::nextafter::Routine { diff --git a/compiler-builtins/libm-test/src/precision.rs b/compiler-builtins/libm-test/src/precision.rs index 7887c032394b8..5d52da168fe72 100644 --- a/compiler-builtins/libm-test/src/precision.rs +++ b/compiler-builtins/libm-test/src/precision.rs @@ -67,7 +67,7 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { Bn::Exp2 => 1, Bn::Expm1 => 1, Bn::Hypot => 1, - Bn::Lgamma | Bn::LgammaR => 16, + Bn::Lgamma | Bn::LgammaR => 4, Bn::Log => 1, Bn::Log10 => 1, Bn::Log1p => 1, @@ -102,7 +102,6 @@ pub fn default_ulp(ctx: &CheckCtx) -> u32 { match ctx.base_name { Bn::Cosh => ulp = 2, Bn::Exp10 if usize::BITS < 64 => ulp = 4, - Bn::Lgamma | Bn::LgammaR => ulp = 400, Bn::Tanh => ulp = 4, _ => (), } @@ -218,17 +217,17 @@ impl MaybeOverride<(f16,)> for SpecialCase {} impl MaybeOverride<(f32,)> for SpecialCase { fn check_float(input: (f32,), actual: F, expected: F, ctx: &CheckCtx) -> CheckAction { - if (ctx.base_name == BaseName::Lgamma || ctx.base_name == BaseName::LgammaR) - && input.0 > 4e36 - && expected.is_infinite() - && !actual.is_infinite() - { - // This result should saturate but we return a finite value. + if ctx.base_name == BaseName::J0 && input.0 < -1e34 { + // Errors get huge close to -inf return XFAIL_NOCHECK; } - if ctx.base_name == BaseName::J0 && input.0 < -1e34 { - // Errors get huge close to -inf + // FIXME(correctness): lgammaf has high relative inaccuracy near its zeroes + if matches!(ctx.base_name, BaseName::Lgamma | BaseName::LgammaR) + && input.0 > -13.0625 + && input.0 < -2.0 + && (expected.abs() < F::ONE || (input.0 - input.0.round()).abs() < 0.02) + { return XFAIL_NOCHECK; } @@ -266,6 +265,24 @@ impl MaybeOverride<(f64,)> for SpecialCase { return XFAIL_NOCHECK; } + if ctx.base_name == BaseName::Acosh + && input.0 < 1.0 + && actual.is_nan() + && ctx.basis == CheckBasis::Musl + { + // Musl sometimes evaluates acosh(negative) to a numeric value + return XFAIL_NOCHECK; + } + + // FIXME(correctness): lgamma has high relative inaccuracy near its zeroes + if matches!(ctx.base_name, BaseName::Lgamma | BaseName::LgammaR) + && input.0 > -32.0 + && input.0 < -2.0 + && (expected.abs() < F::ONE || (input.0 - input.0.round()).abs() < 0.02) + { + return XFAIL_NOCHECK; + } + // maybe_check_nan_bits(actual, expected, ctx) unop_common(input, actual, expected, ctx) } @@ -295,27 +312,6 @@ fn unop_common( expected: F2, ctx: &CheckCtx, ) -> CheckAction { - if ctx.base_name == BaseName::Acosh - && input.0 < F1::NEG_ONE - && !(expected.is_nan() && actual.is_nan()) - { - // acoshf is undefined for x <= 1.0, but we return a random result at lower values. - - if ctx.basis == CheckBasis::Musl { - return XFAIL_NOCHECK; - } - - return XFAIL("acoshf undefined"); - } - - if (ctx.base_name == BaseName::Lgamma || ctx.base_name == BaseName::LgammaR) - && input.0 < F1::ZERO - && !input.0.is_infinite() - { - // loggamma should not be defined for x < 0, yet we both return results - return XFAIL_NOCHECK; - } - // fabs and copysign must leave NaNs untouched. if ctx.base_name == BaseName::Fabs && input.0.is_nan() { // LLVM currently uses x87 instructions which quieten signalling NaNs to handle the i686 @@ -401,14 +397,6 @@ fn binop_common( return SKIP; } - // FIXME(#939): this should not be skipped, there is a bug in our implementationi. - if ctx.base_name == BaseName::FmaximumNum - && ctx.basis == CheckBasis::Mpfr - && ((input.0.is_nan() && actual.is_nan() && expected.is_nan()) || input.1.is_nan()) - { - return XFAIL_NOCHECK; - } - /* FIXME(#439): our fmin and fmax do not compare signed zeros */ if ctx.base_name == BaseName::Fmin @@ -510,7 +498,7 @@ fn int_float_common( if input.0 > 4000 { return XFAIL_NOCHECK; } else if input.0 > 100 { - return CheckAction::AssertWithUlp(1_000_000); + return CheckAction::AssertWithUlp(2_000_000); } } DEFAULT diff --git a/compiler-builtins/libm/CHANGELOG.md b/compiler-builtins/libm/CHANGELOG.md index 33fec06aa2379..037f79ef3ef1c 100644 --- a/compiler-builtins/libm/CHANGELOG.md +++ b/compiler-builtins/libm/CHANGELOG.md @@ -8,6 +8,22 @@ and this project adheres to ## [Unreleased] +## [0.2.16](https://github.com/rust-lang/compiler-builtins/compare/libm-v0.2.15...libm-v0.2.16) - 2025-12-07 + +### Fixed + +- Fix an incorrect result for `fminimum` and `fmaximum` with the input (-0, NaN) +- Fix a typo in `libm::Libm::roundeven` +- Fix the `expm1f` overflow threshold +- Change `CmpResult` to use a pointer-sized return type +- Compare against `CARGO_CFG_TARGET_FAMILY` in a multi-valued fashion +- Implement `exp` and its variants for i586 with inline assembly +- Implement `floor` and `ceil` in assembly on `i586` + +### Other + +- Significantly optimize `fmod` worst case performance ([#1002](https://github.com/rust-lang/compiler-builtins/pull/1002)) + ## [0.2.15](https://github.com/rust-lang/compiler-builtins/compare/libm-v0.2.14...libm-v0.2.15) - 2025-05-06 ### Other diff --git a/compiler-builtins/libm/Cargo.toml b/compiler-builtins/libm/Cargo.toml index 5b5ca34fd2c9e..98202d1977dc6 100644 --- a/compiler-builtins/libm/Cargo.toml +++ b/compiler-builtins/libm/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "libm" -version = "0.2.15" +version = "0.2.16" authors = [ "Alex Crichton ", "Amanieu d'Antras ", @@ -13,7 +13,11 @@ keywords = ["libm", "math"] repository = "https://github.com/rust-lang/compiler-builtins" license = "MIT" edition = "2021" -rust-version = "1.63" +rust-version = "1.67" + +[dev-dependencies] +# FIXME(msrv): switch to `no-panic.workspace` when possible +no-panic = "0.1.35" [features] default = ["arch"] @@ -42,9 +46,6 @@ unstable-float = [] # hard float operations. force-soft-floats = [] -[dev-dependencies] -no-panic = "0.1.35" - [lints.rust] unexpected_cfgs = { level = "warn", check-cfg = [ # compiler-builtins sets this feature, but we use it in `libm` diff --git a/compiler-builtins/libm/src/lib.rs b/compiler-builtins/libm/src/lib.rs index 31b12235314cd..85ed5e2c9fc63 100644 --- a/compiler-builtins/libm/src/lib.rs +++ b/compiler-builtins/libm/src/lib.rs @@ -8,6 +8,7 @@ )] #![cfg_attr(f128_enabled, feature(f128))] #![cfg_attr(f16_enabled, feature(f16))] +#![allow(unstable_name_collisions)] // FIXME(float_bits_const): remove when stable #![allow(clippy::assign_op_pattern)] #![allow(clippy::deprecated_cfg_attr)] #![allow(clippy::eq_op)] diff --git a/compiler-builtins/libm/src/math/acosh.rs b/compiler-builtins/libm/src/math/acosh.rs index 8737bad012c84..2904fc0ed5201 100644 --- a/compiler-builtins/libm/src/math/acosh.rs +++ b/compiler-builtins/libm/src/math/acosh.rs @@ -1,4 +1,4 @@ -use super::{log, log1p, sqrt}; +use super::{Float, log, log1p, sqrt}; const LN2: f64 = 0.693147180559945309417232121458176568; /* 0x3fe62e42, 0xfefa39ef*/ @@ -9,19 +9,19 @@ const LN2: f64 = 0.693147180559945309417232121458176568; /* 0x3fe62e42, 0xfefa3 /// `x` must be a number greater than or equal to 1. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn acosh(x: f64) -> f64 { - let u = x.to_bits(); - let e = ((u >> 52) as usize) & 0x7ff; + let ux = x.to_bits(); /* x < 1 domain error is handled in the called functions */ - - if e < 0x3ff + 1 { - /* |x| < 2, up to 2ulp error in [1,1.125] */ - return log1p(x - 1.0 + sqrt((x - 1.0) * (x - 1.0) + 2.0 * (x - 1.0))); - } - if e < 0x3ff + 26 { - /* |x| < 0x1p26 */ - return log(2.0 * x - 1.0 / (x + sqrt(x * x - 1.0))); + if (ux & !f64::SIGN_MASK) < 2_f64.to_bits() { + /* |x| < 2, invalid if x < 1 */ + /* up to 2ulp error in [1,1.125] */ + let x_1 = x - 1.0; + log1p(x_1 + sqrt(x_1 * x_1 + 2.0 * x_1)) + } else if ux < ((1 << 26) as f64).to_bits() { + /* 2 <= x < 0x1p26 */ + log(2.0 * x - 1.0 / (x + sqrt(x * x - 1.0))) + } else { + /* x >= 0x1p26 or x <= -2 or nan */ + log(x) + LN2 } - /* |x| >= 0x1p26 or nan */ - return log(x) + LN2; } diff --git a/compiler-builtins/libm/src/math/acoshf.rs b/compiler-builtins/libm/src/math/acoshf.rs index 432fa03f11635..d9aafaabdef43 100644 --- a/compiler-builtins/libm/src/math/acoshf.rs +++ b/compiler-builtins/libm/src/math/acoshf.rs @@ -1,4 +1,4 @@ -use super::{log1pf, logf, sqrtf}; +use super::{Float, log1pf, logf, sqrtf}; const LN2: f32 = 0.693147180559945309417232121458176568; @@ -9,18 +9,19 @@ const LN2: f32 = 0.693147180559945309417232121458176568; /// `x` must be a number greater than or equal to 1. #[cfg_attr(assert_no_panic, no_panic::no_panic)] pub fn acoshf(x: f32) -> f32 { - let u = x.to_bits(); - let a = u & 0x7fffffff; + let ux = x.to_bits(); - if a < 0x3f800000 + (1 << 23) { - /* |x| < 2, invalid if x < 1 or nan */ + /* x < 1 domain error is handled in the called functions */ + if (ux & !f32::SIGN_MASK) < 2_f32.to_bits() { + /* |x| < 2, invalid if x < 1 */ /* up to 2ulp error in [1,1.125] */ - return log1pf(x - 1.0 + sqrtf((x - 1.0) * (x - 1.0) + 2.0 * (x - 1.0))); + let x_1 = x - 1.0; + log1pf(x_1 + sqrtf(x_1 * x_1 + 2.0 * x_1)) + } else if ux < ((1 << 12) as f32).to_bits() { + /* 2 <= x < 0x1p12 */ + logf(2.0 * x - 1.0 / (x + sqrtf(x * x - 1.0))) + } else { + /* x >= 0x1p12 or x <= -2 or nan */ + logf(x) + LN2 } - if a < 0x3f800000 + (12 << 23) { - /* |x| < 0x1p12 */ - return logf(2.0 * x - 1.0 / (x + sqrtf(x * x - 1.0))); - } - /* x >= 0x1p12 */ - return logf(x) + LN2; } diff --git a/compiler-builtins/libm/src/math/generic/sqrt.rs b/compiler-builtins/libm/src/math/generic/sqrt.rs index 9481c4cdb7bbe..e97a43d349569 100644 --- a/compiler-builtins/libm/src/math/generic/sqrt.rs +++ b/compiler-builtins/libm/src/math/generic/sqrt.rs @@ -419,9 +419,7 @@ mod tests { fn conformance_tests_f16() { let cases = [ (f16::PI, 0x3f17_u16), - // 10_000.0, using a hex literal for MSRV hack (Rust < 1.67 checks literal widths as - // part of the AST, so the `cfg` is irrelevant here). - (f16::from_bits(0x70e2), 0x5640_u16), + (10000.0_f16, 0x5640_u16), (f16::from_bits(0x0000000f), 0x13bf_u16), (f16::INFINITY, f16::INFINITY.to_bits()), ]; diff --git a/compiler-builtins/libm/src/math/support/float_traits.rs b/compiler-builtins/libm/src/math/support/float_traits.rs index 4e5011f62e0f6..60c8bfca5165b 100644 --- a/compiler-builtins/libm/src/math/support/float_traits.rs +++ b/compiler-builtins/libm/src/math/support/float_traits.rs @@ -1,5 +1,3 @@ -#![allow(unknown_lints)] // FIXME(msrv) we shouldn't need this - use core::{fmt, mem, ops}; use super::int_traits::{CastFrom, Int, MinInt}; @@ -289,10 +287,7 @@ macro_rules! float_impl { cfg_if! { // fma is not yet available in `core` if #[cfg(intrinsics_enabled)] { - // FIXME(msrv,bench): once our benchmark rustc version is above the - // 2022-09-23 nightly, this can be removed. - #[allow(unused_unsafe)] - unsafe { core::intrinsics::$fma_intrinsic(self, y, z) } + core::intrinsics::$fma_intrinsic(self, y, z) } else { super::super::$fma_fn(self, y, z) } diff --git a/compiler-builtins/libm/src/math/support/hex_float.rs b/compiler-builtins/libm/src/math/support/hex_float.rs index c8558b90053d1..2f9369e504417 100644 --- a/compiler-builtins/libm/src/math/support/hex_float.rs +++ b/compiler-builtins/libm/src/math/support/hex_float.rs @@ -121,7 +121,7 @@ const fn parse_finite( Ok(Parsed { sig, exp }) => (sig, exp), }; - let mut round_bits = u128_ilog2(sig) as i32 - sig_bits as i32; + let mut round_bits = sig.ilog2() as i32 - sig_bits as i32; // Round at least up to min_lsb if exp < min_lsb - round_bits { @@ -299,29 +299,11 @@ const fn parse_hex(mut b: &[u8]) -> Result { )); }; - { - let e; - if negate_exp { - e = (exp as i64) - (pexp as i64); - } else { - e = (exp as i64) + (pexp as i64); - }; - - exp = if e < i32::MIN as i64 { - i32::MIN - } else if e > i32::MAX as i64 { - i32::MAX - } else { - e as i32 - }; - } - /* FIXME(msrv): once MSRV >= 1.66, replace the above workaround block with: if negate_exp { exp = exp.saturating_sub_unsigned(pexp); } else { exp = exp.saturating_add_unsigned(pexp); }; - */ Ok(Parsed { sig, exp }) } @@ -342,14 +324,6 @@ const fn hex_digit(c: u8) -> Option { } } -/* FIXME(msrv): vendor some things that are not const stable at our MSRV */ - -/// `u128::ilog2` -const fn u128_ilog2(v: u128) -> u32 { - assert!(v != 0); - u128::BITS - 1 - v.leading_zeros() -} - #[cfg(any(test, feature = "unstable-public-internals"))] mod hex_fmt { use core::fmt; diff --git a/compiler-builtins/rust-version b/compiler-builtins/rust-version index 6a2835bc2d9eb..aa3876b14a221 100644 --- a/compiler-builtins/rust-version +++ b/compiler-builtins/rust-version @@ -1 +1 @@ -23d01cd2412583491621ab1ca4f1b01e37d11e39 +db3e99bbab28c6ca778b13222becdea54533d908 diff --git a/compiler-builtins/triagebot.toml b/compiler-builtins/triagebot.toml index b210a5fb52563..d0cdb497edbad 100644 --- a/compiler-builtins/triagebot.toml +++ b/compiler-builtins/triagebot.toml @@ -10,7 +10,7 @@ exclude_titles = ["Rustc pull update"] # when commits are included in subtrees, as well as warning links in commits. # Documentation at: https://forge.rust-lang.org/triagebot/issue-links.html [issue-links] -check-commits = false +check-commits = "uncanonicalized" # Enable issue transfers within the org # Documentation at: https://forge.rust-lang.org/triagebot/transfer.html diff --git a/core/src/alloc/global.rs b/core/src/alloc/global.rs index 9b80e3b70fa2f..bf3d3e0a5aca7 100644 --- a/core/src/alloc/global.rs +++ b/core/src/alloc/global.rs @@ -57,7 +57,7 @@ use crate::{cmp, ptr}; /// let mut allocated = 0; /// if self /// .remaining -/// .fetch_update(Relaxed, Relaxed, |mut remaining| { +/// .try_update(Relaxed, Relaxed, |mut remaining| { /// if size > remaining { /// return None; /// } @@ -284,9 +284,10 @@ pub unsafe trait GlobalAlloc { /// [`handle_alloc_error`]: ../../alloc/alloc/fn.handle_alloc_error.html #[stable(feature = "global_alloc", since = "1.28.0")] unsafe fn realloc(&self, ptr: *mut u8, layout: Layout, new_size: usize) -> *mut u8 { - // SAFETY: the caller must ensure that the `new_size` does not overflow. - // `layout.align()` comes from a `Layout` and is thus guaranteed to be valid. - let new_layout = unsafe { Layout::from_size_align_unchecked(new_size, layout.align()) }; + let alignment = layout.alignment(); + // SAFETY: the caller must ensure that the `new_size` does not overflow + // when rounded up to the next multiple of `alignment`. + let new_layout = unsafe { Layout::from_size_alignment_unchecked(new_size, alignment) }; // SAFETY: the caller must ensure that `new_layout` is greater than zero. let new_ptr = unsafe { self.alloc(new_layout) }; if !new_ptr.is_null() { diff --git a/core/src/any.rs b/core/src/any.rs index 42f332f7d8ba8..71a529400511c 100644 --- a/core/src/any.rs +++ b/core/src/any.rs @@ -86,7 +86,10 @@ #![stable(feature = "rust1", since = "1.0.0")] -use crate::{fmt, hash, intrinsics, ptr}; +use crate::intrinsics::{self, type_id_vtable}; +use crate::mem::transmute; +use crate::mem::type_info::{TraitImpl, TypeKind}; +use crate::{fmt, hash, ptr}; /////////////////////////////////////////////////////////////////////////////// // Any trait @@ -788,6 +791,67 @@ impl TypeId { const { intrinsics::type_id::() } } + /// Checks if the [TypeId] implements the trait. If it does it returns [TraitImpl] which can be used to build a fat pointer. + /// It can only be called at compile time. `self` must be the [TypeId] of a sized type or None will be returned. + /// + /// # Examples + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::{TypeId}; + /// + /// pub trait Blah {} + /// impl Blah for u8 {} + /// + /// assert!(const { TypeId::of::().trait_info_of::() }.is_some()); + /// assert!(const { TypeId::of::().trait_info_of::() }.is_none()); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + pub const fn trait_info_of< + T: ptr::Pointee> + ?Sized + 'static, + >( + self, + ) -> Option> { + // SAFETY: The vtable was obtained for `T`, so it is guaranteed to be `DynMetadata`. + // The intrinsic can't infer this because it is designed to work with arbitrary TypeIds. + unsafe { transmute(self.trait_info_of_trait_type_id(const { TypeId::of::() })) } + } + + /// Checks if the [TypeId] implements the trait of `trait_represented_by_type_id`. If it does it returns [TraitImpl] which can be used to build a fat pointer. + /// It can only be called at compile time. `self` must be the [TypeId] of a sized type or None will be returned. + /// + /// # Examples + /// + /// ``` + /// #![feature(type_info)] + /// use std::any::{TypeId}; + /// + /// pub trait Blah {} + /// impl Blah for u8 {} + /// + /// assert!(const { TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()) }.is_some()); + /// assert!(const { TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()) }.is_none()); + /// ``` + #[unstable(feature = "type_info", issue = "146922")] + #[rustc_const_unstable(feature = "type_info", issue = "146922")] + pub const fn trait_info_of_trait_type_id( + self, + trait_represented_by_type_id: TypeId, + ) -> Option> { + if self.info().size.is_none() { + return None; + } + + if matches!(trait_represented_by_type_id.info().kind, TypeKind::DynTrait(_)) + && let Some(vtable) = type_id_vtable(self, trait_represented_by_type_id) + { + Some(TraitImpl { vtable }) + } else { + None + } + } + fn as_u128(self) -> u128 { let mut bytes = [0; 16]; @@ -948,7 +1012,8 @@ pub const fn try_as_dyn< >( t: &T, ) -> Option<&U> { - let vtable: Option> = const { intrinsics::vtable_for::() }; + let vtable: Option> = + const { TypeId::of::().trait_info_of::().as_ref().map(TraitImpl::get_vtable) }; match vtable { Some(dyn_metadata) => { let pointer = ptr::from_raw_parts(t, dyn_metadata); @@ -1001,7 +1066,8 @@ pub const fn try_as_dyn_mut< >( t: &mut T, ) -> Option<&mut U> { - let vtable: Option> = const { intrinsics::vtable_for::() }; + let vtable: Option> = + const { TypeId::of::().trait_info_of::().as_ref().map(TraitImpl::get_vtable) }; match vtable { Some(dyn_metadata) => { let pointer = ptr::from_raw_parts_mut(t, dyn_metadata); diff --git a/core/src/array/drain.rs b/core/src/array/drain.rs index 1c6137191324c..17792dca583d2 100644 --- a/core/src/array/drain.rs +++ b/core/src/array/drain.rs @@ -31,7 +31,6 @@ impl<'l, 'f, T, U, const N: usize, F: FnMut(T) -> U> Drain<'l, 'f, T, N, F> { } /// See [`Drain::new`]; this is our fake iterator. -#[rustc_const_unstable(feature = "array_try_map", issue = "79711")] #[unstable(feature = "array_try_map", issue = "79711")] pub(super) struct Drain<'l, 'f, T, const N: usize, F> { // FIXME(const-hack): This is essentially a slice::IterMut<'static>, replace when possible. diff --git a/core/src/array/mod.rs b/core/src/array/mod.rs index 6cca2e6358b63..4a2cf15277441 100644 --- a/core/src/array/mod.rs +++ b/core/src/array/mod.rs @@ -516,20 +516,47 @@ impl [T; N] { /// /// # Note on performance and stack usage /// - /// Unfortunately, usages of this method are currently not always optimized - /// as well as they could be. This mainly concerns large arrays, as mapping - /// over small arrays seem to be optimized just fine. Also note that in - /// debug mode (i.e. without any optimizations), this method can use a lot - /// of stack space (a few times the size of the array or more). - /// - /// Therefore, in performance-critical code, try to avoid using this method - /// on large arrays or check the emitted code. Also try to avoid chained - /// maps (e.g. `arr.map(...).map(...)`). - /// - /// In many cases, you can instead use [`Iterator::map`] by calling `.iter()` - /// or `.into_iter()` on your array. `[T; N]::map` is only necessary if you - /// really need a new array of the same size as the result. Rust's lazy - /// iterators tend to get optimized very well. + /// Note that this method is *eager*. It evaluates `f` all `N` times before + /// returning the new array. + /// + /// That means that `arr.map(f).map(g)` is, in general, *not* equivalent to + /// `array.map(|x| g(f(x)))`, as the former calls `f` 4 times then `g` 4 times, + /// whereas the latter interleaves the calls (`fgfgfgfg`). + /// + /// A consequence of this is that it can have fairly-high stack usage, especially + /// in debug mode or for long arrays. The backend may be able to optimize it + /// away, but especially for complicated mappings it might not be able to. + /// + /// If you're doing a one-step `map` and really want an array as the result, + /// then absolutely use this method. Its implementation uses a bunch of tricks + /// to help the optimizer handle it well. Particularly for simple arrays, + /// like `[u8; 3]` or `[f32; 4]`, there's nothing to be concerned about. + /// + /// However, if you don't actually need an *array* of the results specifically, + /// just to process them, then you likely want [`Iterator::map`] instead. + /// + /// For example, rather than doing an array-to-array map of all the elements + /// in the array up-front and only iterating after that completes, + /// + /// ``` + /// # let my_array = [1, 2, 3]; + /// # let f = |x: i32| x + 1; + /// for x in my_array.map(f) { + /// // ... + /// } + /// ``` + /// + /// It's often better to use an iterator along the lines of + /// + /// ``` + /// # let my_array = [1, 2, 3]; + /// # let f = |x: i32| x + 1; + /// for x in my_array.into_iter().map(f) { + /// // ... + /// } + /// ``` + /// + /// as that's more likely to avoid large temporaries. /// /// /// # Examples diff --git a/core/src/ascii/ascii_char.rs b/core/src/ascii/ascii_char.rs index d77fafed2039b..ec3e551056fee 100644 --- a/core/src/ascii/ascii_char.rs +++ b/core/src/ascii/ascii_char.rs @@ -878,7 +878,7 @@ impl AsciiChar { /// # Examples /// /// ``` - /// #![feature(ascii_char, ascii_char_variants, is_ascii_octdigit)] + /// #![feature(ascii_char, ascii_char_variants)] /// /// use std::ascii; /// diff --git a/core/src/bstr/mod.rs b/core/src/bstr/mod.rs index 34e1ea66c99ad..2be7dfc9bfdda 100644 --- a/core/src/bstr/mod.rs +++ b/core/src/bstr/mod.rs @@ -174,39 +174,38 @@ impl fmt::Debug for ByteStr { #[unstable(feature = "bstr", issue = "134915")] impl fmt::Display for ByteStr { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - fn fmt_nopad(this: &ByteStr, f: &mut fmt::Formatter<'_>) -> fmt::Result { - for chunk in this.utf8_chunks() { - f.write_str(chunk.valid())?; - if !chunk.invalid().is_empty() { - f.write_str("\u{FFFD}")?; - } - } - Ok(()) - } - - let Some(align) = f.align() else { - return fmt_nopad(self, f); - }; let nchars: usize = self .utf8_chunks() .map(|chunk| { chunk.valid().chars().count() + if chunk.invalid().is_empty() { 0 } else { 1 } }) .sum(); + let padding = f.width().unwrap_or(0).saturating_sub(nchars); let fill = f.fill(); - let (lpad, rpad) = match align { - fmt::Alignment::Left => (0, padding), - fmt::Alignment::Right => (padding, 0), - fmt::Alignment::Center => { + + let (lpad, rpad) = match f.align() { + Some(fmt::Alignment::Right) => (padding, 0), + Some(fmt::Alignment::Center) => { let half = padding / 2; (half, half + padding % 2) } + // Either alignment is not specified or it's left aligned + // which behaves the same with padding + _ => (0, padding), }; + for _ in 0..lpad { write!(f, "{fill}")?; } - fmt_nopad(self, f)?; + + for chunk in self.utf8_chunks() { + f.write_str(chunk.valid())?; + if !chunk.invalid().is_empty() { + f.write_str("\u{FFFD}")?; + } + } + for _ in 0..rpad { write!(f, "{fill}")?; } diff --git a/core/src/bstr/traits.rs b/core/src/bstr/traits.rs index ff46bb13ba4eb..7da6c5f13cce1 100644 --- a/core/src/bstr/traits.rs +++ b/core/src/bstr/traits.rs @@ -45,8 +45,7 @@ impl hash::Hash for ByteStr { #[unstable(feature = "bstr_internals", issue = "none")] macro_rules! impl_partial_eq { ($lhs:ty, $rhs:ty) => { - #[allow(unused_lifetimes)] - impl<'a> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { let other: &[u8] = other.as_ref(); @@ -54,8 +53,7 @@ macro_rules! impl_partial_eq { } } - #[allow(unused_lifetimes)] - impl<'a> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { let this: &[u8] = self.as_ref(); @@ -76,9 +74,8 @@ macro_rules! impl_partial_eq_ord { ($lhs:ty, $rhs:ty) => { $crate::bstr::impl_partial_eq!($lhs, $rhs); - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { let other: &[u8] = other.as_ref(); @@ -86,9 +83,8 @@ macro_rules! impl_partial_eq_ord { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] - impl<'a> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { let this: &[u8] = self.as_ref(); @@ -107,7 +103,6 @@ pub use impl_partial_eq_ord; #[unstable(feature = "bstr_internals", issue = "none")] macro_rules! impl_partial_eq_n { ($lhs:ty, $rhs:ty) => { - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] impl PartialEq<$rhs> for $lhs { #[inline] @@ -117,7 +112,6 @@ macro_rules! impl_partial_eq_n { } } - #[allow(unused_lifetimes)] #[unstable(feature = "bstr", issue = "134915")] impl PartialEq<$lhs> for $rhs { #[inline] diff --git a/core/src/cell.rs b/core/src/cell.rs index 661ea4ab6a27f..28c3db6985369 100644 --- a/core/src/cell.rs +++ b/core/src/cell.rs @@ -689,6 +689,30 @@ impl, U> CoerceUnsized> for Cell {} #[unstable(feature = "dispatch_from_dyn", issue = "none")] impl, U> DispatchFromDyn> for Cell {} +#[stable(feature = "more_conversion_trait_impls", since = "CURRENT_RUSTC_VERSION")] +impl AsRef<[Cell; N]> for Cell<[T; N]> { + #[inline] + fn as_ref(&self) -> &[Cell; N] { + self.as_array_of_cells() + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "CURRENT_RUSTC_VERSION")] +impl AsRef<[Cell]> for Cell<[T; N]> { + #[inline] + fn as_ref(&self) -> &[Cell] { + &*self.as_array_of_cells() + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "CURRENT_RUSTC_VERSION")] +impl AsRef<[Cell]> for Cell<[T]> { + #[inline] + fn as_ref(&self) -> &[Cell] { + self.as_slice_of_cells() + } +} + impl Cell<[T]> { /// Returns a `&[Cell]` from a `&Cell<[T]>` /// @@ -750,7 +774,6 @@ impl Cell<[T; N]> { /// following is unsound: /// /// ```rust -/// #![feature(cell_get_cloned)] /// # use std::cell::Cell; /// /// #[derive(Copy, Debug)] diff --git a/core/src/cmp.rs b/core/src/cmp.rs index 78ea1f1113258..b3dc435dda176 100644 --- a/core/src/cmp.rs +++ b/core/src/cmp.rs @@ -336,16 +336,24 @@ pub macro PartialEq($item:item) { #[rustc_diagnostic_item = "Eq"] #[rustc_const_unstable(feature = "const_cmp", issue = "143800")] pub const trait Eq: [const] PartialEq + PointeeSized { - // this method is used solely by `impl Eq or #[derive(Eq)]` to assert that every component of a - // type implements `Eq` itself. The current deriving infrastructure means doing this assertion - // without using a method on this trait is nearly impossible. + // This method was used solely by `#[derive(Eq)]` to assert that every component of a + // type implements `Eq` itself. // // This should never be implemented by hand. #[doc(hidden)] #[coverage(off)] #[inline] #[stable(feature = "rust1", since = "1.0.0")] + #[rustc_diagnostic_item = "assert_receiver_is_total_eq"] + #[deprecated(since = "1.95.0", note = "implementation detail of `#[derive(Eq)]`")] fn assert_receiver_is_total_eq(&self) {} + + // FIXME (#152504): this method is used solely by `#[derive(Eq)]` to assert that + // every component of a type implements `Eq` itself. It will be removed again soon. + #[doc(hidden)] + #[coverage(off)] + #[unstable(feature = "derive_eq_internals", issue = "none")] + fn assert_fields_are_eq(&self) {} } /// Derive macro generating an impl of the trait [`Eq`]. diff --git a/core/src/convert/num.rs b/core/src/convert/num.rs index 6e82e3356410c..40d61de50aaf2 100644 --- a/core/src/convert/num.rs +++ b/core/src/convert/num.rs @@ -198,11 +198,11 @@ macro_rules! impl_float_from_bool { /// # Examples /// ``` $($(#[doc = $doctest_prefix])*)? - #[doc = concat!("let x: ", stringify!($float)," = false.into();")] + #[doc = concat!("let x = ", stringify!($float), "::from(false);")] /// assert_eq!(x, 0.0); /// assert!(x.is_sign_positive()); /// - #[doc = concat!("let y: ", stringify!($float)," = true.into();")] + #[doc = concat!("let y = ", stringify!($float), "::from(true);")] /// assert_eq!(y, 1.0); $($(#[doc = $doctest_suffix])*)? /// ``` @@ -219,6 +219,7 @@ impl_float_from_bool!( f16; doctest_prefix: // rustdoc doesn't remove the conventional space after the `///` + ///# #![allow(unused_features)] ///#![feature(f16)] ///# #[cfg(all(target_arch = "x86_64", target_os = "linux"))] { /// @@ -230,6 +231,7 @@ impl_float_from_bool!(f64); impl_float_from_bool!( f128; doctest_prefix: + ///# #![allow(unused_features)] ///#![feature(f128)] ///# #[cfg(all(target_arch = "x86_64", target_os = "linux"))] { /// @@ -341,11 +343,11 @@ macro_rules! impl_try_from_integer_for_bool { /// # Examples /// /// ``` - #[doc = concat!("assert_eq!(0_", stringify!($int), ".try_into(), Ok(false));")] + #[doc = concat!("assert_eq!(bool::try_from(0_", stringify!($int), "), Ok(false));")] /// - #[doc = concat!("assert_eq!(1_", stringify!($int), ".try_into(), Ok(true));")] + #[doc = concat!("assert_eq!(bool::try_from(1_", stringify!($int), "), Ok(true));")] /// - #[doc = concat!("assert!(<", stringify!($int), " as TryInto>::try_into(2).is_err());")] + #[doc = concat!("assert!(bool::try_from(2_", stringify!($int), ").is_err());")] /// ``` #[inline] fn try_from(i: $int) -> Result { diff --git a/core/src/ffi/va_list.rs b/core/src/ffi/va_list.rs index d0f155316a109..b6dfe3a541842 100644 --- a/core/src/ffi/va_list.rs +++ b/core/src/ffi/va_list.rs @@ -183,7 +183,44 @@ crate::cfg_select! { } } -/// A variable argument list, equivalent to `va_list` in C. +/// A variable argument list, ABI-compatible with `va_list` in C. +/// +/// This type is created in c-variadic functions when `...` is desugared. A `VaList` +/// is automatically initialized (equivalent to calling `va_start` in C). +/// +/// ``` +/// #![feature(c_variadic)] +/// +/// use std::ffi::VaList; +/// +/// /// # Safety +/// /// Must be passed at least `count` arguments of type `i32`. +/// unsafe extern "C" fn my_func(count: u32, ap: ...) -> i32 { +/// unsafe { vmy_func(count, ap) } +/// } +/// +/// /// # Safety +/// /// Must be passed at least `count` arguments of type `i32`. +/// unsafe fn vmy_func(count: u32, mut ap: VaList<'_>) -> i32 { +/// let mut sum = 0; +/// for _ in 0..count { +/// sum += unsafe { ap.arg::() }; +/// } +/// sum +/// } +/// +/// assert_eq!(unsafe { my_func(1, 42i32) }, 42); +/// assert_eq!(unsafe { my_func(3, 42i32, -7i32, 20i32) }, 55); +/// ``` +/// +/// The [`VaList::arg`] method can be used to read an argument from the list. This method +/// automatically advances the `VaList` to the next argument. The C equivalent is `va_arg`. +/// +/// Cloning a `VaList` performs the equivalent of C `va_copy`, producing an independent cursor +/// that arguments can be read from without affecting the original. Dropping a `VaList` performs +/// the equivalent of C `va_end`. +/// +/// This can be used across an FFI boundary, and fully matches the platform's `va_list`. #[repr(transparent)] #[lang = "va_list"] pub struct VaList<'a> { @@ -200,12 +237,13 @@ impl fmt::Debug for VaList<'_> { impl VaList<'_> { // Helper used in the implementation of the `va_copy` intrinsic. - pub(crate) fn duplicate(&self) -> Self { - Self { inner: self.inner.clone(), _marker: self._marker } + pub(crate) const fn duplicate(&self) -> Self { + Self { inner: self.inner, _marker: self._marker } } } -impl Clone for VaList<'_> { +#[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] +impl<'f> const Clone for VaList<'f> { #[inline] fn clone(&self) -> Self { // We only implement Clone and not Copy because some future target might not be able to @@ -216,7 +254,8 @@ impl Clone for VaList<'_> { } } -impl<'f> Drop for VaList<'f> { +#[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] +impl<'f> const Drop for VaList<'f> { fn drop(&mut self) { // SAFETY: this variable argument list is being dropped, so won't be read from again. unsafe { va_end(self) } @@ -276,22 +315,20 @@ unsafe impl VaArgSafe for *mut T {} unsafe impl VaArgSafe for *const T {} impl<'f> VaList<'f> { - /// Advance to and read the next variable argument. + /// Read an argument from the variable argument list, and advance to the next argument. /// - /// # Safety + /// Only types that implement [`VaArgSafe`] can be read from a variable argument list. /// - /// This function is only sound to call when: + /// # Safety /// - /// - there is a next variable argument available. - /// - the next argument's type must be ABI-compatible with the type `T`. - /// - the next argument must have a properly initialized value of type `T`. + /// This function is only sound to call when there is another argument to read, and that + /// argument is a properly initialized value of the type `T`. /// /// Calling this function with an incompatible type, an invalid value, or when there /// are no more variable arguments, is unsound. - /// - /// [valid]: https://doc.rust-lang.org/nightly/nomicon/what-unsafe-does.html #[inline] - pub unsafe fn arg(&mut self) -> T { + #[rustc_const_unstable(feature = "const_c_variadic", issue = "151787")] + pub const unsafe fn arg(&mut self) -> T { // SAFETY: the caller must uphold the safety contract for `va_arg`. unsafe { va_arg(self) } } diff --git a/core/src/field.rs b/core/src/field.rs new file mode 100644 index 0000000000000..e8ef309b9c84f --- /dev/null +++ b/core/src/field.rs @@ -0,0 +1,83 @@ +//! Field Reflection + +use crate::marker::PhantomData; + +/// Field Representing Type +#[unstable(feature = "field_representing_type_raw", issue = "none")] +#[lang = "field_representing_type"] +#[expect(missing_debug_implementations)] +#[fundamental] +pub struct FieldRepresentingType { + _phantom: PhantomData, +} + +// SAFETY: `FieldRepresentingType` doesn't contain any `T` +unsafe impl Send + for FieldRepresentingType +{ +} + +// SAFETY: `FieldRepresentingType` doesn't contain any `T` +unsafe impl Sync + for FieldRepresentingType +{ +} + +impl Copy + for FieldRepresentingType +{ +} + +impl Clone + for FieldRepresentingType +{ + fn clone(&self) -> Self { + *self + } +} + +/// Expands to the field representing type of the given field. +/// +/// The container type may be a tuple, `struct`, `union` or `enum`. In the case of an enum, the +/// variant must also be specified. Only a single field is supported. +#[unstable(feature = "field_projections", issue = "145383")] +#[allow_internal_unstable(field_representing_type_raw, builtin_syntax)] +// NOTE: when stabilizing this macro, we can never add new trait impls for `FieldRepresentingType`, +// since it is `#[fundamental]` and thus could break users of this macro, since the compiler expands +// it to `FieldRepresentingType<...>`. Thus stabilizing this requires careful thought about the +// completeness of the trait impls for `FieldRepresentingType`. +pub macro field_of($Container:ty, $($fields:expr)+ $(,)?) { + builtin # field_of($Container, $($fields)+) +} + +/// Type representing a field of a `struct`, `union`, `enum` variant or tuple. +/// +/// # Safety +/// +/// Given a valid value of type `Self::Base`, there exists a valid value of type `Self::Type` at +/// byte offset `OFFSET` +#[lang = "field"] +#[unstable(feature = "field_projections", issue = "145383")] +#[rustc_deny_explicit_impl] +#[rustc_dyn_incompatible_trait] +// NOTE: the compiler provides the impl of `Field` for `FieldRepresentingType` when it can guarantee +// the safety requirements of this trait. It also has to manually add the correct trait bounds on +// associated types (and the `Self` type). Thus any changes to the bounds here must be reflected in +// the old and new trait solver: +// - `fn assemble_candidates_for_field_trait` in +// `compiler/rustc_trait_selection/src/traits/select/candidate_assembly.rs`, and +// - `fn consider_builtin_field_candidate` in +// `compiler/rustc_next_trait_solver/src/solve/trait_goals.rs`. +pub unsafe trait Field: Send + Sync + Copy { + /// The type of the base where this field exists in. + #[lang = "field_base"] + type Base; + + /// The type of the field. + #[lang = "field_type"] + type Type; + + /// The offset of the field in bytes. + #[lang = "field_offset"] + const OFFSET: usize = crate::intrinsics::field_offset::(); +} diff --git a/core/src/hint.rs b/core/src/hint.rs index dccac26e07e69..3692420be8fcc 100644 --- a/core/src/hint.rs +++ b/core/src/hint.rs @@ -724,7 +724,6 @@ pub const fn unlikely(b: bool) -> bool { /// # Examples /// /// ``` -/// #![feature(cold_path)] /// use core::hint::cold_path; /// /// fn foo(x: &[i32]) { @@ -750,7 +749,6 @@ pub const fn unlikely(b: bool) -> bool { /// than the branch: /// /// ``` -/// #![feature(cold_path)] /// use core::hint::cold_path; /// /// #[inline(always)] @@ -777,7 +775,8 @@ pub const fn unlikely(b: bool) -> bool { /// } /// } /// ``` -#[unstable(feature = "cold_path", issue = "136873")] +#[stable(feature = "cold_path", since = "CURRENT_RUSTC_VERSION")] +#[rustc_const_stable(feature = "cold_path", since = "CURRENT_RUSTC_VERSION")] #[inline(always)] pub const fn cold_path() { crate::intrinsics::cold_path() diff --git a/core/src/index.rs b/core/src/index.rs index 3baefdf10cecb..70372163c6e17 100644 --- a/core/src/index.rs +++ b/core/src/index.rs @@ -315,7 +315,7 @@ unsafe impl SliceIndex<[T]> for Clamp> { } #[unstable(feature = "sliceindex_wrappers", issue = "146179")] -unsafe impl SliceIndex<[T]> for Clamp> { +unsafe impl SliceIndex<[T]> for Clamp> { type Output = [T]; fn get(self, slice: &[T]) -> Option<&Self::Output> { @@ -408,7 +408,7 @@ unsafe impl SliceIndex<[T]> for Clamp> { } #[unstable(feature = "sliceindex_wrappers", issue = "146179")] -unsafe impl SliceIndex<[T]> for Clamp { +unsafe impl SliceIndex<[T]> for Clamp { type Output = [T]; fn get(self, slice: &[T]) -> Option<&Self::Output> { diff --git a/core/src/intrinsics/fallback.rs b/core/src/intrinsics/fallback.rs index 932537f2581f8..aa9033ee3d260 100644 --- a/core/src/intrinsics/fallback.rs +++ b/core/src/intrinsics/fallback.rs @@ -218,3 +218,38 @@ macro_rules! impl_funnel_shifts { impl_funnel_shifts! { u8, u16, u32, u64, u128, usize } + +#[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] +pub const trait CarrylessMul: Copy + 'static { + /// See [`super::carryless_mul`]; we just need the trait indirection to handle + /// different types since calling intrinsics with generics doesn't work. + fn carryless_mul(self, rhs: Self) -> Self; +} + +macro_rules! impl_carryless_mul{ + ($($type:ident),*) => {$( + #[rustc_const_unstable(feature = "core_intrinsics_fallbacks", issue = "none")] + impl const CarrylessMul for $type { + #[inline] + fn carryless_mul(self, rhs: Self) -> Self { + let mut result = 0; + let mut i = 0; + + while i < $type::BITS { + // If the i-th bit in rhs is set. + if (rhs >> i) & 1 != 0 { + // Then xor the result with `self` shifted to the left by i positions. + result ^= self << i; + } + i += 1; + } + + result + } + } + )*}; +} + +impl_carryless_mul! { + u8, u16, u32, u64, u128, usize +} diff --git a/core/src/intrinsics/mod.rs b/core/src/intrinsics/mod.rs index 051dda731881f..7e9adc1e8d571 100644 --- a/core/src/intrinsics/mod.rs +++ b/core/src/intrinsics/mod.rs @@ -409,8 +409,7 @@ pub const unsafe fn assume(b: bool) { /// Therefore, implementations must not require the user to uphold /// any safety invariants. /// -/// This intrinsic does not have a stable counterpart. -#[unstable(feature = "core_intrinsics", issue = "none")] +/// The stabilized version of this intrinsic is [`core::hint::cold_path`]. #[rustc_intrinsic] #[rustc_nounwind] #[miri::intrinsic_fallback_is_spec] @@ -2179,6 +2178,19 @@ pub const unsafe fn unchecked_funnel_shr( unsafe { a.unchecked_funnel_shr(b, shift) } } +/// Carryless multiply. +/// +/// Safe versions of this intrinsic are available on the integer primitives +/// via the `carryless_mul` method. For example, [`u32::carryless_mul`]. +#[rustc_intrinsic] +#[rustc_nounwind] +#[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] +#[unstable(feature = "uint_carryless_mul", issue = "152080")] +#[miri::intrinsic_fallback_is_spec] +pub const fn carryless_mul(a: T, b: T) -> T { + a.carryless_mul(b) +} + /// This is an implementation detail of [`crate::ptr::read`] and should /// not be used anywhere else. See its comments for why this exists. /// @@ -2739,18 +2751,6 @@ pub unsafe fn vtable_size(ptr: *const ()) -> usize; #[rustc_intrinsic] pub unsafe fn vtable_align(ptr: *const ()) -> usize; -/// The intrinsic returns the `U` vtable for `T` if `T` can be coerced to the trait object type `U`. -/// -/// # Compile-time failures -/// Determining whether `T` can be coerced to the trait object type `U` requires trait resolution by the compiler. -/// In some cases, that resolution can exceed the recursion limit, -/// and compilation will fail instead of this function returning `None`. -#[rustc_nounwind] -#[unstable(feature = "core_intrinsics", issue = "none")] -#[rustc_intrinsic] -pub const fn vtable_for> + ?Sized>() --> Option>; - /// The size of a type in bytes. /// /// Note that, unlike most intrinsics, this is safe to call; @@ -2812,6 +2812,20 @@ pub const fn align_of() -> usize; #[lang = "offset_of"] pub const fn offset_of(variant: u32, field: u32) -> usize; +/// The offset of a field queried by its field representing type. +/// +/// Returns the offset of the field represented by `F`. This function essentially does the same as +/// the [`offset_of`] intrinsic, but expects the field to be represented by a generic rather than +/// the variant and field indices. This also is a safe intrinsic and can only be evaluated at +/// compile-time, so it should only appear in constants or inline const blocks. +/// +/// There should be no need to call this intrinsic manually, as its value is used to define +/// [`Field::OFFSET`](crate::field::Field::OFFSET), which is publicly accessible. +#[rustc_intrinsic] +#[unstable(feature = "field_projections", issue = "145383")] +#[rustc_const_unstable(feature = "field_projections", issue = "145383")] +pub const fn field_offset() -> usize; + /// Returns the number of variants of the type `T` cast to a `usize`; /// if `T` has no variants, returns `0`. Uninhabited variants will be counted. /// @@ -2852,6 +2866,20 @@ pub const unsafe fn size_of_val(ptr: *const T) -> usize; #[rustc_intrinsic_const_stable_indirect] pub const unsafe fn align_of_val(ptr: *const T) -> usize; +#[rustc_intrinsic] +#[unstable(feature = "core_intrinsics", issue = "none")] +/// Check if a type represented by a `TypeId` implements a trait represented by a `TypeId`. +/// It can only be called at compile time, the backends do +/// not implement it. If it implements the trait the dyn metadata gets returned for vtable access. +pub const fn type_id_vtable( + _id: crate::any::TypeId, + _trait: crate::any::TypeId, +) -> Option> { + panic!( + "`TypeId::trait_info_of` and `trait_info_of_trait_type_id` can only be called at compile-time" + ) +} + /// Compute the type information of a concrete type. /// It can only be called at compile time, the backends do /// not implement it. @@ -2887,7 +2915,7 @@ pub const fn type_name() -> &'static str; #[rustc_nounwind] #[unstable(feature = "core_intrinsics", issue = "none")] #[rustc_intrinsic] -pub const fn type_id() -> crate::any::TypeId; +pub const fn type_id() -> crate::any::TypeId; /// Tests (at compile-time) if two [`crate::any::TypeId`] instances identify the /// same type. This is necessary because at const-eval time the actual discriminating @@ -3473,7 +3501,7 @@ pub(crate) const fn miri_promise_symbolic_alignment(ptr: *const (), align: usize /// #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn va_arg(ap: &mut VaList<'_>) -> T; +pub const unsafe fn va_arg(ap: &mut VaList<'_>) -> T; /// Duplicates a variable argument list. The returned list is initially at the same position as /// the one in `src`, but can be advanced independently. @@ -3485,7 +3513,7 @@ pub unsafe fn va_arg(ap: &mut VaList<'_>) -> T; /// when a variable argument list is used incorrectly. #[rustc_intrinsic] #[rustc_nounwind] -pub fn va_copy<'f>(src: &VaList<'f>) -> VaList<'f> { +pub const fn va_copy<'f>(src: &VaList<'f>) -> VaList<'f> { src.duplicate() } @@ -3504,6 +3532,6 @@ pub fn va_copy<'f>(src: &VaList<'f>) -> VaList<'f> { /// #[rustc_intrinsic] #[rustc_nounwind] -pub unsafe fn va_end(ap: &mut VaList<'_>) { +pub const unsafe fn va_end(ap: &mut VaList<'_>) { /* deliberately does nothing */ } diff --git a/core/src/intrinsics/simd.rs b/core/src/intrinsics/simd.rs index f70262c38ae50..5fb2102c319e2 100644 --- a/core/src/intrinsics/simd.rs +++ b/core/src/intrinsics/simd.rs @@ -162,6 +162,18 @@ pub const unsafe fn simd_funnel_shl(a: T, b: T, shift: T) -> T; #[rustc_nounwind] pub const unsafe fn simd_funnel_shr(a: T, b: T, shift: T) -> T; +/// Compute the carry-less product. +/// +/// This is similar to long multiplication except that the carry is discarded. +/// +/// This operation can be used to model multiplication in `GF(2)[X]`, the polynomial +/// ring over `GF(2)`. +/// +/// `T` must be a vector of integers. +#[rustc_intrinsic] +#[rustc_nounwind] +pub unsafe fn simd_carryless_mul(a: T, b: T) -> T; + /// "And"s vectors elementwise. /// /// `T` must be a vector of integers. diff --git a/core/src/iter/traits/iterator.rs b/core/src/iter/traits/iterator.rs index d919230d094d8..9e081e65f9ad6 100644 --- a/core/src/iter/traits/iterator.rs +++ b/core/src/iter/traits/iterator.rs @@ -1908,7 +1908,7 @@ pub const trait Iterator { /// without giving up ownership of the original iterator, /// so you can use the original iterator afterwards. /// - /// Uses [`impl Iterator for &mut I { type Item = I::Item; ...}`](https://doc.rust-lang.org/nightly/std/iter/trait.Iterator.html#impl-Iterator-for-%26mut+I). + /// Uses [`impl Iterator for &mut I { type Item = I::Item; ...}`](Iterator#impl-Iterator-for-%26mut+I). /// /// # Examples /// diff --git a/core/src/lib.rs b/core/src/lib.rs index 432ca50b33613..06de9a6ce35a5 100644 --- a/core/src/lib.rs +++ b/core/src/lib.rs @@ -87,6 +87,7 @@ #![allow(incomplete_features)] #![warn(multiple_supertrait_upcastable)] #![allow(internal_features)] +#![allow(unused_features)] #![deny(ffi_unwind_calls)] #![warn(unreachable_pub)] // Do not check link redundancy on bootstrapping phase @@ -95,42 +96,23 @@ // // Library features: // tidy-alphabetical-start -#![feature(array_ptr_get)] #![feature(asm_experimental_arch)] -#![feature(bstr)] #![feature(bstr_internals)] -#![feature(cfg_select)] #![feature(cfg_target_has_reliable_f16_f128)] #![feature(const_carrying_mul_add)] #![feature(const_cmp)] #![feature(const_destruct)] #![feature(const_eval_select)] #![feature(const_select_unpredictable)] -#![feature(const_unsigned_bigint_helpers)] #![feature(core_intrinsics)] #![feature(coverage_attribute)] #![feature(disjoint_bitor)] #![feature(internal_impls_macro)] -#![feature(ip)] -#![feature(is_ascii_octdigit)] #![feature(link_cfg)] #![feature(offset_of_enum)] #![feature(panic_internals)] #![feature(pattern_type_macro)] -#![feature(ptr_alignment_type)] -#![feature(ptr_metadata)] -#![feature(set_ptr_value)] -#![feature(signed_bigint_helpers)] -#![feature(slice_ptr_get)] -#![feature(str_internals)] -#![feature(str_split_inclusive_remainder)] -#![feature(str_split_remainder)] -#![feature(type_info)] #![feature(ub_checks)] -#![feature(unsafe_pinned)] -#![feature(utf16_extra)] -#![feature(variant_count)] -#![feature(widening_mul)] // tidy-alphabetical-end // // Language features: @@ -155,10 +137,10 @@ #![feature(extern_types)] #![feature(f16)] #![feature(f128)] +#![feature(field_projections)] #![feature(freeze_impls)] #![feature(fundamental)] #![feature(funnel_shifts)] -#![feature(if_let_guard)] #![feature(intra_doc_pointers)] #![feature(intrinsics)] #![feature(lang_items)] @@ -175,9 +157,7 @@ #![feature(optimize_attribute)] #![feature(pattern_types)] #![feature(prelude_import)] -#![feature(reborrow)] #![feature(repr_simd)] -#![feature(rustc_allow_const_fn_unstable)] #![feature(rustc_attrs)] #![feature(rustdoc_internals)] #![feature(simd_ffi)] @@ -188,6 +168,7 @@ #![feature(trait_alias)] #![feature(transparent_unions)] #![feature(try_blocks)] +#![feature(uint_carryless_mul)] #![feature(unboxed_closures)] #![feature(unsized_fn_params)] #![feature(with_negative_coherence)] @@ -225,7 +206,7 @@ use prelude::rust_2024::*; #[macro_use] mod macros; -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "CURRENT_RUSTC_VERSION")] pub use crate::macros::{assert_matches, debug_assert_matches}; #[unstable(feature = "derive_from", issue = "144889")] @@ -246,7 +227,7 @@ pub mod autodiff { #[unstable(feature = "contracts", issue = "128044")] pub mod contracts; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "CURRENT_RUSTC_VERSION")] pub use crate::macros::cfg_select; #[macro_use] @@ -294,6 +275,8 @@ pub mod cmp; pub mod convert; pub mod default; pub mod error; +#[unstable(feature = "field_projections", issue = "145383")] +pub mod field; pub mod index; pub mod marker; pub mod ops; @@ -324,7 +307,7 @@ pub mod pat; pub mod pin; #[unstable(feature = "random", issue = "130703")] pub mod random; -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] pub mod range; pub mod result; pub mod sync; diff --git a/core/src/macros/mod.rs b/core/src/macros/mod.rs index 3176f3c067092..28eefd0013ca5 100644 --- a/core/src/macros/mod.rs +++ b/core/src/macros/mod.rs @@ -147,8 +147,6 @@ macro_rules! assert_ne { /// # Examples /// /// ``` -/// #![feature(assert_matches)] -/// /// use std::assert_matches; /// /// let a = Some(345); @@ -166,7 +164,7 @@ macro_rules! assert_ne { /// assert_matches!(a, Some(x) if x > 100); /// // assert_matches!(a, Some(x) if x < 100); // panics /// ``` -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "CURRENT_RUSTC_VERSION")] #[allow_internal_unstable(panic_internals)] #[rustc_macro_transparency = "semiopaque"] pub macro assert_matches { @@ -208,8 +206,6 @@ pub macro assert_matches { /// # Example /// /// ``` -/// #![feature(cfg_select)] -/// /// cfg_select! { /// unix => { /// fn foo() { /* unix specific functionality */ } @@ -227,14 +223,12 @@ pub macro assert_matches { /// right-hand side: /// /// ``` -/// #![feature(cfg_select)] -/// /// let _some_string = cfg_select! { /// unix => "With great power comes great electricity bills", /// _ => { "Behind every successful diet is an unwatched pizza" } /// }; /// ``` -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "CURRENT_RUSTC_VERSION")] #[rustc_diagnostic_item = "cfg_select"] #[rustc_builtin_macro] pub macro cfg_select($($tt:tt)*) { @@ -380,8 +374,6 @@ macro_rules! debug_assert_ne { /// # Examples /// /// ``` -/// #![feature(assert_matches)] -/// /// use std::debug_assert_matches; /// /// let a = Some(345); @@ -399,7 +391,7 @@ macro_rules! debug_assert_ne { /// debug_assert_matches!(a, Some(x) if x > 100); /// // debug_assert_matches!(a, Some(x) if x < 100); // panics /// ``` -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "CURRENT_RUSTC_VERSION")] #[allow_internal_unstable(assert_matches)] #[rustc_macro_transparency = "semiopaque"] pub macro debug_assert_matches($($arg:tt)*) { @@ -449,7 +441,7 @@ macro_rules! matches { /// [raw-identifier syntax][ris]: `r#try`. /// /// [propagating-errors]: https://doc.rust-lang.org/book/ch09-02-recoverable-errors-with-result.html#a-shortcut-for-propagating-errors-the--operator -/// [ris]: https://doc.rust-lang.org/nightly/rust-by-example/compatibility/raw_identifiers.html +/// [ris]: ../rust-by-example/compatibility/raw_identifiers.html /// /// `try!` matches the given [`Result`]. In case of the `Ok` variant, the /// expression has the value of the wrapped value. @@ -611,6 +603,9 @@ macro_rules! write { ($dst:expr, $($arg:tt)*) => { $dst.write_fmt($crate::format_args!($($arg)*)) }; + ($($arg:tt)*) => { + compile_error!("requires a destination and format arguments, like `write!(dest, \"format string\", args...)`") + }; } /// Writes formatted data into a buffer, with a newline appended. @@ -649,6 +644,9 @@ macro_rules! writeln { ($dst:expr, $($arg:tt)*) => { $dst.write_fmt($crate::format_args_nl!($($arg)*)) }; + ($($arg:tt)*) => { + compile_error!("requires a destination and format arguments, like `writeln!(dest, \"format string\", args...)`") + }; } /// Indicates unreachable code. @@ -1781,7 +1779,7 @@ pub(crate) mod builtin { /// /// See also [`std::alloc::GlobalAlloc`](../../../std/alloc/trait.GlobalAlloc.html). #[stable(feature = "global_allocator", since = "1.28.0")] - #[allow_internal_unstable(rustc_attrs)] + #[allow_internal_unstable(rustc_attrs, ptr_alignment_type)] #[rustc_builtin_macro] pub macro global_allocator($item:item) { /* compiler built-in */ diff --git a/core/src/marker.rs b/core/src/marker.rs index 57416455e9de8..7187c71799b92 100644 --- a/core/src/marker.rs +++ b/core/src/marker.rs @@ -927,14 +927,20 @@ marker_impls! { /// This is part of [RFC 3467](https://rust-lang.github.io/rfcs/3467-unsafe-pinned.html), and is /// tracked by [#125735](https://github.com/rust-lang/rust/issues/125735). #[lang = "unsafe_unpin"] -pub(crate) unsafe auto trait UnsafeUnpin {} +#[unstable(feature = "unsafe_unpin", issue = "125735")] +pub unsafe auto trait UnsafeUnpin {} +#[unstable(feature = "unsafe_unpin", issue = "125735")] impl !UnsafeUnpin for UnsafePinned {} -unsafe impl UnsafeUnpin for PhantomData {} -unsafe impl UnsafeUnpin for *const T {} -unsafe impl UnsafeUnpin for *mut T {} -unsafe impl UnsafeUnpin for &T {} -unsafe impl UnsafeUnpin for &mut T {} +marker_impls! { +#[unstable(feature = "unsafe_unpin", issue = "125735")] + unsafe UnsafeUnpin for + {T: ?Sized} PhantomData, + {T: ?Sized} *const T, + {T: ?Sized} *mut T, + {T: ?Sized} &T, + {T: ?Sized} &mut T, +} /// Types that do not require any pinning guarantees. /// @@ -1027,6 +1033,7 @@ impl !Unpin for PhantomPinned {} // continue working. Ideally PhantomPinned could just wrap an `UnsafePinned<()>` to get the same // effect, but we can't add a new field to an already stable unit struct -- that would be a breaking // change. +#[unstable(feature = "unsafe_unpin", issue = "125735")] impl !UnsafeUnpin for PhantomPinned {} marker_impls! { diff --git a/core/src/mem/maybe_uninit.rs b/core/src/mem/maybe_uninit.rs index 320eb97f83a43..5941477201933 100644 --- a/core/src/mem/maybe_uninit.rs +++ b/core/src/mem/maybe_uninit.rs @@ -1532,6 +1532,56 @@ impl MaybeUninit<[T; N]> { } } +#[stable(feature = "more_conversion_trait_impls", since = "CURRENT_RUSTC_VERSION")] +impl From<[MaybeUninit; N]> for MaybeUninit<[T; N]> { + #[inline] + fn from(arr: [MaybeUninit; N]) -> Self { + arr.transpose() + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "CURRENT_RUSTC_VERSION")] +impl AsRef<[MaybeUninit; N]> for MaybeUninit<[T; N]> { + #[inline] + fn as_ref(&self) -> &[MaybeUninit; N] { + // SAFETY: T and MaybeUninit have the same layout + unsafe { &*ptr::from_ref(self).cast() } + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "CURRENT_RUSTC_VERSION")] +impl AsRef<[MaybeUninit]> for MaybeUninit<[T; N]> { + #[inline] + fn as_ref(&self) -> &[MaybeUninit] { + &*AsRef::<[MaybeUninit; N]>::as_ref(self) + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "CURRENT_RUSTC_VERSION")] +impl AsMut<[MaybeUninit; N]> for MaybeUninit<[T; N]> { + #[inline] + fn as_mut(&mut self) -> &mut [MaybeUninit; N] { + // SAFETY: T and MaybeUninit have the same layout + unsafe { &mut *ptr::from_mut(self).cast() } + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "CURRENT_RUSTC_VERSION")] +impl AsMut<[MaybeUninit]> for MaybeUninit<[T; N]> { + #[inline] + fn as_mut(&mut self) -> &mut [MaybeUninit] { + &mut *AsMut::<[MaybeUninit; N]>::as_mut(self) + } +} + +#[stable(feature = "more_conversion_trait_impls", since = "CURRENT_RUSTC_VERSION")] +impl From> for [MaybeUninit; N] { + #[inline] + fn from(arr: MaybeUninit<[T; N]>) -> Self { + arr.transpose() + } +} + impl [MaybeUninit; N] { /// Transposes a `[MaybeUninit; N]` into a `MaybeUninit<[T; N]>`. /// diff --git a/core/src/mem/mod.rs b/core/src/mem/mod.rs index 7c486875a8268..d8521e79006e3 100644 --- a/core/src/mem/mod.rs +++ b/core/src/mem/mod.rs @@ -1260,7 +1260,10 @@ pub trait SizedTypeProperties: Sized { #[doc(hidden)] #[unstable(feature = "ptr_alignment_type", issue = "102070")] - const ALIGNMENT: Alignment = Alignment::of::(); + const ALIGNMENT: Alignment = { + // This can't panic since type alignment is always a power of two. + Alignment::new(Self::ALIGN).unwrap() + }; /// `true` if this type requires no storage. /// `false` if its [size](size_of) is greater than zero. @@ -1485,12 +1488,13 @@ pub macro offset_of($Container:ty, $($fields:expr)+ $(,)?) { /// /// [inhabited]: https://doc.rust-lang.org/reference/glossary.html#inhabited #[unstable(feature = "mem_conjure_zst", issue = "95383")] +#[rustc_const_unstable(feature = "mem_conjure_zst", issue = "95383")] pub const unsafe fn conjure_zst() -> T { const_assert!( size_of::() == 0, - "mem::conjure_zst invoked on a nonzero-sized type", - "mem::conjure_zst invoked on type {t}, which is not zero-sized", - t: &str = stringify!(T) + "mem::conjure_zst invoked on a non-zero-sized type", + "mem::conjure_zst invoked on type {name}, which is not zero-sized", + name: &str = crate::any::type_name::() ); // SAFETY: because the caller must guarantee that it's inhabited and zero-sized, diff --git a/core/src/mem/type_info.rs b/core/src/mem/type_info.rs index 8b30803c97c98..e4d47dedb8606 100644 --- a/core/src/mem/type_info.rs +++ b/core/src/mem/type_info.rs @@ -2,7 +2,9 @@ //! runtime or const-eval processable way. use crate::any::TypeId; -use crate::intrinsics::type_of; +use crate::intrinsics::{type_id, type_of}; +use crate::marker::PointeeSized; +use crate::ptr::DynMetadata; /// Compile-time type information. #[derive(Debug)] @@ -16,6 +18,21 @@ pub struct Type { pub size: Option, } +/// Info of a trait implementation, you can retrieve the vtable with [Self::get_vtable] +#[derive(Debug, PartialEq, Eq)] +#[unstable(feature = "type_info", issue = "146922")] +#[non_exhaustive] +pub struct TraitImpl { + pub(crate) vtable: DynMetadata, +} + +impl TraitImpl { + /// Gets the raw vtable for type reflection mapping + pub const fn get_vtable(&self) -> DynMetadata { + self.vtable + } +} + impl TypeId { /// Compute the type information of a concrete type. /// It can only be called at compile time. @@ -28,11 +45,17 @@ impl TypeId { impl Type { /// Returns the type information of the generic type parameter. + /// + /// Note: Unlike `TypeId`s obtained via `TypeId::of`, the `Type` + /// struct and its fields contain `TypeId`s that are not necessarily + /// derived from types that outlive `'static`. This means that using + /// the `TypeId`s (transitively) obtained from this function will + /// be able to break invariants that other `TypeId` consuming crates + /// may have assumed to hold. #[unstable(feature = "type_info", issue = "146922")] #[rustc_const_unstable(feature = "type_info", issue = "146922")] - // FIXME(reflection): don't require the 'static bound - pub const fn of() -> Self { - const { TypeId::of::().info() } + pub const fn of() -> Self { + const { type_id::().info() } } } @@ -49,6 +72,12 @@ pub enum TypeKind { Slice(Slice), /// Dynamic Traits. DynTrait(DynTrait), + /// Structs. + Struct(Struct), + /// Enums. + Enum(Enum), + /// Unions. + Union(Union), /// Primitive boolean type. Bool(Bool), /// Primitive character type. @@ -63,6 +92,8 @@ pub enum TypeKind { Reference(Reference), /// Pointers. Pointer(Pointer), + /// Function pointers. + FnPtr(FnPtr), /// FIXME(#146922): add all the common types Other, } @@ -81,6 +112,8 @@ pub struct Tuple { #[non_exhaustive] #[unstable(feature = "type_info", issue = "146922")] pub struct Field { + /// The name of the field. + pub name: &'static str, /// The field's type. pub ty: TypeId, /// Offset in bytes from the parent type @@ -137,6 +170,95 @@ pub struct Trait { pub is_auto: bool, } +/// Compile-time type information about structs. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Struct { + /// Instantiated generics of the struct. + pub generics: &'static [Generic], + /// All fields of the struct. + pub fields: &'static [Field], + /// Whether the struct field list is non-exhaustive. + pub non_exhaustive: bool, +} + +/// Compile-time type information about unions. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Union { + /// Instantiated generics of the union. + pub generics: &'static [Generic], + /// All fields of the union. + pub fields: &'static [Field], +} + +/// Compile-time type information about enums. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Enum { + /// Instantiated generics of the enum. + pub generics: &'static [Generic], + /// All variants of the enum. + pub variants: &'static [Variant], + /// Whether the enum variant list is non-exhaustive. + pub non_exhaustive: bool, +} + +/// Compile-time type information about variants of enums. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Variant { + /// The name of the variant. + pub name: &'static str, + /// All fields of the variant. + pub fields: &'static [Field], + /// Whether the enum variant fields is non-exhaustive. + pub non_exhaustive: bool, +} + +/// Compile-time type information about instantiated generics of structs, enum and union variants. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub enum Generic { + /// Lifetimes. + Lifetime(Lifetime), + /// Types. + Type(GenericType), + /// Const parameters. + Const(Const), +} + +/// Compile-time type information about generic lifetimes. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Lifetime { + // No additional information to provide for now. +} + +/// Compile-time type information about instantiated generic types. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct GenericType { + /// The type itself. + pub ty: TypeId, +} + +/// Compile-time type information about generic const parameters. +#[derive(Debug)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +pub struct Const { + /// The const's type. + pub ty: TypeId, +} + /// Compile-time type information about `bool`. #[derive(Debug)] #[non_exhaustive] @@ -202,3 +324,39 @@ pub struct Pointer { /// Whether this pointer is mutable or not. pub mutable: bool, } + +#[derive(Debug)] +#[unstable(feature = "type_info", issue = "146922")] +/// Function pointer, e.g. fn(u8), +pub struct FnPtr { + /// Unsafety, true is unsafe + pub unsafety: bool, + + /// Abi, e.g. extern "C" + pub abi: Abi, + + /// Function inputs + pub inputs: &'static [TypeId], + + /// Function return type, default is TypeId::of::<()> + pub output: TypeId, + + /// Vardiadic function, e.g. extern "C" fn add(n: usize, mut args: ...); + pub variadic: bool, +} + +#[derive(Debug, Default)] +#[non_exhaustive] +#[unstable(feature = "type_info", issue = "146922")] +/// Abi of [FnPtr] +pub enum Abi { + /// Named abi, e.g. extern "custom", "stdcall" etc. + Named(&'static str), + + /// Default + #[default] + ExternRust, + + /// C-calling convention + ExternC, +} diff --git a/core/src/num/f128.rs b/core/src/num/f128.rs index 140b955259ab8..03bc5f20d7e94 100644 --- a/core/src/num/f128.rs +++ b/core/src/num/f128.rs @@ -148,7 +148,10 @@ pub mod consts { pub const LN_10: f128 = 2.30258509299404568401799145468436420760110148862877297603333_f128; } -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), allow(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + allow(internal_features, unused_features) +)))] impl f128 { /// The radix or base of the internal representation of `f128`. #[unstable(feature = "f128", issue = "116909")] @@ -272,6 +275,70 @@ impl f128 { #[unstable(feature = "f128", issue = "116909")] pub const NEG_INFINITY: f128 = -1.0_f128 / 0.0_f128; + /// Maximum integer that can be represented exactly in an [`f128`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i128`] and [`f128`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f128`] and back to + /// [`i128`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f128`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f128::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f128::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f128)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f128)] { + /// let max_exact_int = f128::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f128 as i128); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f128 as i128); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f128 as i128); + /// + /// // Beyond `f128::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f128, (max_exact_int + 2) as f128); + /// # }} + /// ``` + // #[unstable(feature = "f128", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i128 = (1 << Self::MANTISSA_DIGITS) - 1; + + /// Minimum integer that can be represented exactly in an [`f128`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i128`] and [`f128`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f128`] and back to + /// [`i128`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f128`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f128::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f128::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f128)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f128)] { + /// let min_exact_int = f128::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f128 as i128); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f128 as i128); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f128 as i128); + /// + /// // Below `f128::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f128, (min_exact_int - 2) as f128); + /// # }} + /// ``` + // #[unstable(feature = "f128", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i128 = -Self::MAX_EXACT_INTEGER; + /// Sign bit pub(crate) const SIGN_MASK: u128 = 0x8000_0000_0000_0000_0000_0000_0000_0000; @@ -1470,7 +1537,11 @@ impl f128 { // Functions in this module fall into `core_float_math` // #[unstable(feature = "core_float_math", issue = "137578")] #[cfg(not(test))] -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), expect(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + expect(internal_features), + allow(unused_features) +)))] impl f128 { /// Returns the largest integer less than or equal to `self`. /// diff --git a/core/src/num/f16.rs b/core/src/num/f16.rs index 463f07da91b28..ef937fccb47f3 100644 --- a/core/src/num/f16.rs +++ b/core/src/num/f16.rs @@ -142,7 +142,10 @@ pub mod consts { pub const LN_10: f16 = 2.30258509299404568401799145468436421_f16; } -#[doc(test(attr(feature(cfg_target_has_reliable_f16_f128), allow(internal_features))))] +#[doc(test(attr( + feature(cfg_target_has_reliable_f16_f128), + allow(internal_features, unused_features) +)))] impl f16 { /// The radix or base of the internal representation of `f16`. #[unstable(feature = "f16", issue = "116909")] @@ -266,6 +269,70 @@ impl f16 { #[unstable(feature = "f16", issue = "116909")] pub const NEG_INFINITY: f16 = -1.0_f16 / 0.0_f16; + /// Maximum integer that can be represented exactly in an [`f16`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i16`] and [`f16`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f16`] and back to + /// [`i16`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f16`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f16::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f16::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f16)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f16)] { + /// let max_exact_int = f16::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f16 as i16); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f16 as i16); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f16 as i16); + /// + /// // Beyond `f16::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f16, (max_exact_int + 2) as f16); + /// # }} + /// ``` + // #[unstable(feature = "f16", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i16 = (1 << Self::MANTISSA_DIGITS) - 1; + + /// Minimum integer that can be represented exactly in an [`f16`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i16`] and [`f16`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f16`] and back to + /// [`i16`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f16`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f16::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f16::MIN_EXACT_INTEGER + /// ``` + /// #![feature(f16)] + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// # #[cfg(target_has_reliable_f16)] { + /// let min_exact_int = f16::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f16 as i16); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f16 as i16); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f16 as i16); + /// + /// // Below `f16::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f16, (min_exact_int - 2) as f16); + /// # }} + /// ``` + // #[unstable(feature = "f16", issue = "116909")] + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i16 = -Self::MAX_EXACT_INTEGER; + /// Sign bit pub(crate) const SIGN_MASK: u16 = 0x8000; diff --git a/core/src/num/f32.rs b/core/src/num/f32.rs index be908cb3894b7..aac81d48c1b45 100644 --- a/core/src/num/f32.rs +++ b/core/src/num/f32.rs @@ -513,6 +513,64 @@ impl f32 { #[stable(feature = "assoc_int_consts", since = "1.43.0")] pub const NEG_INFINITY: f32 = -1.0_f32 / 0.0_f32; + /// Maximum integer that can be represented exactly in an [`f32`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i32`] and [`f32`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f32`] and back to + /// [`i32`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f32`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f32::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f32::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let max_exact_int = f32::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f32 as i32); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f32 as i32); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f32 as i32); + /// + /// // Beyond `f32::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f32, (max_exact_int + 2) as f32); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i32 = (1 << Self::MANTISSA_DIGITS) - 1; + + /// Minimum integer that can be represented exactly in an [`f32`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i32`] and [`f32`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f32`] and back to + /// [`i32`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f32`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f32::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f32::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let min_exact_int = f32::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f32 as i32); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f32 as i32); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f32 as i32); + /// + /// // Below `f32::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f32, (min_exact_int - 2) as f32); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i32 = -Self::MAX_EXACT_INTEGER; + /// Sign bit pub(crate) const SIGN_MASK: u32 = 0x8000_0000; @@ -1821,6 +1879,7 @@ pub mod math { /// # Examples /// /// ``` + /// # #![allow(unused_features)] /// #![feature(core_float_math)] /// /// # // FIXME(#140515): mingw has an incorrect fma diff --git a/core/src/num/f64.rs b/core/src/num/f64.rs index 73b20a50ff8ee..bacf429e77fab 100644 --- a/core/src/num/f64.rs +++ b/core/src/num/f64.rs @@ -512,6 +512,64 @@ impl f64 { #[stable(feature = "assoc_int_consts", since = "1.43.0")] pub const NEG_INFINITY: f64 = -1.0_f64 / 0.0_f64; + /// Maximum integer that can be represented exactly in an [`f64`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i64`] and [`f64`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f64`] and back to + /// [`i64`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f64`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// [`MAX_EXACT_INTEGER`]: f64::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f64::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let max_exact_int = f64::MAX_EXACT_INTEGER; + /// assert_eq!(max_exact_int, max_exact_int as f64 as i64); + /// assert_eq!(max_exact_int + 1, (max_exact_int + 1) as f64 as i64); + /// assert_ne!(max_exact_int + 2, (max_exact_int + 2) as f64 as i64); + /// + /// // Beyond `f64::MAX_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((max_exact_int + 1) as f64, (max_exact_int + 2) as f64); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MAX_EXACT_INTEGER: i64 = (1 << Self::MANTISSA_DIGITS) - 1; + + /// Minimum integer that can be represented exactly in an [`f64`] value, + /// with no other integer converting to the same floating point value. + /// + /// For an integer `x` which satisfies `MIN_EXACT_INTEGER <= x <= MAX_EXACT_INTEGER`, + /// there is a "one-to-one" mapping between [`i64`] and [`f64`] values. + /// `MAX_EXACT_INTEGER + 1` also converts losslessly to [`f64`] and back to + /// [`i64`], but `MAX_EXACT_INTEGER + 2` converts to the same [`f64`] value + /// (and back to `MAX_EXACT_INTEGER + 1` as an integer) so there is not a + /// "one-to-one" mapping. + /// + /// This constant is equivalent to `-MAX_EXACT_INTEGER`. + /// + /// [`MAX_EXACT_INTEGER`]: f64::MAX_EXACT_INTEGER + /// [`MIN_EXACT_INTEGER`]: f64::MIN_EXACT_INTEGER + /// ``` + /// #![feature(float_exact_integer_constants)] + /// # // FIXME(#152635): Float rounding on `i586` does not adhere to IEEE 754 + /// # #[cfg(not(all(target_arch = "x86", not(target_feature = "sse"))))] { + /// let min_exact_int = f64::MIN_EXACT_INTEGER; + /// assert_eq!(min_exact_int, min_exact_int as f64 as i64); + /// assert_eq!(min_exact_int - 1, (min_exact_int - 1) as f64 as i64); + /// assert_ne!(min_exact_int - 2, (min_exact_int - 2) as f64 as i64); + /// + /// // Below `f64::MIN_EXACT_INTEGER`, multiple integers can map to one float value + /// assert_eq!((min_exact_int - 1) as f64, (min_exact_int - 2) as f64); + /// # } + /// ``` + #[unstable(feature = "float_exact_integer_constants", issue = "152466")] + pub const MIN_EXACT_INTEGER: i64 = -Self::MAX_EXACT_INTEGER; + /// Sign bit pub(crate) const SIGN_MASK: u64 = 0x8000_0000_0000_0000; @@ -1819,6 +1877,7 @@ pub mod math { /// # Examples /// /// ``` + /// # #![allow(unused_features)] /// #![feature(core_float_math)] /// /// # // FIXME(#140515): mingw has an incorrect fma diff --git a/core/src/num/int_macros.rs b/core/src/num/int_macros.rs index b21865a9ae546..d1d5790c694de 100644 --- a/core/src/num/int_macros.rs +++ b/core/src/num/int_macros.rs @@ -2481,7 +2481,8 @@ macro_rules! int_impl { /// /// Returns a tuple of the addition along with a boolean indicating /// whether an arithmetic overflow would occur. If an overflow would have - /// occurred then the wrapped value is returned. + /// occurred then the wrapped value is returned (negative if overflowed + /// above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). /// /// # Examples /// @@ -2516,6 +2517,9 @@ macro_rules! int_impl { /// The output boolean returned by this method is *not* a carry flag, /// and should *not* be added to a more significant word. /// + /// If overflow occurred, the wrapped value is returned (negative if overflowed + /// above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). + /// /// If the input carry is false, this method is equivalent to /// [`overflowing_add`](Self::overflowing_add). /// @@ -2583,7 +2587,8 @@ macro_rules! int_impl { /// Calculates `self` - `rhs`. /// /// Returns a tuple of the subtraction along with a boolean indicating whether an arithmetic overflow - /// would occur. If an overflow would have occurred then the wrapped value is returned. + /// would occur. If an overflow would have occurred then the wrapped value is returned + /// (negative if overflowed above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). /// /// # Examples /// @@ -2619,6 +2624,9 @@ macro_rules! int_impl { /// The output boolean returned by this method is *not* a borrow flag, /// and should *not* be subtracted from a more significant word. /// + /// If overflow occurred, the wrapped value is returned (negative if overflowed + /// above [`MAX`](Self::MAX), non-negative if below [`MIN`](Self::MIN)). + /// /// If the input borrow is false, this method is equivalent to /// [`overflowing_sub`](Self::overflowing_sub). /// diff --git a/core/src/num/mod.rs b/core/src/num/mod.rs index 558426c94e5dc..839a6fbdc9b7e 100644 --- a/core/src/num/mod.rs +++ b/core/src/num/mod.rs @@ -244,6 +244,104 @@ macro_rules! midpoint_impl { }; } +macro_rules! widening_carryless_mul_impl { + ($SelfT:ty, $WideT:ty) => { + /// Performs a widening carry-less multiplication. + /// + /// # Examples + /// + /// ``` + /// #![feature(uint_carryless_mul)] + /// + #[doc = concat!("assert_eq!(", stringify!($SelfT), "::MAX.widening_carryless_mul(", + stringify!($SelfT), "::MAX), ", stringify!($WideT), "::MAX / 3);")] + /// ``` + #[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] + #[doc(alias = "clmul")] + #[unstable(feature = "uint_carryless_mul", issue = "152080")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + pub const fn widening_carryless_mul(self, rhs: $SelfT) -> $WideT { + (self as $WideT).carryless_mul(rhs as $WideT) + } + } +} + +macro_rules! carrying_carryless_mul_impl { + (u128, u256) => { + carrying_carryless_mul_impl! { @internal u128 => + pub const fn carrying_carryless_mul(self, rhs: Self, carry: Self) -> (Self, Self) { + let x0 = self as u64; + let x1 = (self >> 64) as u64; + let y0 = rhs as u64; + let y1 = (rhs >> 64) as u64; + + let z0 = u64::widening_carryless_mul(x0, y0); + let z2 = u64::widening_carryless_mul(x1, y1); + + // The grade school algorithm would compute: + // z1 = x0y1 ^ x1y0 + + // Instead, Karatsuba first computes: + let z3 = u64::widening_carryless_mul(x0 ^ x1, y0 ^ y1); + // Since it distributes over XOR, + // z3 == x0y0 ^ x0y1 ^ x1y0 ^ x1y1 + // |--| |---------| |--| + // == z0 ^ z1 ^ z2 + // so we can compute z1 as + let z1 = z3 ^ z0 ^ z2; + + let lo = z0 ^ (z1 << 64); + let hi = z2 ^ (z1 >> 64); + + (lo ^ carry, hi) + } + } + }; + ($SelfT:ty, $WideT:ty) => { + carrying_carryless_mul_impl! { @internal $SelfT => + pub const fn carrying_carryless_mul(self, rhs: Self, carry: Self) -> (Self, Self) { + // Can't use widening_carryless_mul because it's not implemented for usize. + let p = (self as $WideT).carryless_mul(rhs as $WideT); + + let lo = (p as $SelfT); + let hi = (p >> Self::BITS) as $SelfT; + + (lo ^ carry, hi) + } + } + }; + (@internal $SelfT:ty => $($fn:tt)*) => { + /// Calculates the "full carryless multiplication" without the possibility to overflow. + /// + /// This returns the low-order (wrapping) bits and the high-order (overflow) bits + /// of the result as two separate values, in that order. + /// + /// # Examples + /// + /// Please note that this example is shared among integer types, which is why `u8` is used. + /// + /// ``` + /// #![feature(uint_carryless_mul)] + /// + /// assert_eq!(0b1000_0000u8.carrying_carryless_mul(0b1000_0000, 0b0000), (0, 0b0100_0000)); + /// assert_eq!(0b1000_0000u8.carrying_carryless_mul(0b1000_0000, 0b1111), (0b1111, 0b0100_0000)); + #[doc = concat!("assert_eq!(", + stringify!($SelfT), "::MAX.carrying_carryless_mul(", stringify!($SelfT), "::MAX, ", stringify!($SelfT), "::MAX), ", + "(!(", stringify!($SelfT), "::MAX / 3), ", stringify!($SelfT), "::MAX / 3));" + )] + /// ``` + #[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] + #[doc(alias = "clmul")] + #[unstable(feature = "uint_carryless_mul", issue = "152080")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline] + $($fn)* + } +} + impl i8 { int_impl! { Self = i8, @@ -458,6 +556,9 @@ impl u8 { fsh_op = "0x36", fshl_result = "0x8", fshr_result = "0x8d", + clmul_lhs = "0x12", + clmul_rhs = "0x34", + clmul_result = "0x28", swap_op = "0x12", swapped = "0x12", reversed = "0x48", @@ -468,6 +569,8 @@ impl u8 { bound_condition = "", } midpoint_impl! { u8, u16, unsigned } + widening_carryless_mul_impl! { u8, u16 } + carrying_carryless_mul_impl! { u8, u16 } /// Checks if the value is within the ASCII range. /// @@ -1095,6 +1198,9 @@ impl u16 { fsh_op = "0x2de", fshl_result = "0x30", fshr_result = "0x302d", + clmul_lhs = "0x9012", + clmul_rhs = "0xcd34", + clmul_result = "0x928", swap_op = "0x1234", swapped = "0x3412", reversed = "0x2c48", @@ -1105,6 +1211,8 @@ impl u16 { bound_condition = "", } midpoint_impl! { u16, u32, unsigned } + widening_carryless_mul_impl! { u16, u32 } + carrying_carryless_mul_impl! { u16, u32 } /// Checks if the value is a Unicode surrogate code point, which are disallowed values for [`char`]. /// @@ -1145,6 +1253,9 @@ impl u32 { fsh_op = "0x2fe78e45", fshl_result = "0xb32f", fshr_result = "0xb32fe78e", + clmul_lhs = "0x56789012", + clmul_rhs = "0xf52ecd34", + clmul_result = "0x9b980928", swap_op = "0x12345678", swapped = "0x78563412", reversed = "0x1e6a2c48", @@ -1155,6 +1266,8 @@ impl u32 { bound_condition = "", } midpoint_impl! { u32, u64, unsigned } + widening_carryless_mul_impl! { u32, u64 } + carrying_carryless_mul_impl! { u32, u64 } } impl u64 { @@ -1171,6 +1284,9 @@ impl u64 { fsh_op = "0x2fe78e45983acd98", fshl_result = "0x6e12fe", fshr_result = "0x6e12fe78e45983ac", + clmul_lhs = "0x7890123456789012", + clmul_rhs = "0xdd358416f52ecd34", + clmul_result = "0xa6299579b980928", swap_op = "0x1234567890123456", swapped = "0x5634129078563412", reversed = "0x6a2c48091e6a2c48", @@ -1181,6 +1297,8 @@ impl u64 { bound_condition = "", } midpoint_impl! { u64, u128, unsigned } + widening_carryless_mul_impl! { u64, u128 } + carrying_carryless_mul_impl! { u64, u128 } } impl u128 { @@ -1197,6 +1315,9 @@ impl u128 { fsh_op = "0x2fe78e45983acd98039000008736273", fshl_result = "0x4f7602fe", fshr_result = "0x4f7602fe78e45983acd9803900000873", + clmul_lhs = "0x12345678901234567890123456789012", + clmul_rhs = "0x4317e40ab4ddcf05dd358416f52ecd34", + clmul_result = "0xb9cf660de35d0c170a6299579b980928", swap_op = "0x12345678901234567890123456789012", swapped = "0x12907856341290785634129078563412", reversed = "0x48091e6a2c48091e6a2c48091e6a2c48", @@ -1209,6 +1330,7 @@ impl u128 { bound_condition = "", } midpoint_impl! { u128, unsigned } + carrying_carryless_mul_impl! { u128, u256 } } #[cfg(target_pointer_width = "16")] @@ -1223,9 +1345,12 @@ impl usize { rot = 4, rot_op = "0xa003", rot_result = "0x3a", - fsh_op = "0x2fe78e45983acd98039000008736273", - fshl_result = "0x4f7602fe", - fshr_result = "0x4f7602fe78e45983acd9803900000873", + fsh_op = "0x2de", + fshl_result = "0x30", + fshr_result = "0x302d", + clmul_lhs = "0x9012", + clmul_rhs = "0xcd34", + clmul_result = "0x928", swap_op = "0x1234", swapped = "0x3412", reversed = "0x2c48", @@ -1236,6 +1361,7 @@ impl usize { bound_condition = " on 16-bit targets", } midpoint_impl! { usize, u32, unsigned } + carrying_carryless_mul_impl! { usize, u32 } } #[cfg(target_pointer_width = "32")] @@ -1253,6 +1379,9 @@ impl usize { fsh_op = "0x2fe78e45", fshl_result = "0xb32f", fshr_result = "0xb32fe78e", + clmul_lhs = "0x56789012", + clmul_rhs = "0xf52ecd34", + clmul_result = "0x9b980928", swap_op = "0x12345678", swapped = "0x78563412", reversed = "0x1e6a2c48", @@ -1263,6 +1392,7 @@ impl usize { bound_condition = " on 32-bit targets", } midpoint_impl! { usize, u64, unsigned } + carrying_carryless_mul_impl! { usize, u64 } } #[cfg(target_pointer_width = "64")] @@ -1280,6 +1410,9 @@ impl usize { fsh_op = "0x2fe78e45983acd98", fshl_result = "0x6e12fe", fshr_result = "0x6e12fe78e45983ac", + clmul_lhs = "0x7890123456789012", + clmul_rhs = "0xdd358416f52ecd34", + clmul_result = "0xa6299579b980928", swap_op = "0x1234567890123456", swapped = "0x5634129078563412", reversed = "0x6a2c48091e6a2c48", @@ -1290,6 +1423,7 @@ impl usize { bound_condition = " on 64-bit targets", } midpoint_impl! { usize, u128, unsigned } + carrying_carryless_mul_impl! { usize, u128 } } impl usize { diff --git a/core/src/num/niche_types.rs b/core/src/num/niche_types.rs index 9ac0eb72bdcbc..33b2a6741abdf 100644 --- a/core/src/num/niche_types.rs +++ b/core/src/num/niche_types.rs @@ -5,45 +5,33 @@ )] use crate::cmp::Ordering; -use crate::fmt; use crate::hash::{Hash, Hasher}; use crate::marker::StructuralPartialEq; +use crate::{fmt, pattern_type}; macro_rules! define_valid_range_type { ($( $(#[$m:meta])* - $vis:vis struct $name:ident($int:ident as $uint:ident in $low:literal..=$high:literal); + $vis:vis struct $name:ident($int:ident is $pat:pat); )+) => {$( - #[derive(Clone, Copy, Eq)] + #[derive(Clone, Copy)] #[repr(transparent)] - #[rustc_layout_scalar_valid_range_start($low)] - #[rustc_layout_scalar_valid_range_end($high)] $(#[$m])* - $vis struct $name($int); - - const _: () = { - // With the `valid_range` attributes, it's always specified as unsigned - assert!(<$uint>::MIN == 0); - let ulow: $uint = $low; - let uhigh: $uint = $high; - assert!(ulow <= uhigh); - - assert!(size_of::<$int>() == size_of::<$uint>()); - }; - + $vis struct $name(pattern_type!($int is $pat)); impl $name { #[inline] pub const fn new(val: $int) -> Option { - if (val as $uint) >= ($low as $uint) && (val as $uint) <= ($high as $uint) { - // SAFETY: just checked the inclusive range - Some(unsafe { $name(val) }) + #[allow(non_contiguous_range_endpoints)] + if let $pat = val { + // SAFETY: just checked that the value matches the pattern + Some(unsafe { $name(crate::mem::transmute(val)) }) } else { None } } /// Constructs an instance of this type from the underlying integer - /// primitive without checking whether its zero. + /// primitive without checking whether its valid. /// /// # Safety /// Immediate language UB if `val` is not within the valid range for this @@ -51,13 +39,13 @@ macro_rules! define_valid_range_type { #[inline] pub const unsafe fn new_unchecked(val: $int) -> Self { // SAFETY: Caller promised that `val` is within the valid range. - unsafe { $name(val) } + unsafe { crate::mem::transmute(val) } } #[inline] pub const fn as_inner(self) -> $int { - // SAFETY: This is a transparent wrapper, so unwrapping it is sound - // (Not using `.0` due to MCP#807.) + // SAFETY: pattern types are always legal values of their base type + // (Not using `.0` because that has perf regressions.) unsafe { crate::mem::transmute(self) } } } @@ -67,6 +55,8 @@ macro_rules! define_valid_range_type { // by . impl StructuralPartialEq for $name {} + impl Eq for $name {} + impl PartialEq for $name { #[inline] fn eq(&self, other: &Self) -> bool { @@ -104,7 +94,7 @@ macro_rules! define_valid_range_type { } define_valid_range_type! { - pub struct Nanoseconds(u32 as u32 in 0..=999_999_999); + pub struct Nanoseconds(u32 is 0..=999_999_999); } impl Nanoseconds { @@ -120,47 +110,32 @@ impl const Default for Nanoseconds { } } -define_valid_range_type! { - pub struct NonZeroU8Inner(u8 as u8 in 1..=0xff); - pub struct NonZeroU16Inner(u16 as u16 in 1..=0xff_ff); - pub struct NonZeroU32Inner(u32 as u32 in 1..=0xffff_ffff); - pub struct NonZeroU64Inner(u64 as u64 in 1..=0xffffffff_ffffffff); - pub struct NonZeroU128Inner(u128 as u128 in 1..=0xffffffffffffffff_ffffffffffffffff); - - pub struct NonZeroI8Inner(i8 as u8 in 1..=0xff); - pub struct NonZeroI16Inner(i16 as u16 in 1..=0xff_ff); - pub struct NonZeroI32Inner(i32 as u32 in 1..=0xffff_ffff); - pub struct NonZeroI64Inner(i64 as u64 in 1..=0xffffffff_ffffffff); - pub struct NonZeroI128Inner(i128 as u128 in 1..=0xffffffffffffffff_ffffffffffffffff); - - pub struct NonZeroCharInner(char as u32 in 1..=0x10ffff); -} +const HALF_USIZE: usize = usize::MAX >> 1; -#[cfg(target_pointer_width = "16")] -define_valid_range_type! { - pub struct UsizeNoHighBit(usize as usize in 0..=0x7fff); - pub struct NonZeroUsizeInner(usize as usize in 1..=0xffff); - pub struct NonZeroIsizeInner(isize as usize in 1..=0xffff); -} -#[cfg(target_pointer_width = "32")] define_valid_range_type! { - pub struct UsizeNoHighBit(usize as usize in 0..=0x7fff_ffff); - pub struct NonZeroUsizeInner(usize as usize in 1..=0xffff_ffff); - pub struct NonZeroIsizeInner(isize as usize in 1..=0xffff_ffff); -} -#[cfg(target_pointer_width = "64")] -define_valid_range_type! { - pub struct UsizeNoHighBit(usize as usize in 0..=0x7fff_ffff_ffff_ffff); - pub struct NonZeroUsizeInner(usize as usize in 1..=0xffff_ffff_ffff_ffff); - pub struct NonZeroIsizeInner(isize as usize in 1..=0xffff_ffff_ffff_ffff); -} + pub struct NonZeroU8Inner(u8 is 1..); + pub struct NonZeroU16Inner(u16 is 1..); + pub struct NonZeroU32Inner(u32 is 1..); + pub struct NonZeroU64Inner(u64 is 1..); + pub struct NonZeroU128Inner(u128 is 1..); -define_valid_range_type! { - pub struct U32NotAllOnes(u32 as u32 in 0..=0xffff_fffe); - pub struct I32NotAllOnes(i32 as u32 in 0..=0xffff_fffe); + pub struct NonZeroI8Inner(i8 is ..0 | 1..); + pub struct NonZeroI16Inner(i16 is ..0 | 1..); + pub struct NonZeroI32Inner(i32 is ..0 | 1..); + pub struct NonZeroI64Inner(i64 is ..0 | 1..); + pub struct NonZeroI128Inner(i128 is ..0 | 1..); + + pub struct UsizeNoHighBit(usize is 0..=HALF_USIZE); + pub struct NonZeroUsizeInner(usize is 1..); + pub struct NonZeroIsizeInner(isize is ..0 | 1..); + + pub struct U32NotAllOnes(u32 is 0..u32::MAX); + pub struct I32NotAllOnes(i32 is ..-1 | 0..); + + pub struct U64NotAllOnes(u64 is 0..u64::MAX); + pub struct I64NotAllOnes(i64 is ..-1 | 0..); - pub struct U64NotAllOnes(u64 as u64 in 0..=0xffff_ffff_ffff_fffe); - pub struct I64NotAllOnes(i64 as u64 in 0..=0xffff_ffff_ffff_fffe); + pub struct NonZeroCharInner(char is '\u{1}' ..= '\u{10ffff}'); } pub trait NotAllOnesHelper { @@ -181,7 +156,7 @@ impl NotAllOnesHelper for i64 { } define_valid_range_type! { - pub struct CodePointInner(u32 as u32 in 0..=0x10ffff); + pub struct CodePointInner(u32 is 0..=0x10ffff); } impl CodePointInner { diff --git a/core/src/num/nonzero.rs b/core/src/num/nonzero.rs index 2b5279efb7f79..f52438e4e62e0 100644 --- a/core/src/num/nonzero.rs +++ b/core/src/num/nonzero.rs @@ -31,7 +31,7 @@ use crate::{fmt, intrinsics, ptr, ub_checks}; issue = "none" )] pub unsafe trait ZeroablePrimitive: Sized + Copy + private::Sealed { - #[doc(hidden)] + /// A type like `Self` but with a niche that includes zero. type NonZeroInner: Sized + Copy; } @@ -1240,16 +1240,176 @@ macro_rules! nonzero_integer { // So the result cannot be zero. unsafe { Self::new_unchecked(self.get().saturating_pow(other)) } } + + /// Parses a non-zero integer from an ASCII-byte slice with decimal digits. + /// + /// The characters are expected to be an optional + #[doc = sign_dependent_expr!{ + $signedness ? + if signed { + " `+` or `-` " + } + if unsigned { + " `+` " + } + }] + /// sign followed by only digits. Leading and trailing non-digit characters (including + /// whitespace) represent an error. Underscores (which are accepted in Rust literals) + /// also represent an error. + /// + /// # Examples + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + /// # fn main() { test().unwrap(); } + /// # fn test() -> Option<()> { + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::from_ascii(b\"+10\"), Ok(NonZero::new(10)?));")] + /// # Some(()) + /// # } + /// ``` + /// + /// Trailing space returns error: + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + #[doc = concat!("assert!(NonZero::<", stringify!($Int), ">::from_ascii(b\"1 \").is_err());")] + /// ``` + #[unstable(feature = "int_from_ascii", issue = "134821")] + #[inline] + pub const fn from_ascii(src: &[u8]) -> Result { + Self::from_ascii_radix(src, 10) + } + + /// Parses a non-zero integer from an ASCII-byte slice with digits in a given base. + /// + /// The characters are expected to be an optional + #[doc = sign_dependent_expr!{ + $signedness ? + if signed { + " `+` or `-` " + } + if unsigned { + " `+` " + } + }] + /// sign followed by only digits. Leading and trailing non-digit characters (including + /// whitespace) represent an error. Underscores (which are accepted in Rust literals) + /// also represent an error. + /// + /// Digits are a subset of these characters, depending on `radix`: + /// + /// - `0-9` + /// - `a-z` + /// - `A-Z` + /// + /// # Panics + /// + /// This method panics if `radix` is not in the range from 2 to 36. + /// + /// # Examples + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + /// # fn main() { test().unwrap(); } + /// # fn test() -> Option<()> { + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::from_ascii_radix(b\"A\", 16), Ok(NonZero::new(10)?));")] + /// # Some(()) + /// # } + /// ``` + /// + /// Trailing space returns error: + /// + /// ``` + /// #![feature(int_from_ascii)] + /// + /// # use std::num::NonZero; + /// # + #[doc = concat!("assert!(NonZero::<", stringify!($Int), ">::from_ascii_radix(b\"1 \", 10).is_err());")] + /// ``` + #[unstable(feature = "int_from_ascii", issue = "134821")] + #[inline] + pub const fn from_ascii_radix(src: &[u8], radix: u32) -> Result { + let n = match <$Int>::from_ascii_radix(src, radix) { + Ok(n) => n, + Err(err) => return Err(err), + }; + if let Some(n) = Self::new(n) { + Ok(n) + } else { + Err(ParseIntError { kind: IntErrorKind::Zero }) + } + } + + /// Parses a non-zero integer from a string slice with digits in a given base. + /// + /// The string is expected to be an optional + #[doc = sign_dependent_expr!{ + $signedness ? + if signed { + " `+` or `-` " + } + if unsigned { + " `+` " + } + }] + /// sign followed by only digits. Leading and trailing non-digit characters (including + /// whitespace) represent an error. Underscores (which are accepted in Rust literals) + /// also represent an error. + /// + /// Digits are a subset of these characters, depending on `radix`: + /// + /// - `0-9` + /// - `a-z` + /// - `A-Z` + /// + /// # Panics + /// + /// This method panics if `radix` is not in the range from 2 to 36. + /// + /// # Examples + /// + /// ``` + /// #![feature(nonzero_from_str_radix)] + /// + /// # use std::num::NonZero; + /// # + /// # fn main() { test().unwrap(); } + /// # fn test() -> Option<()> { + #[doc = concat!("assert_eq!(NonZero::<", stringify!($Int), ">::from_str_radix(\"A\", 16), Ok(NonZero::new(10)?));")] + /// # Some(()) + /// # } + /// ``` + /// + /// Trailing space returns error: + /// + /// ``` + /// #![feature(nonzero_from_str_radix)] + /// + /// # use std::num::NonZero; + /// # + #[doc = concat!("assert!(NonZero::<", stringify!($Int), ">::from_str_radix(\"1 \", 10).is_err());")] + /// ``` + #[unstable(feature = "nonzero_from_str_radix", issue = "152193")] + #[inline] + pub const fn from_str_radix(src: &str, radix: u32) -> Result { + Self::from_ascii_radix(src.as_bytes(), radix) + } } #[stable(feature = "nonzero_parse", since = "1.35.0")] impl FromStr for NonZero<$Int> { type Err = ParseIntError; fn from_str(src: &str) -> Result { - Self::new(<$Int>::from_str_radix(src, 10)?) - .ok_or(ParseIntError { - kind: IntErrorKind::Zero - }) + Self::from_str_radix(src, 10) } } diff --git a/core/src/num/uint_macros.rs b/core/src/num/uint_macros.rs index 5c263ea845cc2..33cf7af28df57 100644 --- a/core/src/num/uint_macros.rs +++ b/core/src/num/uint_macros.rs @@ -17,6 +17,9 @@ macro_rules! uint_impl { fsh_op = $fsh_op:literal, fshl_result = $fshl_result:literal, fshr_result = $fshr_result:literal, + clmul_lhs = $clmul_lhs:literal, + clmul_rhs = $clmul_rhs:literal, + clmul_result = $clmul_result:literal, swap_op = $swap_op:literal, swapped = $swapped:literal, reversed = $reversed:literal, @@ -482,6 +485,62 @@ macro_rules! uint_impl { unsafe { intrinsics::unchecked_funnel_shr(self, rhs, n) } } + /// Performs a carry-less multiplication, returning the lower bits. + /// + /// This operation is similar to long multiplication in base 2, except that exclusive or is + /// used instead of addition. The implementation is equivalent to: + /// + /// ```no_run + #[doc = concat!("pub fn carryless_mul(lhs: ", stringify!($SelfT), ", rhs: ", stringify!($SelfT), ") -> ", stringify!($SelfT), "{")] + /// let mut retval = 0; + #[doc = concat!(" for i in 0..", stringify!($SelfT), "::BITS {")] + /// if (rhs >> i) & 1 != 0 { + /// // long multiplication would use += + /// retval ^= lhs << i; + /// } + /// } + /// retval + /// } + /// ``` + /// + /// The actual implementation is more efficient, and on some platforms lowers directly to a + /// dedicated instruction. + /// + /// # Uses + /// + /// Carryless multiplication can be used to turn a bitmask of quote characters into a + /// bit mask of characters surrounded by quotes: + /// + /// ```no_run + /// r#"abc xxx "foobar" zzz "a"!"#; // input string + /// 0b0000000010000001000001010; // quote_mask + /// 0b0000000001111110000000100; // quote_mask.carryless_mul(!0) & !quote_mask + /// ``` + /// + /// Another use is in cryptography, where carryless multiplication allows for efficient + /// implementations of polynomial multiplication in `GF(2)[X]`, the polynomial ring + /// over `GF(2)`. + /// + /// # Examples + /// + /// ``` + /// #![feature(uint_carryless_mul)] + /// + #[doc = concat!("let a = ", $clmul_lhs, stringify!($SelfT), ";")] + #[doc = concat!("let b = ", $clmul_rhs, stringify!($SelfT), ";")] + /// + #[doc = concat!("assert_eq!(a.carryless_mul(b), ", $clmul_result, ");")] + /// ``` + #[rustc_const_unstable(feature = "uint_carryless_mul", issue = "152080")] + #[doc(alias = "clmul")] + #[unstable(feature = "uint_carryless_mul", issue = "152080")] + #[must_use = "this returns the result of the operation, \ + without modifying the original"] + #[inline(always)] + pub const fn carryless_mul(self, rhs: Self) -> Self { + intrinsics::carryless_mul(self, rhs) + } + /// Reverses the byte order of the integer. /// /// # Examples @@ -3072,7 +3131,6 @@ macro_rules! uint_impl { /// implementing it for wider-than-native types. /// /// ``` - /// #![feature(const_unsigned_bigint_helpers)] /// fn scalar_mul_eq(little_endian_digits: &mut Vec, multiplicand: u16) { /// let mut carry = 0; /// for d in little_endian_digits.iter_mut() { @@ -3097,6 +3155,7 @@ macro_rules! uint_impl { /// except that it gives the value of the overflow instead of just whether one happened: /// /// ``` + /// # #![allow(unused_features)] /// #![feature(const_unsigned_bigint_helpers)] /// let r = u8::carrying_mul(7, 13, 0); /// assert_eq!((r.0, r.1 != 0), u8::overflowing_mul(7, 13)); @@ -3109,6 +3168,7 @@ macro_rules! uint_impl { /// [`wrapping_add`](Self::wrapping_add) methods: /// /// ``` + /// # #![allow(unused_features)] /// #![feature(const_unsigned_bigint_helpers)] /// assert_eq!( /// 789_u16.carrying_mul(456, 123).0, diff --git a/core/src/ops/control_flow.rs b/core/src/ops/control_flow.rs index 3cc184f0ab75c..1b1444042335f 100644 --- a/core/src/ops/control_flow.rs +++ b/core/src/ops/control_flow.rs @@ -151,7 +151,7 @@ impl ControlFlow { /// ``` #[inline] #[stable(feature = "control_flow_enum_is", since = "1.59.0")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[rustc_const_stable(feature = "min_const_control_flow", since = "CURRENT_RUSTC_VERSION")] pub const fn is_break(&self) -> bool { matches!(*self, ControlFlow::Break(_)) } @@ -168,7 +168,7 @@ impl ControlFlow { /// ``` #[inline] #[stable(feature = "control_flow_enum_is", since = "1.59.0")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[rustc_const_stable(feature = "min_const_control_flow", since = "CURRENT_RUSTC_VERSION")] pub const fn is_continue(&self) -> bool { matches!(*self, ControlFlow::Continue(_)) } @@ -197,7 +197,7 @@ impl ControlFlow { } } - /// Converts the `ControlFlow` into an `Result` which is `Ok` if the + /// Converts the `ControlFlow` into a `Result` which is `Ok` if the /// `ControlFlow` was `Break` and `Err` if otherwise. /// /// # Examples @@ -264,7 +264,7 @@ impl ControlFlow { /// ``` #[inline] #[unstable(feature = "control_flow_ok", issue = "140266")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[rustc_const_unstable(feature = "control_flow_ok", issue = "140266")] pub const fn break_ok(self) -> Result { match self { ControlFlow::Continue(c) => Err(c), @@ -311,7 +311,7 @@ impl ControlFlow { } } - /// Converts the `ControlFlow` into an `Result` which is `Ok` if the + /// Converts the `ControlFlow` into a `Result` which is `Ok` if the /// `ControlFlow` was `Continue` and `Err` if otherwise. /// /// # Examples @@ -377,7 +377,7 @@ impl ControlFlow { /// ``` #[inline] #[unstable(feature = "control_flow_ok", issue = "140266")] - #[rustc_const_unstable(feature = "min_const_control_flow", issue = "148738")] + #[rustc_const_unstable(feature = "control_flow_ok", issue = "140266")] pub const fn continue_ok(self) -> Result { match self { ControlFlow::Continue(c) => Ok(c), @@ -422,9 +422,9 @@ impl ControlFlow { } } -/// These are used only as part of implementing the iterator adapters. -/// They have mediocre names and non-obvious semantics, so aren't -/// currently on a path to potential stabilization. +// These are used only as part of implementing the iterator adapters. +// They have mediocre names and non-obvious semantics, so aren't +// currently on a path to potential stabilization. impl ControlFlow { /// Creates a `ControlFlow` from any type implementing `Try`. #[inline] diff --git a/core/src/prelude/v1.rs b/core/src/prelude/v1.rs index 354be271ff131..17928b1e9cb31 100644 --- a/core/src/prelude/v1.rs +++ b/core/src/prelude/v1.rs @@ -80,7 +80,7 @@ mod ambiguous_macros_only { #[doc(no_inline)] pub use self::ambiguous_macros_only::{env, panic}; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "CURRENT_RUSTC_VERSION")] #[doc(no_inline)] pub use crate::cfg_select; diff --git a/core/src/ptr/alignment.rs b/core/src/ptr/alignment.rs index 7c34b026e14be..b106314f14d12 100644 --- a/core/src/ptr/alignment.rs +++ b/core/src/ptr/alignment.rs @@ -52,8 +52,7 @@ impl Alignment { #[inline] #[must_use] pub const fn of() -> Self { - // This can't actually panic since type alignment is always a power of two. - const { Alignment::new(align_of::()).unwrap() } + ::ALIGNMENT } /// Returns the [ABI]-required minimum alignment of the type of the value that `val` points to. @@ -113,7 +112,6 @@ impl Alignment { /// /// ``` /// #![feature(ptr_alignment_type)] - /// #![feature(layout_for_ptr)] /// use std::ptr::Alignment; /// /// assert_eq!(unsafe { Alignment::of_val_raw(&5i32) }.as_usize(), 4); diff --git a/core/src/ptr/mod.rs b/core/src/ptr/mod.rs index ad74a8628c61c..48e1e206a313e 100644 --- a/core/src/ptr/mod.rs +++ b/core/src/ptr/mod.rs @@ -15,22 +15,19 @@ //! The precise rules for validity are not determined yet. The guarantees that are //! provided at this point are very minimal: //! -//! * For memory accesses of [size zero][zst], *every* pointer is valid, including the [null] -//! pointer. The following points are only concerned with non-zero-sized accesses. -//! * A [null] pointer is *never* valid. -//! * For a pointer to be valid, it is necessary, but not always sufficient, that the pointer be -//! *dereferenceable*. The [provenance] of the pointer is used to determine which [allocation] -//! it is derived from; a pointer is dereferenceable if the memory range of the given size -//! starting at the pointer is entirely contained within the bounds of that allocation. Note +//! * A [null] pointer is *never* valid for reads/writes. +//! * For memory accesses of [size zero][zst], *every* non-null pointer is valid for reads/writes. +//! The following points are only concerned with non-zero-sized accesses. +//! * For a pointer to be valid for reads/writes, it is necessary, but not always sufficient, that +//! the pointer be *dereferenceable*. The [provenance] of the pointer is used to determine which +//! [allocation] it is derived from; a pointer is dereferenceable if the memory range of the given +//! size starting at the pointer is entirely contained within the bounds of that allocation. Note //! that in Rust, every (stack-allocated) variable is considered a separate allocation. //! * All accesses performed by functions in this module are *non-atomic* in the sense //! of [atomic operations] used to synchronize between threads. This means it is //! undefined behavior to perform two concurrent accesses to the same location from different -//! threads unless both accesses only read from memory. Notice that this explicitly -//! includes [`read_volatile`] and [`write_volatile`]: Volatile accesses cannot -//! be used for inter-thread synchronization, regardless of whether they are acting on -//! Rust memory or not. -//! * The result of casting a reference to a pointer is valid for as long as the +//! threads unless both accesses only read from memory. +//! * The result of casting a reference to a pointer is valid for reads/writes for as long as the //! underlying allocation is live and no reference (just raw pointers) is used to //! access the same memory. That is, reference and pointer accesses cannot be //! interleaved. @@ -41,6 +38,13 @@ //! information, see the [book] as well as the section in the reference devoted //! to [undefined behavior][ub]. //! +//! Note that some operations such as [`read`] and [`write`][`write()`] do allow null pointers if +//! the total size of the access is zero. However, other operations internally convert pointers into +//! references. Therefore, the general notion of "valid for reads/writes" excludes null pointers, +//! and the specific operations that permit null pointers mention that as an exception. Furthermore, +//! [`read_volatile`] and [`write_volatile`] can be used in even more situations; see their +//! documentation for details. +//! //! We say that a pointer is "dangling" if it is not valid for any non-zero-sized accesses. This //! means out-of-bounds pointers, pointers to freed memory, null pointers, and pointers created with //! [`NonNull::dangling`] are all dangling. @@ -450,9 +454,9 @@ mod mut_ptr; /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be [valid] for reads of `count * size_of::()` bytes. +/// * `src` must be [valid] for reads of `count * size_of::()` bytes or that number must be 0. /// -/// * `dst` must be [valid] for writes of `count * size_of::()` bytes. +/// * `dst` must be [valid] for writes of `count * size_of::()` bytes or that number must be 0. /// /// * Both `src` and `dst` must be properly aligned. /// @@ -568,11 +572,11 @@ pub const unsafe fn copy_nonoverlapping(src: *const T, dst: *mut T, count: us /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be [valid] for reads of `count * size_of::()` bytes. +/// * `src` must be [valid] for reads of `count * size_of::()` bytes or that number must be 0. /// -/// * `dst` must be [valid] for writes of `count * size_of::()` bytes, and must remain valid even -/// when `src` is read for `count * size_of::()` bytes. (This means if the memory ranges -/// overlap, the `dst` pointer must not be invalidated by `src` reads.) +/// * `dst` must be [valid] for writes of `count * size_of::()` bytes or that number must be 0, +/// and `dst` must remain valid even when `src` is read for `count * size_of::()` bytes. (This +/// means if the memory ranges overlap, the `dst` pointer must not be invalidated by `src` reads.) /// /// * Both `src` and `dst` must be properly aligned. /// @@ -1508,7 +1512,7 @@ unsafe fn swap_nonoverlapping_bytes(x: *mut u8, y: *mut u8, bytes: NonZero(dst: *mut T, src: T) -> T { // SAFETY: the caller must guarantee that `dst` is valid to be // cast to a mutable reference (valid for writes, aligned, initialized), // and cannot overlap `src` since `dst` must point to a distinct - // allocation. + // allocation. We are excluding null (with a ZST check) before creating a reference. unsafe { ub_checks::assert_unsafe_precondition!( check_language_ub, @@ -1554,6 +1558,12 @@ pub const unsafe fn replace(dst: *mut T, src: T) -> T { is_zst: bool = T::IS_ZST, ) => ub_checks::maybe_is_aligned_and_not_null(addr, align, is_zst) ); + if T::IS_ZST { + // If `T` is a ZST, `dst` is allowed to be null. However, we also don't have to actually + // do anything since there isn't actually any data to be copied anyway. All values of + // type `T` are bit-identical, so we can just return `src` here. + return src; + } mem::replace(&mut *dst, src) } } @@ -1565,7 +1575,7 @@ pub const unsafe fn replace(dst: *mut T, src: T) -> T { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be [valid] for reads. +/// * `src` must be [valid] for reads or `T` must be a ZST. /// /// * `src` must be properly aligned. Use [`read_unaligned`] if this is not the /// case. @@ -1817,7 +1827,7 @@ pub const unsafe fn read_unaligned(src: *const T) -> T { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `dst` must be [valid] for writes. +/// * `dst` must be [valid] for writes or `T` must be a ZST. /// /// * `dst` must be properly aligned. Use [`write_unaligned`] if this is not the /// case. @@ -2040,8 +2050,8 @@ pub const unsafe fn write_unaligned(dst: *mut T, src: T) { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `src` must be either [valid] for reads, or it must point to memory outside of all Rust -/// allocations and reading from that memory must: +/// * `src` must be either [valid] for reads, or `T` must be a ZST, or `src` must point to memory +/// outside of all Rust allocations and reading from that memory must: /// - not trap, and /// - not cause any memory inside a Rust allocation to be modified. /// @@ -2128,8 +2138,8 @@ pub unsafe fn read_volatile(src: *const T) -> T { /// /// Behavior is undefined if any of the following conditions are violated: /// -/// * `dst` must be either [valid] for writes, or it must point to memory outside of all Rust -/// allocations and writing to that memory must: +/// * `dst` must be either [valid] for writes, or `T` must be a ZST, or `dst` must point to memory +/// outside of all Rust allocations and writing to that memory must: /// - not trap, and /// - not cause any memory inside a Rust allocation to be modified. /// diff --git a/core/src/ptr/mut_ptr.rs b/core/src/ptr/mut_ptr.rs index 02e12d56fa659..f19a5d02b98df 100644 --- a/core/src/ptr/mut_ptr.rs +++ b/core/src/ptr/mut_ptr.rs @@ -1800,7 +1800,6 @@ impl *mut [T] { /// /// ``` /// #![feature(raw_slice_split)] - /// #![feature(slice_ptr_get)] /// /// let mut v = [1, 0, 3, 0, 5, 6]; /// let ptr = &mut v as *mut [_]; diff --git a/core/src/ptr/non_null.rs b/core/src/ptr/non_null.rs index 7b9e638289bf0..8be7d3a9ae925 100644 --- a/core/src/ptr/non_null.rs +++ b/core/src/ptr/non_null.rs @@ -1,7 +1,7 @@ use crate::clone::TrivialClone; use crate::cmp::Ordering; use crate::marker::{Destruct, PointeeSized, Unsize}; -use crate::mem::{MaybeUninit, SizedTypeProperties}; +use crate::mem::{MaybeUninit, SizedTypeProperties, transmute}; use crate::num::NonZero; use crate::ops::{CoerceUnsized, DispatchFromDyn}; use crate::pin::PinCoerceUnsized; @@ -100,9 +100,8 @@ impl NonNull { #[must_use] #[inline] pub const fn without_provenance(addr: NonZero) -> Self { - let pointer = crate::ptr::without_provenance(addr.get()); - // SAFETY: we know `addr` is non-zero. - unsafe { NonNull { pointer } } + // SAFETY: we know `addr` is non-zero and all nonzero integers are valid raw pointers. + unsafe { transmute(addr) } } /// Creates a new `NonNull` that is dangling, but well-aligned. @@ -239,7 +238,7 @@ impl NonNull { "NonNull::new_unchecked requires that the pointer is non-null", (ptr: *mut () = ptr as *mut ()) => !ptr.is_null() ); - NonNull { pointer: ptr as _ } + transmute(ptr) } } @@ -282,7 +281,7 @@ impl NonNull { #[inline] pub const fn from_ref(r: &T) -> Self { // SAFETY: A reference cannot be null. - unsafe { NonNull { pointer: r as *const T } } + unsafe { transmute(r as *const T) } } /// Converts a mutable reference to a `NonNull` pointer. @@ -291,7 +290,7 @@ impl NonNull { #[inline] pub const fn from_mut(r: &mut T) -> Self { // SAFETY: A mutable reference cannot be null. - unsafe { NonNull { pointer: r as *mut T } } + unsafe { transmute(r as *mut T) } } /// Performs the same functionality as [`std::ptr::from_raw_parts`], except that a @@ -502,7 +501,7 @@ impl NonNull { #[inline] pub const fn cast(self) -> NonNull { // SAFETY: `self` is a `NonNull` pointer which is necessarily non-null - unsafe { NonNull { pointer: self.as_ptr() as *mut U } } + unsafe { transmute(self.as_ptr() as *mut U) } } /// Try to cast to a pointer of another type by checking alignment. @@ -581,7 +580,7 @@ impl NonNull { // Additionally safety contract of `offset` guarantees that the resulting pointer is // pointing to an allocation, there can't be an allocation at null, thus it's safe to // construct `NonNull`. - unsafe { NonNull { pointer: intrinsics::offset(self.as_ptr(), count) } } + unsafe { transmute(intrinsics::offset(self.as_ptr(), count)) } } /// Calculates the offset from a pointer in bytes. @@ -605,7 +604,7 @@ impl NonNull { // Additionally safety contract of `offset` guarantees that the resulting pointer is // pointing to an allocation, there can't be an allocation at null, thus it's safe to // construct `NonNull`. - unsafe { NonNull { pointer: self.as_ptr().byte_offset(count) } } + unsafe { transmute(self.as_ptr().byte_offset(count)) } } /// Adds an offset to a pointer (convenience for `.offset(count as isize)`). @@ -657,7 +656,7 @@ impl NonNull { // Additionally safety contract of `offset` guarantees that the resulting pointer is // pointing to an allocation, there can't be an allocation at null, thus it's safe to // construct `NonNull`. - unsafe { NonNull { pointer: intrinsics::offset(self.as_ptr(), count) } } + unsafe { transmute(intrinsics::offset(self.as_ptr(), count)) } } /// Calculates the offset from a pointer in bytes (convenience for `.byte_offset(count as isize)`). @@ -681,7 +680,7 @@ impl NonNull { // Additionally safety contract of `add` guarantees that the resulting pointer is pointing // to an allocation, there can't be an allocation at null, thus it's safe to construct // `NonNull`. - unsafe { NonNull { pointer: self.as_ptr().byte_add(count) } } + unsafe { transmute(self.as_ptr().byte_add(count)) } } /// Subtracts an offset from a pointer (convenience for @@ -763,7 +762,7 @@ impl NonNull { // Additionally safety contract of `sub` guarantees that the resulting pointer is pointing // to an allocation, there can't be an allocation at null, thus it's safe to construct // `NonNull`. - unsafe { NonNull { pointer: self.as_ptr().byte_sub(count) } } + unsafe { transmute(self.as_ptr().byte_sub(count)) } } /// Calculates the distance between two pointers within the same allocation. The returned value is in diff --git a/core/src/random.rs b/core/src/random.rs index 8a51fb289d8f3..06f4f30efe2b5 100644 --- a/core/src/random.rs +++ b/core/src/random.rs @@ -1,6 +1,6 @@ //! Random value generation. -use crate::range::RangeFull; +use crate::ops::RangeFull; /// A source of randomness. #[unstable(feature = "random", issue = "130703")] diff --git a/core/src/range.rs b/core/src/range.rs index 4b87d426bda76..0ef0d192a8682 100644 --- a/core/src/range.rs +++ b/core/src/range.rs @@ -24,14 +24,26 @@ mod iter; #[unstable(feature = "new_range_api", issue = "125687")] pub mod legacy; -use Bound::{Excluded, Included, Unbounded}; #[doc(inline)] -pub use iter::{RangeFromIter, RangeInclusiveIter, RangeIter}; - -#[doc(inline)] -pub use crate::iter::Step; +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +pub use iter::RangeInclusiveIter; #[doc(inline)] -pub use crate::ops::{Bound, IntoBounds, OneSidedRange, RangeBounds, RangeFull, RangeTo}; +#[unstable(feature = "new_range_api", issue = "125687")] +pub use iter::{RangeFromIter, RangeIter}; + +// FIXME(#125687): re-exports temporarily removed +// Because re-exports of stable items (Bound, RangeBounds, RangeFull, RangeTo) +// can't be made unstable. +// +// #[doc(inline)] +// #[unstable(feature = "new_range_api", issue = "125687")] +// pub use crate::iter::Step; +// #[doc(inline)] +// #[unstable(feature = "new_range_api", issue = "125687")] +// pub use crate::ops::{Bound, IntoBounds, OneSidedRange, RangeBounds, RangeFull, RangeTo}; +use crate::iter::Step; +use crate::ops::Bound::{self, Excluded, Included, Unbounded}; +use crate::ops::{IntoBounds, RangeBounds}; /// A (half-open) range bounded inclusively below and exclusively above /// (`start..end` in a future edition). @@ -226,7 +238,6 @@ impl const From> for Range { /// The `start..=last` syntax is a `RangeInclusive`: /// /// ``` -/// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert_eq!(RangeInclusive::from(3..=5), RangeInclusive { start: 3, last: 5 }); @@ -234,17 +245,17 @@ impl const From> for Range { /// ``` #[lang = "RangeInclusiveCopy"] #[derive(Clone, Copy, PartialEq, Eq, Hash)] -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] pub struct RangeInclusive { /// The lower bound of the range (inclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] pub start: Idx, /// The upper bound of the range (inclusive). - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] pub last: Idx, } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl fmt::Debug for RangeInclusive { fn fmt(&self, fmt: &mut fmt::Formatter<'_>) -> fmt::Result { self.start.fmt(fmt)?; @@ -260,7 +271,6 @@ impl> RangeInclusive { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert!(!RangeInclusive::from(3..=5).contains(&2)); @@ -278,7 +288,7 @@ impl> RangeInclusive { /// assert!(!RangeInclusive::from(f32::NAN..=1.0).contains(&1.0)); /// ``` #[inline] - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn contains(&self, item: &U) -> bool where @@ -293,7 +303,6 @@ impl> RangeInclusive { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert!(!RangeInclusive::from(3..=5).is_empty()); @@ -304,14 +313,13 @@ impl> RangeInclusive { /// The range is empty if either side is incomparable: /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// assert!(!RangeInclusive::from(3.0..=5.0).is_empty()); /// assert!( RangeInclusive::from(3.0..=f32::NAN).is_empty()); /// assert!( RangeInclusive::from(f32::NAN..=5.0).is_empty()); /// ``` - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[inline] #[rustc_const_unstable(feature = "const_range", issue = "none")] pub const fn is_empty(&self) -> bool @@ -330,7 +338,6 @@ impl RangeInclusive { /// # Examples /// /// ``` - /// #![feature(new_range_api)] /// use core::range::RangeInclusive; /// /// let mut i = RangeInclusive::from(3..=8).iter().map(|n| n*n); @@ -338,23 +345,14 @@ impl RangeInclusive { /// assert_eq!(i.next(), Some(16)); /// assert_eq!(i.next(), Some(25)); /// ``` - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[inline] pub fn iter(&self) -> RangeInclusiveIter { self.clone().into_iter() } } -impl RangeInclusive { - /// Converts to an exclusive `Range` for `SliceIndex` implementations. - /// The caller is responsible for dealing with `last == usize::MAX`. - #[inline] - pub(crate) const fn into_slice_range(self) -> Range { - Range { start: self.start, end: self.last + 1 } - } -} - -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeInclusive { fn start_bound(&self) -> Bound<&T> { @@ -371,7 +369,7 @@ impl const RangeBounds for RangeInclusive { /// If you need to use this implementation where `T` is unsized, /// consider using the `RangeBounds` impl for a 2-tuple of [`Bound<&T>`][Bound], /// i.e. replace `start..=end` with `(Bound::Included(start), Bound::Included(end))`. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const RangeBounds for RangeInclusive<&T> { fn start_bound(&self) -> Bound<&T> { @@ -382,8 +380,8 @@ impl const RangeBounds for RangeInclusive<&T> { } } -// #[unstable(feature = "range_into_bounds", issue = "136903")] -#[unstable(feature = "new_range_api", issue = "125687")] +// #[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] +#[unstable(feature = "range_into_bounds", issue = "136903")] #[rustc_const_unstable(feature = "const_range", issue = "none")] impl const IntoBounds for RangeInclusive { fn into_bounds(self) -> (Bound, Bound) { @@ -391,7 +389,7 @@ impl const IntoBounds for RangeInclusive { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const From> for legacy::RangeInclusive { #[inline] @@ -399,7 +397,7 @@ impl const From> for legacy::RangeInclusive { Self::new(value.start, value.last) } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_convert", issue = "143773")] impl const From> for RangeInclusive { #[inline] @@ -650,12 +648,13 @@ impl> RangeToInclusive { } } +#[unstable(feature = "new_range_api", issue = "125687")] impl From> for RangeToInclusive { fn from(value: legacy::RangeToInclusive) -> Self { Self { last: value.end } } } - +#[unstable(feature = "new_range_api", issue = "125687")] impl From> for legacy::RangeToInclusive { fn from(value: RangeToInclusive) -> Self { Self { end: value.last } diff --git a/core/src/range/iter.rs b/core/src/range/iter.rs index 6fe5d9b34361a..e722b9fa33c57 100644 --- a/core/src/range/iter.rs +++ b/core/src/range/iter.rs @@ -11,6 +11,7 @@ use crate::{intrinsics, mem}; pub struct RangeIter(legacy::Range); impl RangeIter { + #[unstable(feature = "new_range_api", issue = "125687")] /// Returns the remainder of the range being iterated over. pub fn remainder(self) -> Range { Range { start: self.0.start, end: self.0.end } @@ -152,7 +153,7 @@ impl IntoIterator for Range { } /// By-value [`RangeInclusive`] iterator. -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[derive(Debug, Clone)] pub struct RangeInclusiveIter(legacy::RangeInclusive); @@ -160,6 +161,7 @@ impl RangeInclusiveIter { /// Returns the remainder of the range being iterated over. /// /// If the iterator is exhausted or empty, returns `None`. + #[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] pub fn remainder(self) -> Option> { if self.0.is_empty() { return None; @@ -169,7 +171,7 @@ impl RangeInclusiveIter { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl Iterator for RangeInclusiveIter { type Item = A; @@ -225,7 +227,7 @@ impl Iterator for RangeInclusiveIter { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl DoubleEndedIterator for RangeInclusiveIter { #[inline] fn next_back(&mut self) -> Option { @@ -246,10 +248,10 @@ impl DoubleEndedIterator for RangeInclusiveIter { #[unstable(feature = "trusted_len", issue = "37572")] unsafe impl TrustedLen for RangeInclusiveIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl FusedIterator for RangeInclusiveIter {} -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl IntoIterator for RangeInclusive { type Item = A; type IntoIter = RangeInclusiveIter; @@ -276,7 +278,7 @@ macro_rules! range_exact_iter_impl { macro_rules! range_incl_exact_iter_impl { ($($t:ty)*) => ($( - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl ExactSizeIterator for RangeInclusiveIter<$t> { } )*) } @@ -305,6 +307,7 @@ impl RangeFromIter { /// Returns the remainder of the range being iterated over. #[inline] #[rustc_inherit_overflow_checks] + #[unstable(feature = "new_range_api", issue = "125687")] pub fn remainder(self) -> RangeFrom { if intrinsics::overflow_checks() { if !self.first { diff --git a/core/src/slice/index.rs b/core/src/slice/index.rs index 59802989c18fb..3a76c098bb530 100644 --- a/core/src/slice/index.rs +++ b/core/src/slice/index.rs @@ -127,7 +127,7 @@ mod private_slice_index { #[unstable(feature = "new_range_api", issue = "125687")] impl Sealed for range::Range {} - #[unstable(feature = "new_range_api", issue = "125687")] + #[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] impl Sealed for range::RangeInclusive {} #[unstable(feature = "new_range_api", issue = "125687")] impl Sealed for range::RangeToInclusive {} @@ -663,7 +663,6 @@ unsafe impl const SliceIndex<[T]> for ops::RangeFull { } /// The methods `index` and `index_mut` panic if: -/// - the end of the range is `usize::MAX` or /// - the start of the range is greater than the end of the range or /// - the end of the range is out of bounds. #[stable(feature = "inclusive_range", since = "1.26.0")] @@ -673,12 +672,12 @@ unsafe impl const SliceIndex<[T]> for ops::RangeInclusive { #[inline] fn get(self, slice: &[T]) -> Option<&[T]> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get(slice) } } #[inline] fn get_mut(self, slice: &mut [T]) -> Option<&mut [T]> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get_mut(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get_mut(slice) } } #[inline] @@ -724,7 +723,7 @@ unsafe impl const SliceIndex<[T]> for ops::RangeInclusive { } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex<[T]> for range::RangeInclusive { type Output = [T]; @@ -950,8 +949,7 @@ where R: ops::RangeBounds, { let len = bounds.end; - let r = into_range(len, (range.start_bound().copied(), range.end_bound().copied()))?; - if r.start > r.end || r.end > len { None } else { Some(r) } + try_into_slice_range(len, (range.start_bound().copied(), range.end_bound().copied())) } /// Converts a pair of `ops::Bound`s into `ops::Range` without performing any @@ -978,25 +976,31 @@ pub(crate) const fn into_range_unchecked( /// Returns `None` on overflowing indices. #[rustc_const_unstable(feature = "const_range", issue = "none")] #[inline] -pub(crate) const fn into_range( +pub(crate) const fn try_into_slice_range( len: usize, (start, end): (ops::Bound, ops::Bound), ) -> Option> { - use ops::Bound; - let start = match start { - Bound::Included(start) => start, - Bound::Excluded(start) => start.checked_add(1)?, - Bound::Unbounded => 0, - }; - let end = match end { - Bound::Included(end) => end.checked_add(1)?, - Bound::Excluded(end) => end, - Bound::Unbounded => len, + ops::Bound::Included(end) if end >= len => return None, + // Cannot overflow because `end < len` implies `end < usize::MAX`. + ops::Bound::Included(end) => end + 1, + + ops::Bound::Excluded(end) if end > len => return None, + ops::Bound::Excluded(end) => end, + + ops::Bound::Unbounded => len, }; - // Don't bother with checking `start < end` and `end <= len` - // since these checks are handled by `Range` impls + let start = match start { + ops::Bound::Excluded(start) if start >= end => return None, + // Cannot overflow because `start < end` implies `start < usize::MAX`. + ops::Bound::Excluded(start) => start + 1, + + ops::Bound::Included(start) if start > end => return None, + ops::Bound::Included(start) => start, + + ops::Bound::Unbounded => 0, + }; Some(start..end) } @@ -1039,12 +1043,12 @@ unsafe impl SliceIndex<[T]> for (ops::Bound, ops::Bound) { #[inline] fn get(self, slice: &[T]) -> Option<&Self::Output> { - into_range(slice.len(), self)?.get(slice) + try_into_slice_range(slice.len(), self)?.get(slice) } #[inline] fn get_mut(self, slice: &mut [T]) -> Option<&mut Self::Output> { - into_range(slice.len(), self)?.get_mut(slice) + try_into_slice_range(slice.len(), self)?.get_mut(slice) } #[inline] diff --git a/core/src/slice/iter.rs b/core/src/slice/iter.rs index a289b0d6df401..ac096afb38af0 100644 --- a/core/src/slice/iter.rs +++ b/core/src/slice/iter.rs @@ -2175,7 +2175,7 @@ unsafe impl Sync for ChunksExactMut<'_, T> where T: Sync {} /// /// [`array_windows`]: slice::array_windows /// [slices]: slice -#[derive(Debug, Clone, Copy)] +#[derive(Debug)] #[stable(feature = "array_windows", since = "1.94.0")] #[must_use = "iterators are lazy and do nothing unless consumed"] pub struct ArrayWindows<'a, T: 'a, const N: usize> { @@ -2189,6 +2189,14 @@ impl<'a, T: 'a, const N: usize> ArrayWindows<'a, T, N> { } } +// FIXME(#26925) Remove in favor of `#[derive(Clone)]` +#[stable(feature = "array_windows", since = "1.94.0")] +impl Clone for ArrayWindows<'_, T, N> { + fn clone(&self) -> Self { + Self { v: self.v } + } +} + #[stable(feature = "array_windows", since = "1.94.0")] impl<'a, T, const N: usize> Iterator for ArrayWindows<'a, T, N> { type Item = &'a [T; N]; @@ -2224,6 +2232,14 @@ impl<'a, T, const N: usize> Iterator for ArrayWindows<'a, T, N> { fn last(self) -> Option { self.v.last_chunk() } + + unsafe fn __iterator_get_unchecked(&mut self, idx: usize) -> Self::Item { + // SAFETY: since the caller guarantees that `idx` is in bounds, + // which means that `idx` cannot overflow an `isize`, and the + // "slice" created by `cast_array` is a subslice of `self.v` + // thus is guaranteed to be valid for the lifetime `'a` of `self.v`. + unsafe { &*self.v.as_ptr().add(idx).cast_array() } + } } #[stable(feature = "array_windows", since = "1.94.0")] @@ -2252,6 +2268,22 @@ impl ExactSizeIterator for ArrayWindows<'_, T, N> { } } +#[unstable(feature = "trusted_len", issue = "37572")] +unsafe impl TrustedLen for ArrayWindows<'_, T, N> {} + +#[stable(feature = "array_windows", since = "1.94.0")] +impl FusedIterator for ArrayWindows<'_, T, N> {} + +#[doc(hidden)] +#[unstable(feature = "trusted_random_access", issue = "none")] +unsafe impl TrustedRandomAccess for ArrayWindows<'_, T, N> {} + +#[doc(hidden)] +#[unstable(feature = "trusted_random_access", issue = "none")] +unsafe impl TrustedRandomAccessNoCoerce for ArrayWindows<'_, T, N> { + const MAY_HAVE_SIDE_EFFECT: bool = false; +} + /// An iterator over a slice in (non-overlapping) chunks (`chunk_size` elements at a /// time), starting at the end of the slice. /// diff --git a/core/src/str/iter.rs b/core/src/str/iter.rs index d2985d8a18669..283aa9a6a73ae 100644 --- a/core/src/str/iter.rs +++ b/core/src/str/iter.rs @@ -99,9 +99,6 @@ impl<'a> Iterator for Chars<'a> { #[inline] fn size_hint(&self) -> (usize, Option) { let len = self.iter.len(); - // `(len + 3)` can't overflow, because we know that the `slice::Iter` - // belongs to a slice in memory which has a maximum length of - // `isize::MAX` (that's well below `usize::MAX`). (len.div_ceil(4), Some(len)) } @@ -1528,9 +1525,6 @@ impl<'a> Iterator for EncodeUtf16<'a> { // is therefore determined by assuming the remaining bytes contain as // many 3-byte sequences as possible. The highest bytes:code units // ratio is for 1-byte sequences, so use this for the upper bound. - // `(len + 2)` can't overflow, because we know that the `slice::Iter` - // belongs to a slice in memory which has a maximum length of - // `isize::MAX` (that's well below `usize::MAX`) if self.extra == 0 { (len.div_ceil(3), Some(len)) } else { diff --git a/core/src/str/mod.rs b/core/src/str/mod.rs index ab7389a1300c5..98354643aa405 100644 --- a/core/src/str/mod.rs +++ b/core/src/str/mod.rs @@ -85,34 +85,50 @@ fn slice_error_fail_rt(s: &str, begin: usize, end: usize) -> ! { let trunc_len = s.floor_char_boundary(MAX_DISPLAY_LENGTH); let s_trunc = &s[..trunc_len]; let ellipsis = if trunc_len < s.len() { "[...]" } else { "" }; + let len = s.len(); - // 1. out of bounds - if begin > s.len() || end > s.len() { - let oob_index = if begin > s.len() { begin } else { end }; - panic!("byte index {oob_index} is out of bounds of `{s_trunc}`{ellipsis}"); - } - - // 2. begin <= end - assert!( - begin <= end, - "begin <= end ({} <= {}) when slicing `{}`{}", - begin, - end, - s_trunc, - ellipsis - ); - - // 3. character boundary - let index = if !s.is_char_boundary(begin) { begin } else { end }; - // find the character - let char_start = s.floor_char_boundary(index); - // `char_start` must be less than len and a char boundary - let ch = s[char_start..].chars().next().unwrap(); - let char_range = char_start..char_start + ch.len_utf8(); - panic!( - "byte index {} is not a char boundary; it is inside {:?} (bytes {:?}) of `{}`{}", - index, ch, char_range, s_trunc, ellipsis - ); + // 1. begin is OOB. + if begin > len { + panic!("start byte index {begin} is out of bounds of `{s_trunc}`{ellipsis}"); + } + + // 2. end is OOB. + if end > len { + panic!("end byte index {end} is out of bounds of `{s_trunc}`{ellipsis}"); + } + + // 3. range is backwards. + if begin > end { + panic!("begin > end ({begin} > {end}) when slicing `{s_trunc}`{ellipsis}") + } + + // 4. begin is inside a character. + if !s.is_char_boundary(begin) { + let floor = s.floor_char_boundary(begin); + let ceil = s.ceil_char_boundary(begin); + let range = floor..ceil; + let ch = s[floor..ceil].chars().next().unwrap(); + panic!( + "start byte index {begin} is not a char boundary; it is inside {ch:?} (bytes {range:?}) of `{s_trunc}`{ellipsis}" + ) + } + + // 5. end is inside a character. + if !s.is_char_boundary(end) { + let floor = s.floor_char_boundary(end); + let ceil = s.ceil_char_boundary(end); + let range = floor..ceil; + let ch = s[floor..ceil].chars().next().unwrap(); + panic!( + "end byte index {end} is not a char boundary; it is inside {ch:?} (bytes {range:?}) of `{s_trunc}`{ellipsis}" + ) + } + + // 6. end is OOB and range is inclusive (end == len). + // This test cannot be combined with 2. above because for cases like + // `"abcαβγ"[4..9]` the error is that 4 is inside 'α', not that 9 is OOB. + debug_assert_eq!(end, len); + panic!("end byte index {end} is out of bounds of `{s_trunc}`{ellipsis}"); } impl str { diff --git a/core/src/str/pattern.rs b/core/src/str/pattern.rs index b54522fcc886f..25202ffd67313 100644 --- a/core/src/str/pattern.rs +++ b/core/src/str/pattern.rs @@ -997,7 +997,8 @@ impl<'b> Pattern for &'b str { #[cfg(any( all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") + all(target_arch = "loongarch64", target_feature = "lsx"), + all(target_arch = "aarch64", target_feature = "neon") ))] if self.len() <= 32 { if let Some(result) = simd_contains(self, haystack) { @@ -1782,7 +1783,8 @@ impl TwoWayStrategy for RejectAndMatch { /// [0]: http://0x80.pl/articles/simd-strfind.html#sse-avx2 #[cfg(any( all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") + all(target_arch = "loongarch64", target_feature = "lsx"), + all(target_arch = "aarch64", target_feature = "neon") ))] #[inline] fn simd_contains(needle: &str, haystack: &str) -> Option { @@ -1917,7 +1919,8 @@ fn simd_contains(needle: &str, haystack: &str) -> Option { /// Both slices must have the same length. #[cfg(any( all(target_arch = "x86_64", target_feature = "sse2"), - all(target_arch = "loongarch64", target_feature = "lsx") + all(target_arch = "loongarch64", target_feature = "lsx"), + all(target_arch = "aarch64", target_feature = "neon") ))] #[inline] unsafe fn small_slice_eq(x: &[u8], y: &[u8]) -> bool { diff --git a/core/src/str/traits.rs b/core/src/str/traits.rs index a7cc943994c53..edf07c0c16f42 100644 --- a/core/src/str/traits.rs +++ b/core/src/str/traits.rs @@ -76,13 +76,6 @@ where } } -#[inline(never)] -#[cold] -#[track_caller] -const fn str_index_overflow_fail() -> ! { - panic!("attempted to index str up to maximum usize"); -} - /// Implements substring slicing with syntax `&self[..]` or `&mut self[..]`. /// /// Returns a slice of the whole string, i.e., returns `&self` or `&mut @@ -389,12 +382,12 @@ unsafe impl SliceIndex for (ops::Bound, ops::Bound) { #[inline] fn get(self, slice: &str) -> Option<&str> { - crate::slice::index::into_range(slice.len(), self)?.get(slice) + crate::slice::index::try_into_slice_range(slice.len(), self)?.get(slice) } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut str> { - crate::slice::index::into_range(slice.len(), self)?.get_mut(slice) + crate::slice::index::try_into_slice_range(slice.len(), self)?.get_mut(slice) } #[inline] @@ -640,11 +633,11 @@ unsafe impl const SliceIndex for ops::RangeInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get(slice) } } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> { - if *self.end() == usize::MAX { None } else { self.into_slice_range().get_mut(slice) } + if *self.end() >= slice.len() { None } else { self.into_slice_range().get_mut(slice) } } #[inline] unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output { @@ -658,55 +651,69 @@ unsafe impl const SliceIndex for ops::RangeInclusive { } #[inline] fn index(self, slice: &str) -> &Self::Output { - if *self.end() == usize::MAX { - str_index_overflow_fail(); + let Self { mut start, mut end, exhausted } = self; + let len = slice.len(); + if end < len { + end = end + 1; + start = if exhausted { end } else { start }; + if start <= end && slice.is_char_boundary(start) && slice.is_char_boundary(end) { + // SAFETY: just checked that `start` and `end` are on a char boundary, + // and we are passing in a safe reference, so the return value will also be one. + // We also checked char boundaries, so this is valid UTF-8. + unsafe { return &*(start..end).get_unchecked(slice) } + } } - self.into_slice_range().index(slice) + + super::slice_error_fail(slice, start, end) } #[inline] fn index_mut(self, slice: &mut str) -> &mut Self::Output { - if *self.end() == usize::MAX { - str_index_overflow_fail(); + let Self { mut start, mut end, exhausted } = self; + let len = slice.len(); + if end < len { + end = end + 1; + start = if exhausted { end } else { start }; + if start <= end && slice.is_char_boundary(start) && slice.is_char_boundary(end) { + // SAFETY: just checked that `start` and `end` are on a char boundary, + // and we are passing in a safe reference, so the return value will also be one. + // We also checked char boundaries, so this is valid UTF-8. + unsafe { return &mut *(start..end).get_unchecked_mut(slice) } + } } - self.into_slice_range().index_mut(slice) + + super::slice_error_fail(slice, start, end) } } -#[unstable(feature = "new_range_api", issue = "125687")] +#[stable(feature = "new_range_inclusive_api", since = "CURRENT_RUSTC_VERSION")] #[rustc_const_unstable(feature = "const_index", issue = "143775")] unsafe impl const SliceIndex for range::RangeInclusive { type Output = str; #[inline] fn get(self, slice: &str) -> Option<&Self::Output> { - if self.last == usize::MAX { None } else { self.into_slice_range().get(slice) } + ops::RangeInclusive::from(self).get(slice) } #[inline] fn get_mut(self, slice: &mut str) -> Option<&mut Self::Output> { - if self.last == usize::MAX { None } else { self.into_slice_range().get_mut(slice) } + ops::RangeInclusive::from(self).get_mut(slice) } #[inline] unsafe fn get_unchecked(self, slice: *const str) -> *const Self::Output { // SAFETY: the caller must uphold the safety contract for `get_unchecked`. - unsafe { self.into_slice_range().get_unchecked(slice) } + unsafe { ops::RangeInclusive::from(self).get_unchecked(slice) } } #[inline] unsafe fn get_unchecked_mut(self, slice: *mut str) -> *mut Self::Output { // SAFETY: the caller must uphold the safety contract for `get_unchecked_mut`. - unsafe { self.into_slice_range().get_unchecked_mut(slice) } + unsafe { ops::RangeInclusive::from(self).get_unchecked_mut(slice) } } #[inline] fn index(self, slice: &str) -> &Self::Output { - if self.last == usize::MAX { - str_index_overflow_fail(); - } - self.into_slice_range().index(slice) + ops::RangeInclusive::from(self).index(slice) } #[inline] fn index_mut(self, slice: &mut str) -> &mut Self::Output { - if self.last == usize::MAX { - str_index_overflow_fail(); - } - self.into_slice_range().index_mut(slice) + ops::RangeInclusive::from(self).index_mut(slice) } } diff --git a/core/src/sync/atomic.rs b/core/src/sync/atomic.rs index 22f46ec385ced..adc2bbcde51b0 100644 --- a/core/src/sync/atomic.rs +++ b/core/src/sync/atomic.rs @@ -1287,73 +1287,27 @@ impl AtomicBool { self.v.get().cast() } - /// Fetches the value, and applies a function to it that returns an optional - /// new value. Returns a `Result` of `Ok(previous_value)` if the function - /// returned `Some(_)`, else `Err(previous_value)`. - /// - /// Note: This may call the function multiple times if the value has been - /// changed from other threads in the meantime, as long as the function - /// returns `Some(_)`, but the function will have been applied only once to - /// the stored value. - /// - /// `fetch_update` takes two [`Ordering`] arguments to describe the memory - /// ordering of this operation. The first describes the required ordering for - /// when the operation finally succeeds while the second describes the - /// required ordering for loads. These correspond to the success and failure - /// orderings of [`AtomicBool::compare_exchange`] respectively. - /// - /// Using [`Acquire`] as success ordering makes the store part of this - /// operation [`Relaxed`], and using [`Release`] makes the final successful - /// load [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`], - /// [`Acquire`] or [`Relaxed`]. - /// - /// **Note:** This method is only available on platforms that support atomic - /// operations on `u8`. - /// - /// # Considerations - /// - /// This method is not magic; it is not provided by the hardware, and does not act like a - /// critical section or mutex. - /// - /// It is implemented on top of an atomic [compare-and-swap operation], and thus is subject to - /// the usual drawbacks of CAS operations. In particular, be careful of the [ABA problem]. - /// - /// [ABA Problem]: https://en.wikipedia.org/wiki/ABA_problem - /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap - /// - /// # Examples - /// - /// ```rust - /// use std::sync::atomic::{AtomicBool, Ordering}; - /// - /// let x = AtomicBool::new(false); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(false)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(!x)), Ok(false)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(!x)), Ok(true)); - /// assert_eq!(x.load(Ordering::SeqCst), false); - /// ``` + /// An alias for [`AtomicBool::try_update`]. #[inline] #[stable(feature = "atomic_fetch_update", since = "1.53.0")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] + #[deprecated( + since = "1.99.0", + note = "renamed to `try_update` for consistency", + suggestion = "try_update" + )] pub fn fetch_update( &self, set_order: Ordering, fetch_order: Ordering, - mut f: F, + f: F, ) -> Result where F: FnMut(bool) -> Option, { - let mut prev = self.load(fetch_order); - while let Some(next) = f(prev) { - match self.compare_exchange_weak(prev, next, set_order, fetch_order) { - x @ Ok(_) => return x, - Err(next_prev) => prev = next_prev, - } - } - Err(prev) + self.try_update(set_order, fetch_order, f) } /// Fetches the value, and applies a function to it that returns an optional @@ -1395,7 +1349,6 @@ impl AtomicBool { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// use std::sync::atomic::{AtomicBool, Ordering}; /// /// let x = AtomicBool::new(false); @@ -1405,7 +1358,7 @@ impl AtomicBool { /// assert_eq!(x.load(Ordering::SeqCst), false); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "CURRENT_RUSTC_VERSION")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -1413,11 +1366,16 @@ impl AtomicBool { &self, set_order: Ordering, fetch_order: Ordering, - f: impl FnMut(bool) -> Option, + mut f: impl FnMut(bool) -> Option, ) -> Result { - // FIXME(atomic_try_update): this is currently an unstable alias to `fetch_update`; - // when stabilizing, turn `fetch_update` into a deprecated alias to `try_update`. - self.fetch_update(set_order, fetch_order, f) + let mut prev = self.load(fetch_order); + while let Some(next) = f(prev) { + match self.compare_exchange_weak(prev, next, set_order, fetch_order) { + x @ Ok(_) => return x, + Err(next_prev) => prev = next_prev, + } + } + Err(prev) } /// Fetches the value, applies a function to it that it return a new value. @@ -1454,7 +1412,6 @@ impl AtomicBool { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// /// use std::sync::atomic::{AtomicBool, Ordering}; /// @@ -1464,7 +1421,7 @@ impl AtomicBool { /// assert_eq!(x.load(Ordering::SeqCst), false); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "CURRENT_RUSTC_VERSION")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -2000,83 +1957,27 @@ impl AtomicPtr { unsafe { atomic_compare_exchange_weak(self.p.get(), current, new, success, failure) } } - /// Fetches the value, and applies a function to it that returns an optional - /// new value. Returns a `Result` of `Ok(previous_value)` if the function - /// returned `Some(_)`, else `Err(previous_value)`. - /// - /// Note: This may call the function multiple times if the value has been - /// changed from other threads in the meantime, as long as the function - /// returns `Some(_)`, but the function will have been applied only once to - /// the stored value. - /// - /// `fetch_update` takes two [`Ordering`] arguments to describe the memory - /// ordering of this operation. The first describes the required ordering for - /// when the operation finally succeeds while the second describes the - /// required ordering for loads. These correspond to the success and failure - /// orderings of [`AtomicPtr::compare_exchange`] respectively. - /// - /// Using [`Acquire`] as success ordering makes the store part of this - /// operation [`Relaxed`], and using [`Release`] makes the final successful - /// load [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`], - /// [`Acquire`] or [`Relaxed`]. - /// - /// **Note:** This method is only available on platforms that support atomic - /// operations on pointers. - /// - /// # Considerations - /// - /// This method is not magic; it is not provided by the hardware, and does not act like a - /// critical section or mutex. - /// - /// It is implemented on top of an atomic [compare-and-swap operation], and thus is subject to - /// the usual drawbacks of CAS operations. In particular, be careful of the [ABA problem], - /// which is a particularly common pitfall for pointers! - /// - /// [ABA Problem]: https://en.wikipedia.org/wiki/ABA_problem - /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap - /// - /// # Examples - /// - /// ```rust - /// use std::sync::atomic::{AtomicPtr, Ordering}; - /// - /// let ptr: *mut _ = &mut 5; - /// let some_ptr = AtomicPtr::new(ptr); - /// - /// let new: *mut _ = &mut 10; - /// assert_eq!(some_ptr.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(ptr)); - /// let result = some_ptr.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| { - /// if x == ptr { - /// Some(new) - /// } else { - /// None - /// } - /// }); - /// assert_eq!(result, Ok(ptr)); - /// assert_eq!(some_ptr.load(Ordering::SeqCst), new); - /// ``` + /// An alias for [`AtomicPtr::try_update`]. #[inline] #[stable(feature = "atomic_fetch_update", since = "1.53.0")] #[cfg(target_has_atomic = "ptr")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] + #[deprecated( + since = "1.99.0", + note = "renamed to `try_update` for consistency", + suggestion = "try_update" + )] pub fn fetch_update( &self, set_order: Ordering, fetch_order: Ordering, - mut f: F, + f: F, ) -> Result<*mut T, *mut T> where F: FnMut(*mut T) -> Option<*mut T>, { - let mut prev = self.load(fetch_order); - while let Some(next) = f(prev) { - match self.compare_exchange_weak(prev, next, set_order, fetch_order) { - x @ Ok(_) => return x, - Err(next_prev) => prev = next_prev, - } - } - Err(prev) + self.try_update(set_order, fetch_order, f) } /// Fetches the value, and applies a function to it that returns an optional /// new value. Returns a `Result` of `Ok(previous_value)` if the function @@ -2118,7 +2019,6 @@ impl AtomicPtr { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// use std::sync::atomic::{AtomicPtr, Ordering}; /// /// let ptr: *mut _ = &mut 5; @@ -2137,7 +2037,7 @@ impl AtomicPtr { /// assert_eq!(some_ptr.load(Ordering::SeqCst), new); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "CURRENT_RUSTC_VERSION")] #[cfg(target_has_atomic = "ptr")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -2145,11 +2045,16 @@ impl AtomicPtr { &self, set_order: Ordering, fetch_order: Ordering, - f: impl FnMut(*mut T) -> Option<*mut T>, + mut f: impl FnMut(*mut T) -> Option<*mut T>, ) -> Result<*mut T, *mut T> { - // FIXME(atomic_try_update): this is currently an unstable alias to `fetch_update`; - // when stabilizing, turn `fetch_update` into a deprecated alias to `try_update`. - self.fetch_update(set_order, fetch_order, f) + let mut prev = self.load(fetch_order); + while let Some(next) = f(prev) { + match self.compare_exchange_weak(prev, next, set_order, fetch_order) { + x @ Ok(_) => return x, + Err(next_prev) => prev = next_prev, + } + } + Err(prev) } /// Fetches the value, applies a function to it that it return a new value. @@ -2188,7 +2093,6 @@ impl AtomicPtr { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] /// /// use std::sync::atomic::{AtomicPtr, Ordering}; /// @@ -2201,7 +2105,7 @@ impl AtomicPtr { /// assert_eq!(some_ptr.load(Ordering::SeqCst), new); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "CURRENT_RUSTC_VERSION")] #[cfg(target_has_atomic = "8")] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -3399,69 +3303,25 @@ macro_rules! atomic_int { unsafe { atomic_xor(self.v.get(), val, order) } } - /// Fetches the value, and applies a function to it that returns an optional - /// new value. Returns a `Result` of `Ok(previous_value)` if the function returned `Some(_)`, else - /// `Err(previous_value)`. - /// - /// Note: This may call the function multiple times if the value has been changed from other threads in - /// the meantime, as long as the function returns `Some(_)`, but the function will have been applied - /// only once to the stored value. - /// - /// `fetch_update` takes two [`Ordering`] arguments to describe the memory ordering of this operation. - /// The first describes the required ordering for when the operation finally succeeds while the second - /// describes the required ordering for loads. These correspond to the success and failure orderings of - #[doc = concat!("[`", stringify!($atomic_type), "::compare_exchange`]")] - /// respectively. - /// - /// Using [`Acquire`] as success ordering makes the store part - /// of this operation [`Relaxed`], and using [`Release`] makes the final successful load - /// [`Relaxed`]. The (failed) load ordering can only be [`SeqCst`], [`Acquire`] or [`Relaxed`]. - /// - /// **Note**: This method is only available on platforms that support atomic operations on - #[doc = concat!("[`", $s_int_type, "`].")] - /// - /// # Considerations - /// - /// This method is not magic; it is not provided by the hardware, and does not act like a - /// critical section or mutex. - /// - /// It is implemented on top of an atomic [compare-and-swap operation], and thus is subject to - /// the usual drawbacks of CAS operations. In particular, be careful of the [ABA problem] - /// if this atomic integer is an index or more generally if knowledge of only the *bitwise value* - /// of the atomic is not in and of itself sufficient to ensure any required preconditions. - /// - /// [ABA Problem]: https://en.wikipedia.org/wiki/ABA_problem - /// [compare-and-swap operation]: https://en.wikipedia.org/wiki/Compare-and-swap - /// - /// # Examples - /// - /// ```rust - #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] - /// - #[doc = concat!("let x = ", stringify!($atomic_type), "::new(7);")] - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |_| None), Err(7)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(x + 1)), Ok(7)); - /// assert_eq!(x.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |x| Some(x + 1)), Ok(8)); - /// assert_eq!(x.load(Ordering::SeqCst), 9); - /// ``` + /// An alias for + #[doc = concat!("[`", stringify!($atomic_type), "::try_update`]")] + /// . #[inline] #[stable(feature = "no_more_cas", since = "1.45.0")] #[$cfg_cas] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] + #[deprecated( + since = "1.99.0", + note = "renamed to `try_update` for consistency", + suggestion = "try_update" + )] pub fn fetch_update(&self, set_order: Ordering, fetch_order: Ordering, - mut f: F) -> Result<$int_type, $int_type> + f: F) -> Result<$int_type, $int_type> where F: FnMut($int_type) -> Option<$int_type> { - let mut prev = self.load(fetch_order); - while let Some(next) = f(prev) { - match self.compare_exchange_weak(prev, next, set_order, fetch_order) { - x @ Ok(_) => return x, - Err(next_prev) => prev = next_prev - } - } - Err(prev) + self.try_update(set_order, fetch_order, f) } /// Fetches the value, and applies a function to it that returns an optional @@ -3503,7 +3363,6 @@ macro_rules! atomic_int { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let x = ", stringify!($atomic_type), "::new(7);")] @@ -3513,7 +3372,7 @@ macro_rules! atomic_int { /// assert_eq!(x.load(Ordering::SeqCst), 9); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "CURRENT_RUSTC_VERSION")] #[$cfg_cas] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] @@ -3521,11 +3380,16 @@ macro_rules! atomic_int { &self, set_order: Ordering, fetch_order: Ordering, - f: impl FnMut($int_type) -> Option<$int_type>, + mut f: impl FnMut($int_type) -> Option<$int_type>, ) -> Result<$int_type, $int_type> { - // FIXME(atomic_try_update): this is currently an unstable alias to `fetch_update`; - // when stabilizing, turn `fetch_update` into a deprecated alias to `try_update`. - self.fetch_update(set_order, fetch_order, f) + let mut prev = self.load(fetch_order); + while let Some(next) = f(prev) { + match self.compare_exchange_weak(prev, next, set_order, fetch_order) { + x @ Ok(_) => return x, + Err(next_prev) => prev = next_prev + } + } + Err(prev) } /// Fetches the value, applies a function to it that it return a new value. @@ -3566,7 +3430,6 @@ macro_rules! atomic_int { /// # Examples /// /// ```rust - /// #![feature(atomic_try_update)] #[doc = concat!($extra_feature, "use std::sync::atomic::{", stringify!($atomic_type), ", Ordering};")] /// #[doc = concat!("let x = ", stringify!($atomic_type), "::new(7);")] @@ -3575,7 +3438,7 @@ macro_rules! atomic_int { /// assert_eq!(x.load(Ordering::SeqCst), 9); /// ``` #[inline] - #[unstable(feature = "atomic_try_update", issue = "135894")] + #[stable(feature = "atomic_try_update", since = "CURRENT_RUSTC_VERSION")] #[$cfg_cas] #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces #[rustc_should_not_be_called_on_const_items] diff --git a/core/src/time.rs b/core/src/time.rs index b4efc09684e7f..a5b654033ba14 100644 --- a/core/src/time.rs +++ b/core/src/time.rs @@ -690,7 +690,6 @@ impl Duration { /// # Examples /// /// ``` - /// #![feature(duration_constants)] /// use std::time::Duration; /// /// assert_eq!(Duration::new(0, 0).saturating_add(Duration::new(0, 1)), Duration::new(0, 1)); @@ -801,7 +800,6 @@ impl Duration { /// # Examples /// /// ``` - /// #![feature(duration_constants)] /// use std::time::Duration; /// /// assert_eq!(Duration::new(0, 500_000_001).saturating_mul(2), Duration::new(1, 2)); diff --git a/coretests/tests/cmp.rs b/coretests/tests/cmp.rs index 55e35a4a7250e..0a14470060c3d 100644 --- a/coretests/tests/cmp.rs +++ b/coretests/tests/cmp.rs @@ -1,5 +1,5 @@ +use core::cmp; use core::cmp::Ordering::{self, *}; -use core::cmp::{self}; #[test] fn test_int_totalord() { diff --git a/coretests/tests/floats/mod.rs b/coretests/tests/floats/mod.rs index 06fc3c96eafc8..b729cdf8458d7 100644 --- a/coretests/tests/floats/mod.rs +++ b/coretests/tests/floats/mod.rs @@ -2,19 +2,37 @@ use std::num::FpCategory as Fp; use std::ops::{Add, Div, Mul, Rem, Sub}; trait TestableFloat: Sized { + const BITS: u32; /// Unsigned int with the same size, for converting to/from bits. type Int; + /// Signed int with the same size. + type SInt; /// Set the default tolerance for float comparison based on the type. const APPROX: Self; /// Allow looser tolerance for f32 on miri const POWI_APPROX: Self = Self::APPROX; + /// Tolerance for `powf` tests; some types need looser bounds + const POWF_APPROX: Self = Self::APPROX; /// Allow looser tolerance for f16 const _180_TO_RADIANS_APPROX: Self = Self::APPROX; /// Allow for looser tolerance for f16 const PI_TO_DEGREES_APPROX: Self = Self::APPROX; + /// Tolerance for math tests + const EXP_APPROX: Self = Self::APPROX; + const LN_APPROX: Self = Self::APPROX; + const LOG_APPROX: Self = Self::APPROX; + const LOG2_APPROX: Self = Self::APPROX; + const LOG10_APPROX: Self = Self::APPROX; + const ASINH_APPROX: Self = Self::APPROX; + const ACOSH_APPROX: Self = Self::APPROX; + const ATANH_APPROX: Self = Self::APPROX; + const GAMMA_APPROX: Self = Self::APPROX; + const GAMMA_APPROX_LOOSE: Self = Self::APPROX; + const LNGAMMA_APPROX: Self = Self::APPROX; + const LNGAMMA_APPROX_LOOSE: Self = Self::APPROX; const ZERO: Self; const ONE: Self; - const PI: Self; + const MIN_POSITIVE_NORMAL: Self; const MAX_SUBNORMAL: Self; /// Smallest number @@ -43,13 +61,27 @@ trait TestableFloat: Sized { } impl TestableFloat for f16 { + const BITS: u32 = 16; type Int = u16; + type SInt = i16; const APPROX: Self = 1e-3; + const POWF_APPROX: Self = 5e-1; const _180_TO_RADIANS_APPROX: Self = 1e-2; const PI_TO_DEGREES_APPROX: Self = 0.125; + const EXP_APPROX: Self = 1e-2; + const LN_APPROX: Self = 1e-2; + const LOG_APPROX: Self = 1e-2; + const LOG2_APPROX: Self = 1e-2; + const LOG10_APPROX: Self = 1e-2; + const ASINH_APPROX: Self = 1e-2; + const ACOSH_APPROX: Self = 1e-2; + const ATANH_APPROX: Self = 1e-2; + const GAMMA_APPROX: Self = 1e-2; + const GAMMA_APPROX_LOOSE: Self = 1e-1; + const LNGAMMA_APPROX: Self = 1e-2; + const LNGAMMA_APPROX_LOOSE: Self = 1e-1; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f16::consts::PI; const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -70,15 +102,29 @@ impl TestableFloat for f16 { } impl TestableFloat for f32 { + const BITS: u32 = 32; type Int = u32; + type SInt = i32; const APPROX: Self = 1e-6; /// Miri adds some extra errors to float functions; make sure the tests still pass. /// These values are purely used as a canary to test against and are thus not a stable guarantee Rust provides. /// They serve as a way to get an idea of the real precision of floating point operations on different platforms. const POWI_APPROX: Self = if cfg!(miri) { 1e-4 } else { Self::APPROX }; + const POWF_APPROX: Self = if cfg!(miri) { 1e-3 } else { 1e-4 }; + const EXP_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LN_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LOG_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LOG2_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LOG10_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const ASINH_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const ACOSH_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const ATANH_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const GAMMA_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const GAMMA_APPROX_LOOSE: Self = if cfg!(miri) { 1e-2 } else { 1e-4 }; + const LNGAMMA_APPROX: Self = if cfg!(miri) { 1e-3 } else { Self::APPROX }; + const LNGAMMA_APPROX_LOOSE: Self = if cfg!(miri) { 1e-2 } else { 1e-4 }; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f32::consts::PI; const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -99,11 +145,14 @@ impl TestableFloat for f32 { } impl TestableFloat for f64 { + const BITS: u32 = 64; type Int = u64; + type SInt = i64; const APPROX: Self = 1e-6; + const GAMMA_APPROX_LOOSE: Self = 1e-4; + const LNGAMMA_APPROX_LOOSE: Self = 1e-4; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f64::consts::PI; const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -124,11 +173,24 @@ impl TestableFloat for f64 { } impl TestableFloat for f128 { + const BITS: u32 = 128; type Int = u128; + type SInt = i128; const APPROX: Self = 1e-9; + const EXP_APPROX: Self = 1e-12; + const LN_APPROX: Self = 1e-12; + const LOG_APPROX: Self = 1e-12; + const LOG2_APPROX: Self = 1e-12; + const LOG10_APPROX: Self = 1e-12; + const ASINH_APPROX: Self = 1e-10; + const ACOSH_APPROX: Self = 1e-10; + const ATANH_APPROX: Self = 1e-10; + const GAMMA_APPROX: Self = 1e-12; + const GAMMA_APPROX_LOOSE: Self = 1e-10; + const LNGAMMA_APPROX: Self = 1e-12; + const LNGAMMA_APPROX_LOOSE: Self = 1e-10; const ZERO: Self = 0.0; const ONE: Self = 1.0; - const PI: Self = std::f128::consts::PI; const MIN_POSITIVE_NORMAL: Self = Self::MIN_POSITIVE; const MAX_SUBNORMAL: Self = Self::MIN_POSITIVE.next_down(); const TINY: Self = Self::from_bits(0x1); @@ -287,6 +349,8 @@ macro_rules! float_test { #[test] $( $( #[$f16_meta] )+ )? fn test_f16() { + #[allow(unused_imports)] + use core::f16::consts; type $fty = f16; #[allow(unused)] const fn flt (x: $fty) -> $fty { x } @@ -296,6 +360,8 @@ macro_rules! float_test { #[test] $( $( #[$f32_meta] )+ )? fn test_f32() { + #[allow(unused_imports)] + use core::f32::consts; type $fty = f32; #[allow(unused)] const fn flt (x: $fty) -> $fty { x } @@ -305,6 +371,8 @@ macro_rules! float_test { #[test] $( $( #[$f64_meta] )+ )? fn test_f64() { + #[allow(unused_imports)] + use core::f64::consts; type $fty = f64; #[allow(unused)] const fn flt (x: $fty) -> $fty { x } @@ -314,6 +382,8 @@ macro_rules! float_test { #[test] $( $( #[$f128_meta] )+ )? fn test_f128() { + #[allow(unused_imports)] + use core::f128::consts; type $fty = f128; #[allow(unused)] const fn flt (x: $fty) -> $fty { x } @@ -338,6 +408,8 @@ macro_rules! float_test { #[test] $( $( #[$f16_const_meta] )+ )? fn test_f16() { + #[allow(unused_imports)] + use core::f16::consts; type $fty = f16; #[allow(unused)] const fn flt (x: $fty) -> $fty { x } @@ -347,6 +419,8 @@ macro_rules! float_test { #[test] $( $( #[$f32_const_meta] )+ )? fn test_f32() { + #[allow(unused_imports)] + use core::f32::consts; type $fty = f32; #[allow(unused)] const fn flt (x: $fty) -> $fty { x } @@ -356,6 +430,8 @@ macro_rules! float_test { #[test] $( $( #[$f64_const_meta] )+ )? fn test_f64() { + #[allow(unused_imports)] + use core::f64::consts; type $fty = f64; #[allow(unused)] const fn flt (x: $fty) -> $fty { x } @@ -365,6 +441,8 @@ macro_rules! float_test { #[test] $( $( #[$f128_const_meta] )+ )? fn test_f128() { + #[allow(unused_imports)] + use core::f128::consts; type $fty = f128; #[allow(unused)] const fn flt (x: $fty) -> $fty { x } @@ -631,25 +709,25 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((0.0 as Float).min(0.0), 0.0); - assert_biteq!((-0.0 as Float).min(-0.0), -0.0); - assert_biteq!((9.0 as Float).min(9.0), 9.0); - assert_biteq!((-9.0 as Float).min(0.0), -9.0); - assert_biteq!((0.0 as Float).min(9.0), 0.0); - assert_biteq!((-0.0 as Float).min(9.0), -0.0); - assert_biteq!((-0.0 as Float).min(-9.0), -9.0); + assert_biteq!(flt(0.0).min(0.0), 0.0); + assert_biteq!(flt(-0.0).min(-0.0), -0.0); + assert_biteq!(flt(9.0).min(9.0), 9.0); + assert_biteq!(flt(-9.0).min(0.0), -9.0); + assert_biteq!(flt(0.0).min(9.0), 0.0); + assert_biteq!(flt(-0.0).min(9.0), -0.0); + assert_biteq!(flt(-0.0).min(-9.0), -9.0); assert_biteq!(Float::INFINITY.min(9.0), 9.0); - assert_biteq!((9.0 as Float).min(Float::INFINITY), 9.0); + assert_biteq!(flt(9.0).min(Float::INFINITY), 9.0); assert_biteq!(Float::INFINITY.min(-9.0), -9.0); - assert_biteq!((-9.0 as Float).min(Float::INFINITY), -9.0); + assert_biteq!(flt(-9.0).min(Float::INFINITY), -9.0); assert_biteq!(Float::NEG_INFINITY.min(9.0), Float::NEG_INFINITY); - assert_biteq!((9.0 as Float).min(Float::NEG_INFINITY), Float::NEG_INFINITY); + assert_biteq!(flt(9.0).min(Float::NEG_INFINITY), Float::NEG_INFINITY); assert_biteq!(Float::NEG_INFINITY.min(-9.0), Float::NEG_INFINITY); - assert_biteq!((-9.0 as Float).min(Float::NEG_INFINITY), Float::NEG_INFINITY); + assert_biteq!(flt(-9.0).min(Float::NEG_INFINITY), Float::NEG_INFINITY); assert_biteq!(Float::NAN.min(9.0), 9.0); assert_biteq!(Float::NAN.min(-9.0), -9.0); - assert_biteq!((9.0 as Float).min(Float::NAN), 9.0); - assert_biteq!((-9.0 as Float).min(Float::NAN), -9.0); + assert_biteq!(flt(9.0).min(Float::NAN), 9.0); + assert_biteq!(flt(-9.0).min(Float::NAN), -9.0); assert!(Float::NAN.min(Float::NAN).is_nan()); } } @@ -661,26 +739,26 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((0.0 as Float).max(0.0), 0.0); - assert_biteq!((-0.0 as Float).max(-0.0), -0.0); - assert_biteq!((9.0 as Float).max(9.0), 9.0); - assert_biteq!((-9.0 as Float).max(0.0), 0.0); - assert_biteq!((-9.0 as Float).max(-0.0), -0.0); - assert_biteq!((0.0 as Float).max(9.0), 9.0); - assert_biteq!((0.0 as Float).max(-9.0), 0.0); - assert_biteq!((-0.0 as Float).max(-9.0), -0.0); + assert_biteq!(flt(0.0).max(0.0), 0.0); + assert_biteq!(flt(-0.0).max(-0.0), -0.0); + assert_biteq!(flt(9.0).max(9.0), 9.0); + assert_biteq!(flt(-9.0).max(0.0), 0.0); + assert_biteq!(flt(-9.0).max(-0.0), -0.0); + assert_biteq!(flt(0.0).max(9.0), 9.0); + assert_biteq!(flt(0.0).max(-9.0), 0.0); + assert_biteq!(flt(-0.0).max(-9.0), -0.0); assert_biteq!(Float::INFINITY.max(9.0), Float::INFINITY); - assert_biteq!((9.0 as Float).max(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(9.0).max(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::INFINITY.max(-9.0), Float::INFINITY); - assert_biteq!((-9.0 as Float).max(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(-9.0).max(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::NEG_INFINITY.max(9.0), 9.0); - assert_biteq!((9.0 as Float).max(Float::NEG_INFINITY), 9.0); + assert_biteq!(flt(9.0).max(Float::NEG_INFINITY), 9.0); assert_biteq!(Float::NEG_INFINITY.max(-9.0), -9.0); - assert_biteq!((-9.0 as Float).max(Float::NEG_INFINITY), -9.0); + assert_biteq!(flt(-9.0).max(Float::NEG_INFINITY), -9.0); assert_biteq!(Float::NAN.max(9.0), 9.0); assert_biteq!(Float::NAN.max(-9.0), -9.0); - assert_biteq!((9.0 as Float).max(Float::NAN), 9.0); - assert_biteq!((-9.0 as Float).max(Float::NAN), -9.0); + assert_biteq!(flt(9.0).max(Float::NAN), 9.0); + assert_biteq!(flt(-9.0).max(Float::NAN), -9.0); assert!(Float::NAN.max(Float::NAN).is_nan()); } } @@ -692,26 +770,26 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((0.0 as Float).minimum(0.0), 0.0); - assert_biteq!((-0.0 as Float).minimum(0.0), -0.0); - assert_biteq!((-0.0 as Float).minimum(-0.0), -0.0); - assert_biteq!((9.0 as Float).minimum(9.0), 9.0); - assert_biteq!((-9.0 as Float).minimum(0.0), -9.0); - assert_biteq!((0.0 as Float).minimum(9.0), 0.0); - assert_biteq!((-0.0 as Float).minimum(9.0), -0.0); - assert_biteq!((-0.0 as Float).minimum(-9.0), -9.0); + assert_biteq!(flt(0.0).minimum(0.0), 0.0); + assert_biteq!(flt(-0.0).minimum(0.0), -0.0); + assert_biteq!(flt(-0.0).minimum(-0.0), -0.0); + assert_biteq!(flt(9.0).minimum(9.0), 9.0); + assert_biteq!(flt(-9.0).minimum(0.0), -9.0); + assert_biteq!(flt(0.0).minimum(9.0), 0.0); + assert_biteq!(flt(-0.0).minimum(9.0), -0.0); + assert_biteq!(flt(-0.0).minimum(-9.0), -9.0); assert_biteq!(Float::INFINITY.minimum(9.0), 9.0); - assert_biteq!((9.0 as Float).minimum(Float::INFINITY), 9.0); + assert_biteq!(flt(9.0).minimum(Float::INFINITY), 9.0); assert_biteq!(Float::INFINITY.minimum(-9.0), -9.0); - assert_biteq!((-9.0 as Float).minimum(Float::INFINITY), -9.0); + assert_biteq!(flt(-9.0).minimum(Float::INFINITY), -9.0); assert_biteq!(Float::NEG_INFINITY.minimum(9.0), Float::NEG_INFINITY); - assert_biteq!((9.0 as Float).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); + assert_biteq!(flt(9.0).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); assert_biteq!(Float::NEG_INFINITY.minimum(-9.0), Float::NEG_INFINITY); - assert_biteq!((-9.0 as Float).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); + assert_biteq!(flt(-9.0).minimum(Float::NEG_INFINITY), Float::NEG_INFINITY); assert!(Float::NAN.minimum(9.0).is_nan()); assert!(Float::NAN.minimum(-9.0).is_nan()); - assert!((9.0 as Float).minimum(Float::NAN).is_nan()); - assert!((-9.0 as Float).minimum(Float::NAN).is_nan()); + assert!(flt(9.0).minimum(Float::NAN).is_nan()); + assert!(flt(-9.0).minimum(Float::NAN).is_nan()); assert!(Float::NAN.minimum(Float::NAN).is_nan()); } } @@ -723,27 +801,27 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((0.0 as Float).maximum(0.0), 0.0); - assert_biteq!((-0.0 as Float).maximum(0.0), 0.0); - assert_biteq!((-0.0 as Float).maximum(-0.0), -0.0); - assert_biteq!((9.0 as Float).maximum(9.0), 9.0); - assert_biteq!((-9.0 as Float).maximum(0.0), 0.0); - assert_biteq!((-9.0 as Float).maximum(-0.0), -0.0); - assert_biteq!((0.0 as Float).maximum(9.0), 9.0); - assert_biteq!((0.0 as Float).maximum(-9.0), 0.0); - assert_biteq!((-0.0 as Float).maximum(-9.0), -0.0); + assert_biteq!(flt(0.0).maximum(0.0), 0.0); + assert_biteq!(flt(-0.0).maximum(0.0), 0.0); + assert_biteq!(flt(-0.0).maximum(-0.0), -0.0); + assert_biteq!(flt(9.0).maximum(9.0), 9.0); + assert_biteq!(flt(-9.0).maximum(0.0), 0.0); + assert_biteq!(flt(-9.0).maximum(-0.0), -0.0); + assert_biteq!(flt(0.0).maximum(9.0), 9.0); + assert_biteq!(flt(0.0).maximum(-9.0), 0.0); + assert_biteq!(flt(-0.0).maximum(-9.0), -0.0); assert_biteq!(Float::INFINITY.maximum(9.0), Float::INFINITY); - assert_biteq!((9.0 as Float).maximum(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(9.0).maximum(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::INFINITY.maximum(-9.0), Float::INFINITY); - assert_biteq!((-9.0 as Float).maximum(Float::INFINITY), Float::INFINITY); + assert_biteq!(flt(-9.0).maximum(Float::INFINITY), Float::INFINITY); assert_biteq!(Float::NEG_INFINITY.maximum(9.0), 9.0); - assert_biteq!((9.0 as Float).maximum(Float::NEG_INFINITY), 9.0); + assert_biteq!(flt(9.0).maximum(Float::NEG_INFINITY), 9.0); assert_biteq!(Float::NEG_INFINITY.maximum(-9.0), -9.0); - assert_biteq!((-9.0 as Float).maximum(Float::NEG_INFINITY), -9.0); + assert_biteq!(flt(-9.0).maximum(Float::NEG_INFINITY), -9.0); assert!(Float::NAN.maximum(9.0).is_nan()); assert!(Float::NAN.maximum(-9.0).is_nan()); - assert!((9.0 as Float).maximum(Float::NAN).is_nan()); - assert!((-9.0 as Float).maximum(Float::NAN).is_nan()); + assert!(flt(9.0).maximum(Float::NAN).is_nan()); + assert!(flt(-9.0).maximum(Float::NAN).is_nan()); assert!(Float::NAN.maximum(Float::NAN).is_nan()); } } @@ -755,15 +833,15 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((0.5 as Float).midpoint(0.5), 0.5); - assert_biteq!((0.5 as Float).midpoint(2.5), 1.5); - assert_biteq!((3.0 as Float).midpoint(4.0), 3.5); - assert_biteq!((-3.0 as Float).midpoint(4.0), 0.5); - assert_biteq!((3.0 as Float).midpoint(-4.0), -0.5); - assert_biteq!((-3.0 as Float).midpoint(-4.0), -3.5); - assert_biteq!((0.0 as Float).midpoint(0.0), 0.0); - assert_biteq!((-0.0 as Float).midpoint(-0.0), -0.0); - assert_biteq!((-5.0 as Float).midpoint(5.0), 0.0); + assert_biteq!(flt(0.5).midpoint(0.5), 0.5); + assert_biteq!(flt(0.5).midpoint(2.5), 1.5); + assert_biteq!(flt(3.0).midpoint(4.0), 3.5); + assert_biteq!(flt(-3.0).midpoint(4.0), 0.5); + assert_biteq!(flt(3.0).midpoint(-4.0), -0.5); + assert_biteq!(flt(-3.0).midpoint(-4.0), -3.5); + assert_biteq!(flt(0.0).midpoint(0.0), 0.0); + assert_biteq!(flt(-0.0).midpoint(-0.0), -0.0); + assert_biteq!(flt(-5.0).midpoint(5.0), 0.0); assert_biteq!(Float::MAX.midpoint(Float::MIN), 0.0); assert_biteq!(Float::MIN.midpoint(Float::MAX), 0.0); assert_biteq!(Float::MAX.midpoint(Float::MIN_POSITIVE), Float::MAX / 2.); @@ -793,7 +871,7 @@ float_test! { assert!(Float::NEG_INFINITY.midpoint(Float::INFINITY).is_nan()); assert!(Float::INFINITY.midpoint(Float::NEG_INFINITY).is_nan()); assert!(Float::NAN.midpoint(1.0).is_nan()); - assert!((1.0 as Float).midpoint(Float::NAN).is_nan()); + assert!(flt(1.0).midpoint(Float::NAN).is_nan()); assert!(Float::NAN.midpoint(Float::NAN).is_nan()); } } @@ -815,10 +893,10 @@ float_test! { // be safely doubled, while j is significantly smaller. for i in Float::MAX_EXP.saturating_sub(64)..Float::MAX_EXP { for j in 0..64u8 { - let large = (2.0 as Float).powi(i); + let large = flt(2.0).powi(i); // a much smaller number, such that there is no chance of overflow to test // potential double rounding in midpoint's implementation. - let small = (2.0 as Float).powi(Float::MAX_EXP - 1) + let small = flt(2.0).powi(Float::MAX_EXP - 1) * Float::EPSILON * Float::from(j); @@ -856,8 +934,8 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((1.0 as Float).copysign(-2.0), -1.0); - assert_biteq!((-1.0 as Float).copysign(2.0), 1.0); + assert_biteq!(flt(1.0).copysign(-2.0), -1.0); + assert_biteq!(flt(-1.0).copysign(2.0), 1.0); assert_biteq!(Float::INFINITY.copysign(-0.0), Float::NEG_INFINITY); assert_biteq!(Float::NEG_INFINITY.copysign(0.0), Float::INFINITY); } @@ -871,9 +949,9 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert!(Float::INFINITY.rem_euclid(42.0 as Float).is_nan()); - assert_biteq!((42.0 as Float).rem_euclid(Float::INFINITY), 42.0 as Float); - assert!((42.0 as Float).rem_euclid(Float::NAN).is_nan()); + assert!(Float::INFINITY.rem_euclid(42.0).is_nan()); + assert_biteq!(flt(42.0).rem_euclid(Float::INFINITY), 42.0); + assert!(flt(42.0).rem_euclid(Float::NAN).is_nan()); assert!(Float::INFINITY.rem_euclid(Float::INFINITY).is_nan()); assert!(Float::INFINITY.rem_euclid(Float::NAN).is_nan()); assert!(Float::NAN.rem_euclid(Float::INFINITY).is_nan()); @@ -888,8 +966,8 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((42.0 as Float).div_euclid(Float::INFINITY), 0.0); - assert!((42.0 as Float).div_euclid(Float::NAN).is_nan()); + assert_biteq!(flt(42.0).div_euclid(Float::INFINITY), 0.0); + assert!(flt(42.0).div_euclid(Float::NAN).is_nan()); assert!(Float::INFINITY.div_euclid(Float::INFINITY).is_nan()); assert!(Float::INFINITY.div_euclid(Float::NAN).is_nan()); assert!(Float::NAN.div_euclid(Float::INFINITY).is_nan()); @@ -903,18 +981,18 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((1.0 as Float).floor(), 1.0); - assert_biteq!((1.3 as Float).floor(), 1.0); - assert_biteq!((1.5 as Float).floor(), 1.0); - assert_biteq!((1.7 as Float).floor(), 1.0); - assert_biteq!((0.5 as Float).floor(), 0.0); - assert_biteq!((0.0 as Float).floor(), 0.0); - assert_biteq!((-0.0 as Float).floor(), -0.0); - assert_biteq!((-0.5 as Float).floor(), -1.0); - assert_biteq!((-1.0 as Float).floor(), -1.0); - assert_biteq!((-1.3 as Float).floor(), -2.0); - assert_biteq!((-1.5 as Float).floor(), -2.0); - assert_biteq!((-1.7 as Float).floor(), -2.0); + assert_biteq!(flt(1.0).floor(), 1.0); + assert_biteq!(flt(1.3).floor(), 1.0); + assert_biteq!(flt(1.5).floor(), 1.0); + assert_biteq!(flt(1.7).floor(), 1.0); + assert_biteq!(flt(0.5).floor(), 0.0); + assert_biteq!(flt(0.0).floor(), 0.0); + assert_biteq!(flt(-0.0).floor(), -0.0); + assert_biteq!(flt(-0.5).floor(), -1.0); + assert_biteq!(flt(-1.0).floor(), -1.0); + assert_biteq!(flt(-1.3).floor(), -2.0); + assert_biteq!(flt(-1.5).floor(), -2.0); + assert_biteq!(flt(-1.7).floor(), -2.0); assert_biteq!(Float::MAX.floor(), Float::MAX); assert_biteq!(Float::MIN.floor(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.floor(), 0.0); @@ -932,18 +1010,18 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((1.0 as Float).ceil(), 1.0); - assert_biteq!((1.3 as Float).ceil(), 2.0); - assert_biteq!((1.5 as Float).ceil(), 2.0); - assert_biteq!((1.7 as Float).ceil(), 2.0); - assert_biteq!((0.5 as Float).ceil(), 1.0); - assert_biteq!((0.0 as Float).ceil(), 0.0); - assert_biteq!((-0.0 as Float).ceil(), -0.0); - assert_biteq!((-0.5 as Float).ceil(), -0.0); - assert_biteq!((-1.0 as Float).ceil(), -1.0); - assert_biteq!((-1.3 as Float).ceil(), -1.0); - assert_biteq!((-1.5 as Float).ceil(), -1.0); - assert_biteq!((-1.7 as Float).ceil(), -1.0); + assert_biteq!(flt(1.0).ceil(), 1.0); + assert_biteq!(flt(1.3).ceil(), 2.0); + assert_biteq!(flt(1.5).ceil(), 2.0); + assert_biteq!(flt(1.7).ceil(), 2.0); + assert_biteq!(flt(0.5).ceil(), 1.0); + assert_biteq!(flt(0.0).ceil(), 0.0); + assert_biteq!(flt(-0.0).ceil(), -0.0); + assert_biteq!(flt(-0.5).ceil(), -0.0); + assert_biteq!(flt(-1.0).ceil(), -1.0); + assert_biteq!(flt(-1.3).ceil(), -1.0); + assert_biteq!(flt(-1.5).ceil(), -1.0); + assert_biteq!(flt(-1.7).ceil(), -1.0); assert_biteq!(Float::MAX.ceil(), Float::MAX); assert_biteq!(Float::MIN.ceil(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.ceil(), 1.0); @@ -961,19 +1039,19 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((2.5 as Float).round(), 3.0); - assert_biteq!((1.0 as Float).round(), 1.0); - assert_biteq!((1.3 as Float).round(), 1.0); - assert_biteq!((1.5 as Float).round(), 2.0); - assert_biteq!((1.7 as Float).round(), 2.0); - assert_biteq!((0.5 as Float).round(), 1.0); - assert_biteq!((0.0 as Float).round(), 0.0); - assert_biteq!((-0.0 as Float).round(), -0.0); - assert_biteq!((-0.5 as Float).round(), -1.0); - assert_biteq!((-1.0 as Float).round(), -1.0); - assert_biteq!((-1.3 as Float).round(), -1.0); - assert_biteq!((-1.5 as Float).round(), -2.0); - assert_biteq!((-1.7 as Float).round(), -2.0); + assert_biteq!(flt(2.5).round(), 3.0); + assert_biteq!(flt(1.0).round(), 1.0); + assert_biteq!(flt(1.3).round(), 1.0); + assert_biteq!(flt(1.5).round(), 2.0); + assert_biteq!(flt(1.7).round(), 2.0); + assert_biteq!(flt(0.5).round(), 1.0); + assert_biteq!(flt(0.0).round(), 0.0); + assert_biteq!(flt(-0.0).round(), -0.0); + assert_biteq!(flt(-0.5).round(), -1.0); + assert_biteq!(flt(-1.0).round(), -1.0); + assert_biteq!(flt(-1.3).round(), -1.0); + assert_biteq!(flt(-1.5).round(), -2.0); + assert_biteq!(flt(-1.7).round(), -2.0); assert_biteq!(Float::MAX.round(), Float::MAX); assert_biteq!(Float::MIN.round(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.round(), 0.0); @@ -991,19 +1069,19 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((2.5 as Float).round_ties_even(), 2.0); - assert_biteq!((1.0 as Float).round_ties_even(), 1.0); - assert_biteq!((1.3 as Float).round_ties_even(), 1.0); - assert_biteq!((1.5 as Float).round_ties_even(), 2.0); - assert_biteq!((1.7 as Float).round_ties_even(), 2.0); - assert_biteq!((0.5 as Float).round_ties_even(), 0.0); - assert_biteq!((0.0 as Float).round_ties_even(), 0.0); - assert_biteq!((-0.0 as Float).round_ties_even(), -0.0); - assert_biteq!((-0.5 as Float).round_ties_even(), -0.0); - assert_biteq!((-1.0 as Float).round_ties_even(), -1.0); - assert_biteq!((-1.3 as Float).round_ties_even(), -1.0); - assert_biteq!((-1.5 as Float).round_ties_even(), -2.0); - assert_biteq!((-1.7 as Float).round_ties_even(), -2.0); + assert_biteq!(flt(2.5).round_ties_even(), 2.0); + assert_biteq!(flt(1.0).round_ties_even(), 1.0); + assert_biteq!(flt(1.3).round_ties_even(), 1.0); + assert_biteq!(flt(1.5).round_ties_even(), 2.0); + assert_biteq!(flt(1.7).round_ties_even(), 2.0); + assert_biteq!(flt(0.5).round_ties_even(), 0.0); + assert_biteq!(flt(0.0).round_ties_even(), 0.0); + assert_biteq!(flt(-0.0).round_ties_even(), -0.0); + assert_biteq!(flt(-0.5).round_ties_even(), -0.0); + assert_biteq!(flt(-1.0).round_ties_even(), -1.0); + assert_biteq!(flt(-1.3).round_ties_even(), -1.0); + assert_biteq!(flt(-1.5).round_ties_even(), -2.0); + assert_biteq!(flt(-1.7).round_ties_even(), -2.0); assert_biteq!(Float::MAX.round_ties_even(), Float::MAX); assert_biteq!(Float::MIN.round_ties_even(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.round_ties_even(), 0.0); @@ -1021,18 +1099,18 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((1.0 as Float).trunc(), 1.0); - assert_biteq!((1.3 as Float).trunc(), 1.0); - assert_biteq!((1.5 as Float).trunc(), 1.0); - assert_biteq!((1.7 as Float).trunc(), 1.0); - assert_biteq!((0.5 as Float).trunc(), 0.0); - assert_biteq!((0.0 as Float).trunc(), 0.0); - assert_biteq!((-0.0 as Float).trunc(), -0.0); - assert_biteq!((-0.5 as Float).trunc(), -0.0); - assert_biteq!((-1.0 as Float).trunc(), -1.0); - assert_biteq!((-1.3 as Float).trunc(), -1.0); - assert_biteq!((-1.5 as Float).trunc(), -1.0); - assert_biteq!((-1.7 as Float).trunc(), -1.0); + assert_biteq!(flt(1.0).trunc(), 1.0); + assert_biteq!(flt(1.3).trunc(), 1.0); + assert_biteq!(flt(1.5).trunc(), 1.0); + assert_biteq!(flt(1.7).trunc(), 1.0); + assert_biteq!(flt(0.5).trunc(), 0.0); + assert_biteq!(flt(0.0).trunc(), 0.0); + assert_biteq!(flt(-0.0).trunc(), -0.0); + assert_biteq!(flt(-0.5).trunc(), -0.0); + assert_biteq!(flt(-1.0).trunc(), -1.0); + assert_biteq!(flt(-1.3).trunc(), -1.0); + assert_biteq!(flt(-1.5).trunc(), -1.0); + assert_biteq!(flt(-1.7).trunc(), -1.0); assert_biteq!(Float::MAX.trunc(), Float::MAX); assert_biteq!(Float::MIN.trunc(), Float::MIN); assert_biteq!(Float::MIN_POSITIVE.trunc(), 0.0); @@ -1050,18 +1128,18 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128_math))], }, test { - assert_biteq!((1.0 as Float).fract(), 0.0); - assert_approx_eq!((1.3 as Float).fract(), 0.3); // rounding differs between float types - assert_biteq!((1.5 as Float).fract(), 0.5); - assert_approx_eq!((1.7 as Float).fract(), 0.7); - assert_biteq!((0.5 as Float).fract(), 0.5); - assert_biteq!((0.0 as Float).fract(), 0.0); - assert_biteq!((-0.0 as Float).fract(), 0.0); - assert_biteq!((-0.5 as Float).fract(), -0.5); - assert_biteq!((-1.0 as Float).fract(), 0.0); - assert_approx_eq!((-1.3 as Float).fract(), -0.3); // rounding differs between float types - assert_biteq!((-1.5 as Float).fract(), -0.5); - assert_approx_eq!((-1.7 as Float).fract(), -0.7); + assert_biteq!(flt(1.0).fract(), 0.0); + assert_approx_eq!(flt(1.3).fract(), 0.3); // rounding differs between float types + assert_biteq!(flt(1.5).fract(), 0.5); + assert_approx_eq!(flt(1.7).fract(), 0.7); + assert_biteq!(flt(0.5).fract(), 0.5); + assert_biteq!(flt(0.0).fract(), 0.0); + assert_biteq!(flt(-0.0).fract(), 0.0); + assert_biteq!(flt(-0.5).fract(), -0.5); + assert_biteq!(flt(-1.0).fract(), 0.0); + assert_approx_eq!(flt(-1.3).fract(), -0.3); // rounding differs between float types + assert_biteq!(flt(-1.5).fract(), -0.5); + assert_approx_eq!(flt(-1.7).fract(), -0.7); assert_biteq!(Float::MAX.fract(), 0.0); assert_biteq!(Float::MIN.fract(), 0.0); assert_biteq!(Float::MIN_POSITIVE.fract(), Float::MIN_POSITIVE); @@ -1425,10 +1503,10 @@ float_test! { let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; let max: Float = Float::MAX; - assert_biteq!((1.0 as Float).recip(), 1.0); - assert_biteq!((2.0 as Float).recip(), 0.5); - assert_biteq!((-0.4 as Float).recip(), -2.5); - assert_biteq!((0.0 as Float).recip(), inf); + assert_biteq!(flt(1.0).recip(), 1.0); + assert_biteq!(flt(2.0).recip(), 0.5); + assert_biteq!(flt(-0.4).recip(), -2.5); + assert_biteq!(flt(0.0).recip(), inf); assert!(nan.recip().is_nan()); assert_biteq!(inf.recip(), 0.0); assert_biteq!(neg_inf.recip(), -0.0); @@ -1449,15 +1527,314 @@ float_test! { let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; assert_approx_eq!(Float::ONE.powi(1), Float::ONE); - assert_approx_eq!((-3.1 as Float).powi(2), 9.6100000000000005506706202140776519387, Float::POWI_APPROX); - assert_approx_eq!((5.9 as Float).powi(-2), 0.028727377190462507313100483690639638451); - assert_biteq!((8.3 as Float).powi(0), Float::ONE); + assert_approx_eq!(flt(-3.1).powi(2), 9.6100000000000005506706202140776519387, Float::POWI_APPROX); + assert_approx_eq!(flt(5.9).powi(-2), 0.028727377190462507313100483690639638451); + assert_biteq!(flt(8.3).powi(0), Float::ONE); assert!(nan.powi(2).is_nan()); assert_biteq!(inf.powi(3), inf); assert_biteq!(neg_inf.powi(2), inf); } } +float_test! { + name: powf, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_biteq!(flt(1.0).powf(1.0), 1.0); + assert_approx_eq!(flt(3.4).powf(4.5), 246.40818323761892815995637964326426756, Float::POWF_APPROX); + assert_approx_eq!(flt(2.7).powf(-3.2), 0.041652009108526178281070304373500889273, Float::POWF_APPROX); + assert_approx_eq!(flt(-3.1).powf(2.0), 9.6100000000000005506706202140776519387, Float::POWF_APPROX); + assert_approx_eq!(flt(5.9).powf(-2.0), 0.028727377190462507313100483690639638451, Float::POWF_APPROX); + assert_biteq!(flt(8.3).powf(0.0), 1.0); + assert!(nan.powf(2.0).is_nan()); + assert_biteq!(inf.powf(2.0), inf); + assert_biteq!(neg_inf.powf(3.0), neg_inf); + } +} + +float_test! { + name: exp, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_biteq!(1.0, flt(0.0).exp()); + assert_approx_eq!(consts::E, flt(1.0).exp(), Float::EXP_APPROX); + assert_approx_eq!(148.41315910257660342111558004055227962348775, flt(5.0).exp(), Float::EXP_APPROX); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf, inf.exp()); + assert_biteq!(0.0, neg_inf.exp()); + assert!(nan.exp().is_nan()); + } +} + +float_test! { + name: exp2, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_approx_eq!(32.0, flt(5.0).exp2(), Float::EXP_APPROX); + assert_biteq!(1.0, flt(0.0).exp2()); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf, inf.exp2()); + assert_biteq!(0.0, neg_inf.exp2()); + assert!(nan.exp2().is_nan()); + } +} + +float_test! { + name: ln, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(1.0).exp().ln(), 1.0, Float::LN_APPROX); + assert!(nan.ln().is_nan()); + assert_biteq!(inf.ln(), inf); + assert!(neg_inf.ln().is_nan()); + assert!(flt(-2.3).ln().is_nan()); + assert_biteq!(flt(-0.0).ln(), neg_inf); + assert_biteq!(flt(0.0).ln(), neg_inf); + assert_approx_eq!(flt(4.0).ln(), 1.3862943611198906188344642429163531366, Float::LN_APPROX); + } +} + +float_test! { + name: log, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(10.0).log(10.0), 1.0, Float::LOG_APPROX); + assert_approx_eq!(flt(2.3).log(3.5), 0.66485771361478710036766645911922010272, Float::LOG_APPROX); + assert_approx_eq!(flt(1.0).exp().log(flt(1.0).exp()), 1.0, Float::LOG_APPROX); + assert!(flt(1.0).log(1.0).is_nan()); + assert!(flt(1.0).log(-13.9).is_nan()); + assert!(nan.log(2.3).is_nan()); + assert_biteq!(inf.log(10.0), inf); + assert!(neg_inf.log(8.8).is_nan()); + assert!(flt(-2.3).log(0.1).is_nan()); + assert_biteq!(flt(-0.0).log(2.0), neg_inf); + assert_biteq!(flt(0.0).log(7.0), neg_inf); + } +} + +float_test! { + name: log2, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(10.0).log2(), 3.32192809488736234787031942948939017, Float::LOG2_APPROX); + assert_approx_eq!(flt(2.3).log2(), 1.2016338611696504130002982471978765921, Float::LOG2_APPROX); + assert_approx_eq!(flt(1.0).exp().log2(), 1.4426950408889634073599246810018921381, Float::LOG2_APPROX); + assert!(nan.log2().is_nan()); + assert_biteq!(inf.log2(), inf); + assert!(neg_inf.log2().is_nan()); + assert!(flt(-2.3).log2().is_nan()); + assert_biteq!(flt(-0.0).log2(), neg_inf); + assert_biteq!(flt(0.0).log2(), neg_inf); + } +} + +float_test! { + name: log10, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let nan: Float = Float::NAN; + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_approx_eq!(flt(10.0).log10(), 1.0, Float::LOG10_APPROX); + assert_approx_eq!(flt(2.3).log10(), 0.36172783601759284532595218865859309898, Float::LOG10_APPROX); + assert_approx_eq!(flt(1.0).exp().log10(), 0.43429448190325182765112891891660508222, Float::LOG10_APPROX); + assert_biteq!(flt(1.0).log10(), 0.0); + assert!(nan.log10().is_nan()); + assert_biteq!(inf.log10(), inf); + assert!(neg_inf.log10().is_nan()); + assert!(flt(-2.3).log10().is_nan()); + assert_biteq!(flt(-0.0).log10(), neg_inf); + assert_biteq!(flt(0.0).log10(), neg_inf); + } +} + +float_test! { + name: asinh, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_biteq!(flt(0.0).asinh(), 0.0); + assert_biteq!(flt(-0.0).asinh(), -0.0); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf.asinh(), inf); + assert_biteq!(neg_inf.asinh(), neg_inf); + assert!(nan.asinh().is_nan()); + assert!(flt(-0.0).asinh().is_sign_negative()); + + // issue 63271 + assert_approx_eq!(flt(2.0).asinh(), 1.443635475178810342493276740273105, Float::ASINH_APPROX); + assert_approx_eq!(flt(-2.0).asinh(), -1.443635475178810342493276740273105, Float::ASINH_APPROX); + + assert_approx_eq!(flt(-200.0).asinh(), -5.991470797049389, Float::ASINH_APPROX); + + #[allow(overflowing_literals)] + if Float::MAX > flt(66000.0) { + // regression test for the catastrophic cancellation fixed in 72486 + assert_approx_eq!(flt(-67452098.07139316).asinh(), -18.720075426274544393985484294000831757220, Float::ASINH_APPROX); + } + } +} + +float_test! { + name: acosh, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_biteq!(flt(1.0).acosh(), 0.0); + assert!(flt(0.999).acosh().is_nan()); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + let nan: Float = Float::NAN; + assert_biteq!(inf.acosh(), inf); + assert!(neg_inf.acosh().is_nan()); + assert!(nan.acosh().is_nan()); + assert_approx_eq!(flt(2.0).acosh(), 1.31695789692481670862504634730796844, Float::ACOSH_APPROX); + assert_approx_eq!(flt(3.0).acosh(), 1.76274717403908605046521864995958461, Float::ACOSH_APPROX); + + #[allow(overflowing_literals)] + if Float::MAX > flt(66000.0) { + // test for low accuracy from issue 104548 + assert_approx_eq!(flt(60.0), flt(60.0).cosh().acosh(), Float::ACOSH_APPROX); + } + } +} + +float_test! { + name: atanh, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_biteq!(flt(0.0).atanh(), 0.0); + assert_biteq!(flt(-0.0).atanh(), -0.0); + + let inf: Float = Float::INFINITY; + let neg_inf: Float = Float::NEG_INFINITY; + assert_biteq!(flt(1.0).atanh(), inf); + assert_biteq!(flt(-1.0).atanh(), neg_inf); + + let nan: Float = Float::NAN; + assert!(inf.atanh().is_nan()); + assert!(neg_inf.atanh().is_nan()); + assert!(nan.atanh().is_nan()); + + assert_approx_eq!(flt(0.5).atanh(), 0.54930614433405484569762261846126285, Float::ATANH_APPROX); + assert_approx_eq!(flt(-0.5).atanh(), -0.54930614433405484569762261846126285, Float::ATANH_APPROX); + } +} + +float_test! { + name: gamma, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_approx_eq!(flt(1.0).gamma(), 1.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(2.0).gamma(), 1.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(3.0).gamma(), 2.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(4.0).gamma(), 6.0, Float::GAMMA_APPROX); + assert_approx_eq!(flt(5.0).gamma(), 24.0, Float::GAMMA_APPROX_LOOSE); + assert_approx_eq!(flt(0.5).gamma(), consts::PI.sqrt(), Float::GAMMA_APPROX); + assert_approx_eq!(flt(-0.5).gamma(), flt(-2.0) * consts::PI.sqrt(), Float::GAMMA_APPROX_LOOSE); + assert_biteq!(flt(0.0).gamma(), Float::INFINITY); + assert_biteq!(flt(-0.0).gamma(), Float::NEG_INFINITY); + assert!(flt(-1.0).gamma().is_nan()); + assert!(flt(-2.0).gamma().is_nan()); + assert!(Float::NAN.gamma().is_nan()); + assert!(Float::NEG_INFINITY.gamma().is_nan()); + assert_biteq!(Float::INFINITY.gamma(), Float::INFINITY); + + // FIXME: there is a bug in the MinGW gamma implementation that causes this to + // return NaN. https://sourceforge.net/p/mingw-w64/bugs/517/ + if !cfg!(all(target_os = "windows", target_env = "gnu", not(target_abi = "llvm"))) { + assert_biteq!(flt(1760.9).gamma(), Float::INFINITY); + } + + if ::BITS <= 64 { + assert_biteq!(flt(171.71).gamma(), Float::INFINITY); + } + } +} + +float_test! { + name: ln_gamma, + attrs: { + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + assert_approx_eq!(flt(1.0).ln_gamma().0, 0.0, Float::LNGAMMA_APPROX); + assert_eq!(flt(1.0).ln_gamma().1, 1); + assert_approx_eq!(flt(2.0).ln_gamma().0, 0.0, Float::LNGAMMA_APPROX); + assert_eq!(flt(2.0).ln_gamma().1, 1); + assert_approx_eq!(flt(3.0).ln_gamma().0, flt(2.0).ln(), Float::LNGAMMA_APPROX); + assert_eq!(flt(3.0).ln_gamma().1, 1); + assert_approx_eq!(flt(-0.5).ln_gamma().0, (flt(2.0) * consts::PI.sqrt()).ln(), Float::LNGAMMA_APPROX_LOOSE); + assert_eq!(flt(-0.5).ln_gamma().1, -1); + } +} + float_test! { name: to_degrees, attrs: { @@ -1465,17 +1842,17 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128))], }, test { - let pi: Float = Float::PI; + let pi: Float = consts::PI; let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; - assert_biteq!((0.0 as Float).to_degrees(), 0.0); - assert_approx_eq!((-5.8 as Float).to_degrees(), -332.31552117587745090765431723855668471); + assert_biteq!(flt(0.0).to_degrees(), 0.0); + assert_approx_eq!(flt(-5.8).to_degrees(), -332.31552117587745090765431723855668471); assert_approx_eq!(pi.to_degrees(), 180.0, Float::PI_TO_DEGREES_APPROX); assert!(nan.to_degrees().is_nan()); assert_biteq!(inf.to_degrees(), inf); assert_biteq!(neg_inf.to_degrees(), neg_inf); - assert_biteq!((1.0 as Float).to_degrees(), 57.2957795130823208767981548141051703); + assert_biteq!(flt(1.0).to_degrees(), 57.2957795130823208767981548141051703); } } @@ -1486,14 +1863,14 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128))], }, test { - let pi: Float = Float::PI; + let pi: Float = consts::PI; let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; - assert_biteq!((0.0 as Float).to_radians(), 0.0); - assert_approx_eq!((154.6 as Float).to_radians(), 2.6982790235832334267135442069489767804); - assert_approx_eq!((-332.31 as Float).to_radians(), -5.7999036373023566567593094812182763013); - assert_approx_eq!((180.0 as Float).to_radians(), pi, Float::_180_TO_RADIANS_APPROX); + assert_biteq!(flt(0.0).to_radians(), 0.0); + assert_approx_eq!(flt(154.6).to_radians(), 2.6982790235832334267135442069489767804); + assert_approx_eq!(flt(-332.31).to_radians(), -5.7999036373023566567593094812182763013); + assert_approx_eq!(flt(180.0).to_radians(), pi, Float::_180_TO_RADIANS_APPROX); assert!(nan.to_radians().is_nan()); assert_biteq!(inf.to_radians(), inf); assert_biteq!(neg_inf.to_radians(), neg_inf); @@ -1507,8 +1884,8 @@ float_test! { f128: #[cfg(any(miri, target_has_reliable_f128))], }, test { - let a: Float = 123.0; - let b: Float = 456.0; + let a: Float = flt(123.0); + let b: Float = flt(456.0); // Check that individual operations match their primitive counterparts. // @@ -1564,8 +1941,8 @@ float_test! { let nan: Float = Float::NAN; let inf: Float = Float::INFINITY; let neg_inf: Float = Float::NEG_INFINITY; - assert_biteq!(flt(12.3).mul_add(4.5, 6.7), Float::MUL_ADD_RESULT); - assert_biteq!((flt(-12.3)).mul_add(-4.5, -6.7), Float::NEG_MUL_ADD_RESULT); + assert_biteq!(flt(12.3).mul_add(flt(4.5), flt(6.7)), Float::MUL_ADD_RESULT); + assert_biteq!((flt(-12.3)).mul_add(flt(-4.5), flt(-6.7)), Float::NEG_MUL_ADD_RESULT); assert_biteq!(flt(0.0).mul_add(8.9, 1.2), 1.2); assert_biteq!(flt(3.4).mul_add(-0.0, 5.6), 5.6); assert!(nan.mul_add(7.8, 9.0).is_nan()); @@ -1632,6 +2009,93 @@ float_test! { } } +// Test the `float_exact_integer_constants` feature +float_test! { + name: max_exact_integer_constant, + attrs: { + f16: #[cfg(any(miri, target_has_reliable_f16))], + f128: #[cfg(any(miri, target_has_reliable_f128))], + }, + test { + // The maximum integer that converts to a unique floating point + // value. + const MAX_EXACT_INTEGER: ::SInt = Float::MAX_EXACT_INTEGER; + + let max_minus_one = (MAX_EXACT_INTEGER - 1) as Float as ::SInt; + let max_plus_one = (MAX_EXACT_INTEGER + 1) as Float as ::SInt; + let max_plus_two = (MAX_EXACT_INTEGER + 2) as Float as ::SInt; + + // This does an extra round trip back to float for the second operand in + // order to print the results if there is a mismatch + assert_biteq!((MAX_EXACT_INTEGER - 1) as Float, max_minus_one as Float); + assert_biteq!(MAX_EXACT_INTEGER as Float, MAX_EXACT_INTEGER as Float as ::SInt as Float); + assert_biteq!((MAX_EXACT_INTEGER + 1) as Float, max_plus_one as Float); + // The first non-unique conversion, where `max_plus_two` roundtrips to + // `max_plus_one` + assert_biteq!((MAX_EXACT_INTEGER + 1) as Float, (MAX_EXACT_INTEGER + 2) as Float); + assert_biteq!((MAX_EXACT_INTEGER + 2) as Float, max_plus_one as Float); + assert_biteq!((MAX_EXACT_INTEGER + 2) as Float, max_plus_two as Float); + + // Lossless roundtrips, for integers + assert!(MAX_EXACT_INTEGER - 1 == max_minus_one); + assert!(MAX_EXACT_INTEGER == MAX_EXACT_INTEGER as Float as ::SInt); + assert!(MAX_EXACT_INTEGER + 1 == max_plus_one); + // The first non-unique conversion, where `max_plus_two` roundtrips to + // one less than the starting value + assert!(MAX_EXACT_INTEGER + 2 != max_plus_two); + + // max-1 | max+0 | max+1 | max+2 + // After roundtripping, +1 and +2 will equal each other + assert!(max_minus_one != MAX_EXACT_INTEGER); + assert!(MAX_EXACT_INTEGER != max_plus_one); + assert!(max_plus_one == max_plus_two); + } +} + +float_test! { + name: min_exact_integer_constant, + attrs: { + f16: #[cfg(any(miri, target_has_reliable_f16))], + f128: #[cfg(any(miri, target_has_reliable_f128))], + }, + test { + // The minimum integer that converts to a unique floating point + // value. + const MIN_EXACT_INTEGER: ::SInt = Float::MIN_EXACT_INTEGER; + + // Same logic as the `max` test, but we work our way leftward + // across the number line from (min_exact + 1) to (min_exact - 2). + let min_plus_one = (MIN_EXACT_INTEGER + 1) as Float as ::SInt; + let min_minus_one = (MIN_EXACT_INTEGER - 1) as Float as ::SInt; + let min_minus_two = (MIN_EXACT_INTEGER - 2) as Float as ::SInt; + + // This does an extra round trip back to float for the second operand in + // order to print the results if there is a mismatch + assert_biteq!((MIN_EXACT_INTEGER + 1) as Float, min_plus_one as Float); + assert_biteq!(MIN_EXACT_INTEGER as Float, MIN_EXACT_INTEGER as Float as ::SInt as Float); + assert_biteq!((MIN_EXACT_INTEGER - 1) as Float, min_minus_one as Float); + // The first non-unique conversion, which roundtrips to one + // greater than the starting value. + assert_biteq!((MIN_EXACT_INTEGER - 1) as Float, (MIN_EXACT_INTEGER - 2) as Float); + assert_biteq!((MIN_EXACT_INTEGER - 2) as Float, min_minus_one as Float); + assert_biteq!((MIN_EXACT_INTEGER - 2) as Float, min_minus_two as Float); + + // Lossless roundtrips, for integers + assert!(MIN_EXACT_INTEGER + 1 == min_plus_one); + assert!(MIN_EXACT_INTEGER == MIN_EXACT_INTEGER as Float as ::SInt); + assert!(MIN_EXACT_INTEGER - 1 == min_minus_one); + // The first non-unique conversion, which roundtrips to one + // greater than the starting value. + assert!(MIN_EXACT_INTEGER - 2 != min_minus_two); + + // min-2 | min-1 | min | min+1 + // After roundtripping, -2 and -1 will equal each other. + assert!(min_plus_one != MIN_EXACT_INTEGER); + assert!(MIN_EXACT_INTEGER != min_minus_one); + assert!(min_minus_one == min_minus_two); + } +} + // FIXME(f128): Uncomment and adapt these tests once the From<{u64,i64}> impls are added. // float_test! { // name: from_u64_i64, @@ -1650,3 +2114,30 @@ float_test! { // assert_biteq!(Float::from(i64::MAX), 9223372036854775807.0); // } // } + +float_test! { + name: real_consts, + attrs: { + // FIXME(f16_f128): add math tests when available + const: #[cfg(false)], + f16: #[cfg(all(not(miri), target_has_reliable_f16_math))], + f128: #[cfg(all(not(miri), target_has_reliable_f128_math))], + }, + test { + let pi: Float = consts::PI; + assert_approx_eq!(consts::FRAC_PI_2, pi / 2.0); + assert_approx_eq!(consts::FRAC_PI_3, pi / 3.0, Float::APPROX); + assert_approx_eq!(consts::FRAC_PI_4, pi / 4.0); + assert_approx_eq!(consts::FRAC_PI_6, pi / 6.0); + assert_approx_eq!(consts::FRAC_PI_8, pi / 8.0); + assert_approx_eq!(consts::FRAC_1_PI, 1.0 / pi); + assert_approx_eq!(consts::FRAC_2_PI, 2.0 / pi); + assert_approx_eq!(consts::FRAC_2_SQRT_PI, 2.0 / pi.sqrt()); + assert_approx_eq!(consts::SQRT_2, flt(2.0).sqrt()); + assert_approx_eq!(consts::FRAC_1_SQRT_2, 1.0 / flt(2.0).sqrt()); + assert_approx_eq!(consts::LOG2_E, consts::E.log2()); + assert_approx_eq!(consts::LOG10_E, consts::E.log10()); + assert_approx_eq!(consts::LN_2, flt(2.0).ln()); + assert_approx_eq!(consts::LN_10, flt(10.0).ln(), Float::APPROX); + } +} diff --git a/coretests/tests/intrinsics.rs b/coretests/tests/intrinsics.rs index c6d841b8383a8..e562f49b0a2fc 100644 --- a/coretests/tests/intrinsics.rs +++ b/coretests/tests/intrinsics.rs @@ -1,6 +1,7 @@ use core::any::TypeId; -use core::intrinsics::{assume, vtable_for}; +use core::intrinsics::assume; use std::fmt::Debug; +use std::intrinsics::type_id_vtable; use std::option::Option; use std::ptr::DynMetadata; @@ -198,15 +199,17 @@ fn carrying_mul_add_fallback_i128() { } #[test] -fn test_vtable_for() { +fn test_type_id_vtable() { #[derive(Debug)] struct A {} struct B {} - const A_VTABLE: Option> = vtable_for::(); + const A_VTABLE: Option> = + type_id_vtable(TypeId::of::(), TypeId::of::()); assert!(A_VTABLE.is_some()); - const B_VTABLE: Option> = vtable_for::(); + const B_VTABLE: Option> = + type_id_vtable(TypeId::of::(), TypeId::of::()); assert!(B_VTABLE.is_none()); } diff --git a/coretests/tests/iter/adapters/array_chunks.rs b/coretests/tests/iter/adapters/array_chunks.rs index e6e279b14e626..480d3138bdb35 100644 --- a/coretests/tests/iter/adapters/array_chunks.rs +++ b/coretests/tests/iter/adapters/array_chunks.rs @@ -1,4 +1,4 @@ -use core::iter::{self}; +use core::iter; use super::*; diff --git a/coretests/tests/lib.rs b/coretests/tests/lib.rs index d085e4ad1a8fe..7cd946dc9a03f 100644 --- a/coretests/tests/lib.rs +++ b/coretests/tests/lib.rs @@ -1,6 +1,5 @@ // tidy-alphabetical-start #![cfg_attr(target_has_atomic = "128", feature(integer_atomics))] -#![cfg_attr(test, feature(cfg_select))] #![feature(array_ptr_get)] #![feature(array_try_from_fn)] #![feature(array_try_map)] @@ -13,7 +12,6 @@ #![feature(cfg_target_has_reliable_f16_f128)] #![feature(char_internals)] #![feature(char_max_len)] -#![feature(clamp_magnitude)] #![feature(clone_to_uninit)] #![feature(const_array)] #![feature(const_bool)] @@ -35,7 +33,6 @@ #![feature(const_trait_impl)] #![feature(const_unsigned_bigint_helpers)] #![feature(control_flow_ok)] -#![feature(core_float_math)] #![feature(core_intrinsics)] #![feature(core_intrinsics_fallbacks)] #![feature(core_io_borrowed_buf)] @@ -47,7 +44,6 @@ #![feature(drop_guard)] #![feature(duration_constants)] #![feature(duration_constructors)] -#![feature(error_generic_member_access)] #![feature(exact_div)] #![feature(exact_size_is_empty)] #![feature(extend_one)] @@ -55,6 +51,8 @@ #![feature(f16)] #![feature(f128)] #![feature(float_algebraic)] +#![feature(float_bits_const)] +#![feature(float_exact_integer_constants)] #![feature(float_gamma)] #![feature(float_minimum_maximum)] #![feature(flt2dec)] @@ -66,6 +64,7 @@ #![feature(generic_assert_internals)] #![feature(hasher_prefixfree_extras)] #![feature(hashmap_internals)] +#![feature(int_from_ascii)] #![feature(int_lowest_highest_one)] #![feature(int_roundings)] #![feature(ip)] @@ -90,9 +89,9 @@ #![feature(new_range_api)] #![feature(next_index)] #![feature(non_exhaustive_omitted_patterns_lint)] +#![feature(nonzero_from_str_radix)] #![feature(numfmt)] #![feature(one_sided_range)] -#![feature(option_reduce)] #![feature(pattern)] #![feature(pointer_is_aligned_to)] #![feature(portable_simd)] @@ -112,7 +111,6 @@ #![feature(step_trait)] #![feature(str_internals)] #![feature(strict_provenance_lints)] -#![feature(test)] #![feature(trusted_len)] #![feature(trusted_random_access)] #![feature(try_blocks)] @@ -120,6 +118,7 @@ #![feature(try_trait_v2)] #![feature(type_info)] #![feature(uint_bit_width)] +#![feature(uint_carryless_mul)] #![feature(uint_gather_scatter_bits)] #![feature(unsize)] #![feature(unwrap_infallible)] diff --git a/coretests/tests/mem.rs b/coretests/tests/mem.rs index 193d5416b06a7..b95e6e13063f5 100644 --- a/coretests/tests/mem.rs +++ b/coretests/tests/mem.rs @@ -1,3 +1,5 @@ +mod fn_ptr; +mod trait_info_of; mod type_info; use core::mem::*; diff --git a/coretests/tests/mem/fn_ptr.rs b/coretests/tests/mem/fn_ptr.rs new file mode 100644 index 0000000000000..1d50a2552a193 --- /dev/null +++ b/coretests/tests/mem/fn_ptr.rs @@ -0,0 +1,169 @@ +use std::any::TypeId; +use std::mem::type_info::{Abi, FnPtr, Type, TypeKind}; + +const STRING_TY: TypeId = const { TypeId::of::() }; +const U8_TY: TypeId = const { TypeId::of::() }; +const _U8_REF_TY: TypeId = const { TypeId::of::<&u8>() }; +const UNIT_TY: TypeId = const { TypeId::of::<()>() }; + +#[test] +fn test_fn_ptrs() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); +} +#[test] +fn test_ref() { + const { + // references are tricky because the lifetimes give the references different type ids + // so we check the pointees instead + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[ty1, ty2], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + if output != UNIT_TY { + panic!(); + } + let TypeKind::Reference(reference) = ty1.info().kind else { + panic!(); + }; + if reference.pointee != U8_TY { + panic!(); + } + let TypeKind::Reference(reference) = ty2.info().kind else { + panic!(); + }; + if reference.pointee != U8_TY { + panic!(); + } + } +} + +#[test] +fn test_unsafe() { + let TypeKind::FnPtr(FnPtr { + unsafety: true, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); +} +#[test] +fn test_abi() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternC, + inputs: &[], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + + let TypeKind::FnPtr(FnPtr { + unsafety: true, + abi: Abi::Named("system"), + inputs: &[], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); +} + +#[test] +fn test_inputs() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[ty1, ty2], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + assert_eq!(ty1, STRING_TY); + assert_eq!(ty2, U8_TY); + + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[ty1, ty2], + output, + variadic: false, + }) = (const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, UNIT_TY); + assert_eq!(ty1, STRING_TY); + assert_eq!(ty2, U8_TY); +} + +#[test] +fn test_output() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternRust, + inputs: &[], + output, + variadic: false, + }) = (const { Type::of:: u8>().kind }) + else { + panic!(); + }; + assert_eq!(output, U8_TY); +} + +#[test] +fn test_variadic() { + let TypeKind::FnPtr(FnPtr { + unsafety: false, + abi: Abi::ExternC, + inputs: [ty1], + output, + variadic: true, + }) = &(const { Type::of::().kind }) + else { + panic!(); + }; + assert_eq!(output, &UNIT_TY); + assert_eq!(*ty1, U8_TY); +} diff --git a/coretests/tests/mem/trait_info_of.rs b/coretests/tests/mem/trait_info_of.rs new file mode 100644 index 0000000000000..c723a96095815 --- /dev/null +++ b/coretests/tests/mem/trait_info_of.rs @@ -0,0 +1,70 @@ +use std::any::TypeId; +use std::ptr::DynMetadata; + +struct Garlic(i32); +trait Blah { + fn get_truth(&self) -> i32; +} +impl Blah for Garlic { + fn get_truth(&self) -> i32 { + self.0 * 21 + } +} + +#[test] +fn test_implements_trait() { + const { + assert!(TypeId::of::().trait_info_of::().is_some()); + assert!(TypeId::of::().trait_info_of::().is_some()); + assert!(TypeId::of::<*const Box>().trait_info_of::().is_none()); + assert!(TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()).is_none()); + } +} + +#[test] +fn test_dyn_creation() { + let garlic = Garlic(2); + unsafe { + assert_eq!( + std::ptr::from_raw_parts::( + &raw const garlic, + const { TypeId::of::().trait_info_of::() }.unwrap().get_vtable() + ) + .as_ref() + .unwrap() + .get_truth(), + 42 + ); + } + + assert_eq!( + const { + TypeId::of::() + .trait_info_of_trait_type_id(TypeId::of::()) + .unwrap() + }.get_vtable(), + unsafe { + crate::mem::transmute::<_, DynMetadata<*const ()>>( + const { + TypeId::of::().trait_info_of::() + }.unwrap().get_vtable(), + ) + } + ); +} + +#[test] +fn test_incorrect_use() { + assert_eq!( + const { TypeId::of::().trait_info_of_trait_type_id(TypeId::of::()) }, + None + ); +} + +trait DstTrait {} +impl DstTrait for [i32] {} + +#[test] +fn dst_ice() { + assert!(const { TypeId::of::<[i32]>().trait_info_of::() }.is_none()); +} diff --git a/coretests/tests/mem/type_info.rs b/coretests/tests/mem/type_info.rs index 87f2d5dd8289c..2483b4c2aacd7 100644 --- a/coretests/tests/mem/type_info.rs +++ b/coretests/tests/mem/type_info.rs @@ -1,5 +1,8 @@ +#![allow(dead_code)] + use std::any::{Any, TypeId}; -use std::mem::type_info::{Type, TypeKind}; +use std::mem::offset_of; +use std::mem::type_info::{Const, Generic, GenericType, Type, TypeKind}; #[test] fn test_arrays() { @@ -66,6 +69,155 @@ fn test_tuples() { } } +#[test] +fn test_structs() { + use TypeKind::*; + + const { + struct TestStruct { + first: u8, + second: u16, + reference: &'static u16, + } + + let Type { kind: Struct(ty), size, .. } = Type::of::() else { panic!() }; + assert!(size == Some(size_of::())); + assert!(!ty.non_exhaustive); + assert!(ty.fields.len() == 3); + assert!(ty.fields[0].name == "first"); + assert!(ty.fields[0].ty == TypeId::of::()); + assert!(ty.fields[0].offset == offset_of!(TestStruct, first)); + assert!(ty.fields[1].name == "second"); + assert!(ty.fields[1].ty == TypeId::of::()); + assert!(ty.fields[1].offset == offset_of!(TestStruct, second)); + assert!(ty.fields[2].name == "reference"); + assert!(ty.fields[2].ty == TypeId::of::<&'static u16>()); + assert!(ty.fields[2].offset == offset_of!(TestStruct, reference)); + } + + const { + #[non_exhaustive] + struct NonExhaustive { + a: u8, + } + + let Type { kind: Struct(ty), .. } = Type::of::() else { panic!() }; + assert!(ty.non_exhaustive); + } + + const { + struct TupleStruct(u8, u16); + + let Type { kind: Struct(ty), .. } = Type::of::() else { panic!() }; + assert!(ty.fields.len() == 2); + assert!(ty.fields[0].name == "0"); + assert!(ty.fields[0].ty == TypeId::of::()); + assert!(ty.fields[1].name == "1"); + assert!(ty.fields[1].ty == TypeId::of::()); + } + + const { + struct Generics<'a, T, const C: u64> { + a: &'a T, + } + + let Type { kind: Struct(ty), .. } = Type::of::>() else { + panic!() + }; + assert!(ty.fields.len() == 1); + assert!(ty.generics.len() == 3); + + let Generic::Lifetime(_) = ty.generics[0] else { panic!() }; + let Generic::Type(GenericType { ty: generic_ty, .. }) = ty.generics[1] else { panic!() }; + assert!(generic_ty == TypeId::of::()); + let Generic::Const(Const { ty: const_ty, .. }) = ty.generics[2] else { panic!() }; + assert!(const_ty == TypeId::of::()); + } +} + +#[test] +fn test_unions() { + use TypeKind::*; + + const { + union TestUnion { + first: i16, + second: u16, + } + + let Type { kind: Union(ty), size, .. } = Type::of::() else { panic!() }; + assert!(size == Some(size_of::())); + assert!(ty.fields.len() == 2); + assert!(ty.fields[0].name == "first"); + assert!(ty.fields[0].offset == offset_of!(TestUnion, first)); + assert!(ty.fields[1].name == "second"); + assert!(ty.fields[1].offset == offset_of!(TestUnion, second)); + } + + const { + union Generics<'a, T: Copy, const C: u64> { + a: T, + z: &'a (), + } + + let Type { kind: Union(ty), .. } = Type::of::>() else { + panic!() + }; + assert!(ty.fields.len() == 2); + assert!(ty.fields[0].offset == offset_of!(Generics<'static, i32, 1_u64>, a)); + assert!(ty.fields[1].offset == offset_of!(Generics<'static, i32, 1_u64>, z)); + + assert!(ty.generics.len() == 3); + let Generic::Lifetime(_) = ty.generics[0] else { panic!() }; + let Generic::Type(GenericType { ty: generic_ty, .. }) = ty.generics[1] else { panic!() }; + assert!(generic_ty == TypeId::of::()); + let Generic::Const(Const { ty: const_ty, .. }) = ty.generics[2] else { panic!() }; + assert!(const_ty == TypeId::of::()); + } +} + +#[test] +fn test_enums() { + use TypeKind::*; + + const { + enum E { + Some(u32), + None, + #[non_exhaustive] + Foomp { + a: (), + b: &'static str, + }, + } + + let Type { kind: Enum(ty), size, .. } = Type::of::() else { panic!() }; + assert!(size == Some(size_of::())); + assert!(ty.variants.len() == 3); + + assert!(ty.variants[0].name == "Some"); + assert!(!ty.variants[0].non_exhaustive); + assert!(ty.variants[0].fields.len() == 1); + + assert!(ty.variants[1].name == "None"); + assert!(!ty.variants[1].non_exhaustive); + assert!(ty.variants[1].fields.len() == 0); + + assert!(ty.variants[2].name == "Foomp"); + assert!(ty.variants[2].non_exhaustive); + assert!(ty.variants[2].fields.len() == 2); + } + + const { + let Type { kind: Enum(ty), size, .. } = Type::of::>() else { panic!() }; + assert!(size == Some(size_of::>())); + assert!(ty.variants.len() == 2); + assert!(ty.generics.len() == 1); + let Generic::Type(GenericType { ty: generic_ty, .. }) = ty.generics[0] else { panic!() }; + assert!(generic_ty == TypeId::of::()); + } +} + #[test] fn test_primitives() { use TypeKind::*; diff --git a/coretests/tests/nonzero.rs b/coretests/tests/nonzero.rs index c368a2621740b..861e9e05081fc 100644 --- a/coretests/tests/nonzero.rs +++ b/coretests/tests/nonzero.rs @@ -124,6 +124,97 @@ fn test_from_signed_nonzero() { assert_eq!(num, 1i32); } +#[test] +fn test_from_ascii_radix() { + assert_eq!(NonZero::::from_ascii_radix(b"123", 10), Ok(NonZero::new(123).unwrap())); + assert_eq!(NonZero::::from_ascii_radix(b"1001", 2), Ok(NonZero::new(9).unwrap())); + assert_eq!(NonZero::::from_ascii_radix(b"123", 8), Ok(NonZero::new(83).unwrap())); + assert_eq!(NonZero::::from_ascii_radix(b"123", 16), Ok(NonZero::new(291).unwrap())); + assert_eq!(NonZero::::from_ascii_radix(b"ffff", 16), Ok(NonZero::new(65535).unwrap())); + assert_eq!(NonZero::::from_ascii_radix(b"z", 36), Ok(NonZero::new(35).unwrap())); + assert_eq!( + NonZero::::from_ascii_radix(b"0", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::Zero) + ); + assert_eq!( + NonZero::::from_ascii_radix(b"-1", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_ascii_radix(b"-129", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::NegOverflow) + ); + assert_eq!( + NonZero::::from_ascii_radix(b"257", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::PosOverflow) + ); + + assert_eq!( + NonZero::::from_ascii_radix(b"Z", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_ascii_radix(b"_", 2).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); +} + +#[test] +fn test_from_ascii() { + assert_eq!(NonZero::::from_ascii(b"123"), Ok(NonZero::new(123).unwrap())); + assert_eq!( + NonZero::::from_ascii(b"0").err().map(|e| e.kind().clone()), + Some(IntErrorKind::Zero) + ); + assert_eq!( + NonZero::::from_ascii(b"-1").err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_ascii(b"-129").err().map(|e| e.kind().clone()), + Some(IntErrorKind::NegOverflow) + ); + assert_eq!( + NonZero::::from_ascii(b"257").err().map(|e| e.kind().clone()), + Some(IntErrorKind::PosOverflow) + ); +} + +#[test] +fn test_from_str_radix() { + assert_eq!(NonZero::::from_str_radix("123", 10), Ok(NonZero::new(123).unwrap())); + assert_eq!(NonZero::::from_str_radix("1001", 2), Ok(NonZero::new(9).unwrap())); + assert_eq!(NonZero::::from_str_radix("123", 8), Ok(NonZero::new(83).unwrap())); + assert_eq!(NonZero::::from_str_radix("123", 16), Ok(NonZero::new(291).unwrap())); + assert_eq!(NonZero::::from_str_radix("ffff", 16), Ok(NonZero::new(65535).unwrap())); + assert_eq!(NonZero::::from_str_radix("z", 36), Ok(NonZero::new(35).unwrap())); + assert_eq!( + NonZero::::from_str_radix("0", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::Zero) + ); + assert_eq!( + NonZero::::from_str_radix("-1", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_str_radix("-129", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::NegOverflow) + ); + assert_eq!( + NonZero::::from_str_radix("257", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::PosOverflow) + ); + + assert_eq!( + NonZero::::from_str_radix("Z", 10).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); + assert_eq!( + NonZero::::from_str_radix("_", 2).err().map(|e| e.kind().clone()), + Some(IntErrorKind::InvalidDigit) + ); +} + #[test] fn test_from_str() { assert_eq!("123".parse::>(), Ok(NonZero::new(123).unwrap())); diff --git a/coretests/tests/num/carryless_mul.rs b/coretests/tests/num/carryless_mul.rs new file mode 100644 index 0000000000000..5d4690beaedea --- /dev/null +++ b/coretests/tests/num/carryless_mul.rs @@ -0,0 +1,254 @@ +//! Tests the `Unsigned::{carryless_mul, widening_carryless_mul, carrying_carryless_mul}` methods. + +#[test] +fn carryless_mul_u128() { + assert_eq_const_safe!(u128: ::carryless_mul(0, 0), 0); + assert_eq_const_safe!(u128: ::carryless_mul(1, 1), 1); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x0123456789ABCDEF_FEDCBA9876543210, + 1u128 << 64, + ), + 0xFEDCBA9876543210_0000000000000000 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x0123456789ABCDEF_FEDCBA9876543210, + (1u128 << 64) | 1, + ), + 0xFFFFFFFFFFFFFFFF_FEDCBA9876543210 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x0123456789ABCDEF_FEDCBA9876543211, + 1u128 << 127, + ), + 0x8000000000000000_0000000000000000 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0xAAAAAAAAAAAAAAAA_AAAAAAAAAAAAAAAA, + 0x5555555555555555_5555555555555555, + ), + 0x2222222222222222_2222222222222222 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + (1 << 127) | (1 << 64) | 1, + (1 << 63) | 1 + ), + (1 << 64) | (1 << 63) | 1 + ); + + assert_eq_const_safe!( + u128: ::carryless_mul( + 0x8000000000000000_0000000000000001, + 0x7FFFFFFFFFFFFFFF_FFFFFFFFFFFFFFFF, + ), + 0xFFFFFFFFFFFFFFFF_FFFFFFFFFFFFFFFF + ); +} + +#[test] +fn carryless_mul_u64() { + assert_eq_const_safe!(u64: ::carryless_mul(0, 0), 0); + assert_eq_const_safe!(u64: ::carryless_mul(1, 1), 1); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x0123_4567_89AB_CDEF, + 1u64 << 32, + ), + 0x89AB_CDEF_0000_0000 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x0123_4567_89AB_CDEF, + (1u64 << 32) | 1, + ), + 0x8888_8888_89AB_CDEF + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x0123_4567_89AB_CDEF, + 1u64 << 63, + ), + 0x8000_0000_0000_0000 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0xAAAA_AAAA_AAAA_AAAA, + 0x5555_5555_5555_5555, + ), + 0x2222_2222_2222_2222 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + (1u64 << 63) | (1u64 << 32) | 1, + (1u64 << 31) | 1, + ), + (1u64 << 32) | (1u64 << 31) | 1 + ); + + assert_eq_const_safe!( + u64: ::carryless_mul( + 0x8000_0000_0000_0001, + 0x7FFF_FFFF_FFFF_FFFF, + ), + 0xFFFF_FFFF_FFFF_FFFF + ); +} + +#[test] +fn carryless_mul_u32() { + assert_eq_const_safe!( + u32: ::carryless_mul(0x0123_4567, 1u32 << 16), + 0x4567_0000 + ); + + assert_eq_const_safe!( + u32: ::carryless_mul(0xAAAA_AAAA, 0x5555_5555), + 0x2222_2222 + ); +} + +#[test] +fn carryless_mul_u16() { + assert_eq_const_safe!( + u16: ::carryless_mul(0x0123, 1u16 << 8), + 0x2300 + ); + + assert_eq_const_safe!( + u16: ::carryless_mul(0xAAAA, 0x5555), + 0x2222 + ); +} + +#[test] +fn carryless_mul_u8() { + assert_eq_const_safe!( + u8: ::carryless_mul(0x01, 1u8 << 4), + 0x10 + ); + + assert_eq_const_safe!( + u8: ::carryless_mul(0xAA, 0x55), + 0x22 + ); +} + +#[test] +fn widening_carryless_mul() { + assert_eq_const_safe!( + u16: ::widening_carryless_mul(0xEFu8, 1u8 << 7), + 0x7780u16 + ); + assert_eq_const_safe!( + u16: ::widening_carryless_mul(0xEFu8, (1u8 << 7) | 1), + 0x776Fu16 + ); + + assert_eq_const_safe!( + u32: ::widening_carryless_mul(0xBEEFu16, 1u16 << 15), + 0x5F77_8000u32 + ); + assert_eq_const_safe!( + u32: ::widening_carryless_mul(0xBEEFu16, (1u16 << 15) | 1), + 0x5F77_3EEFu32 + ); + + assert_eq_const_safe!( + u64: ::widening_carryless_mul(0xDEAD_BEEFu32, 1u32 << 31), + 0x6F56_DF77_8000_0000u64 + ); + assert_eq_const_safe!( + u64: ::widening_carryless_mul(0xDEAD_BEEFu32, (1u32 << 31) | 1), + 0x6F56_DF77_5EAD_BEEFu64 + ); + + assert_eq_const_safe!( + u128: ::widening_carryless_mul(0xDEAD_BEEF_FACE_FEEDu64, 1u64 << 63), + 147995377545877439359040026616086396928 + + ); + assert_eq_const_safe!( + u128: ::widening_carryless_mul(0xDEAD_BEEF_FACE_FEEDu64, (1u64 << 63) | 1), + 147995377545877439356638973527682121453 + ); +} + +#[test] +fn carrying_carryless_mul() { + assert_eq_const_safe!( + (u8, u8): ::carrying_carryless_mul(0xEFu8, 1u8 << 7, 0), + (0x80u8, 0x77u8) + ); + assert_eq_const_safe!( + (u8, u8): ::carrying_carryless_mul(0xEFu8, (1u8 << 7) | 1, 0xEF), + (0x80u8, 0x77u8) + ); + + assert_eq_const_safe!( + (u16, u16): ::carrying_carryless_mul(0xBEEFu16, 1u16 << 15, 0), + (0x8000u16, 0x5F77u16) + ); + assert_eq_const_safe!( + (u16, u16): ::carrying_carryless_mul(0xBEEFu16, (1u16 << 15) | 1, 0xBEEF), + (0x8000u16, 0x5F77u16) + ); + + assert_eq_const_safe!( + (u32, u32): ::carrying_carryless_mul(0xDEAD_BEEFu32, 1u32 << 31, 0), + (0x8000_0000u32, 0x6F56_DF77u32) + ); + assert_eq_const_safe!( + (u32, u32): ::carrying_carryless_mul(0xDEAD_BEEFu32, (1u32 << 31) | 1, 0xDEAD_BEEF), + (0x8000_0000u32, 0x6F56_DF77u32) + ); + + assert_eq_const_safe!( + (u64, u64): ::carrying_carryless_mul(0xDEAD_BEEF_FACE_FEEDu64, 1u64 << 63, 0), + (9223372036854775808, 8022845492652638070) + ); + assert_eq_const_safe!( + (u64, u64): ::carrying_carryless_mul( + 0xDEAD_BEEF_FACE_FEEDu64, + (1u64 << 63) | 1, + 0xDEAD_BEEF_FACE_FEED, + ), + (9223372036854775808, 8022845492652638070) + ); + + assert_eq_const_safe!( + (u128, u128): ::carrying_carryless_mul( + 0xDEAD_BEEF_FACE_FEED_0123_4567_89AB_CDEFu128, + 1u128 << 127, + 0, + ), + ( + 0x8000_0000_0000_0000_0000_0000_0000_0000u128, + 147995377545877439359081019380694640375, + ) + ); + assert_eq_const_safe!( + (u128, u128): ::carrying_carryless_mul( + 0xDEAD_BEEF_FACE_FEED_0123_4567_89AB_CDEFu128, + (1u128 << 127) | 1, + 0xDEAD_BEEF_FACE_FEED_0123_4567_89AB_CDEF, + ), + ( + 0x8000_0000_0000_0000_0000_0000_0000_0000u128, + 147995377545877439359081019380694640375, + ) + ); +} diff --git a/coretests/tests/num/mod.rs b/coretests/tests/num/mod.rs index 913f766ec1683..73b0e2333feee 100644 --- a/coretests/tests/num/mod.rs +++ b/coretests/tests/num/mod.rs @@ -22,6 +22,7 @@ mod u64; mod u8; mod bignum; +mod carryless_mul; mod const_from; mod dec2flt; mod float_iter_sum_identity; diff --git a/coretests/tests/num/uint_macros.rs b/coretests/tests/num/uint_macros.rs index 7c4fb22599c03..240c66fd5c715 100644 --- a/coretests/tests/num/uint_macros.rs +++ b/coretests/tests/num/uint_macros.rs @@ -117,6 +117,13 @@ macro_rules! uint_module { assert_eq_const_safe!($T: <$T>::funnel_shr(_1, _1, 4), <$T>::rotate_right(_1, 4)); } + fn test_carryless_mul() { + assert_eq_const_safe!($T: <$T>::carryless_mul(0, 0), 0); + assert_eq_const_safe!($T: <$T>::carryless_mul(1, 1), 1); + + assert_eq_const_safe!($T: <$T>::carryless_mul(0b0100, 2), 0b1000); + } + fn test_swap_bytes() { assert_eq_const_safe!($T: A.swap_bytes().swap_bytes(), A); assert_eq_const_safe!($T: B.swap_bytes().swap_bytes(), B); diff --git a/panic_unwind/src/lib.rs b/panic_unwind/src/lib.rs index 1be19913f260f..fc0a627d293f3 100644 --- a/panic_unwind/src/lib.rs +++ b/panic_unwind/src/lib.rs @@ -14,10 +14,9 @@ #![no_std] #![unstable(feature = "panic_unwind", issue = "32837")] #![doc(issue_tracker_base_url = "https://github.com/rust-lang/rust/issues/")] +#![cfg_attr(all(target_os = "emscripten", not(emscripten_wasm_eh)), feature(lang_items))] #![feature(cfg_emscripten_wasm_eh)] -#![feature(cfg_select)] #![feature(core_intrinsics)] -#![feature(lang_items)] #![feature(panic_unwind)] #![feature(staged_api)] #![feature(std_internals)] @@ -25,6 +24,7 @@ #![panic_runtime] #![feature(panic_runtime)] #![allow(internal_features)] +#![allow(unused_features)] #![warn(unreachable_pub)] #![deny(unsafe_op_in_unsafe_fn)] diff --git a/proc_macro/src/bridge/client.rs b/proc_macro/src/bridge/client.rs index 8f4a79b389f62..696cd4ee3d887 100644 --- a/proc_macro/src/bridge/client.rs +++ b/proc_macro/src/bridge/client.rs @@ -98,7 +98,7 @@ pub(crate) use super::symbol::Symbol; macro_rules! define_client_side { ( - $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)* + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* ) => { impl Methods { $(pub(crate) fn $method($($arg: $arg_ty),*) $(-> $ret_ty)? { @@ -121,7 +121,7 @@ macro_rules! define_client_side { } } } -with_api!(self, define_client_side); +with_api!(define_client_side, TokenStream, Span, Symbol); struct Bridge<'a> { /// Reusable buffer (only `clear`-ed, never shrunk), primarily @@ -129,7 +129,7 @@ struct Bridge<'a> { cached_buffer: Buffer, /// Server-side function that the client uses to make requests. - dispatch: closure::Closure<'a, Buffer, Buffer>, + dispatch: closure::Closure<'a>, /// Provided globals for this macro expansion. globals: ExpnGlobals, diff --git a/proc_macro/src/bridge/closure.rs b/proc_macro/src/bridge/closure.rs index e5133907854b2..88c4dd6630b15 100644 --- a/proc_macro/src/bridge/closure.rs +++ b/proc_macro/src/bridge/closure.rs @@ -1,10 +1,12 @@ -//! Closure type (equivalent to `&mut dyn FnMut(A) -> R`) that's `repr(C)`. +//! Closure type (equivalent to `&mut dyn FnMut(Buffer) -> Buffer`) that's `repr(C)`. use std::marker::PhantomData; +use super::Buffer; + #[repr(C)] -pub(super) struct Closure<'a, A, R> { - call: unsafe extern "C" fn(*mut Env, A) -> R, +pub(super) struct Closure<'a> { + call: extern "C" fn(*mut Env, Buffer) -> Buffer, env: *mut Env, // Prevent Send and Sync impls. // @@ -14,17 +16,17 @@ pub(super) struct Closure<'a, A, R> { struct Env; -impl<'a, A, R, F: FnMut(A) -> R> From<&'a mut F> for Closure<'a, A, R> { +impl<'a, F: FnMut(Buffer) -> Buffer> From<&'a mut F> for Closure<'a> { fn from(f: &'a mut F) -> Self { - unsafe extern "C" fn call R>(env: *mut Env, arg: A) -> R { + extern "C" fn call Buffer>(env: *mut Env, arg: Buffer) -> Buffer { unsafe { (*(env as *mut _ as *mut F))(arg) } } - Closure { call: call::, env: f as *mut _ as *mut Env, _marker: PhantomData } + Closure { call: call::, env: f as *mut _ as *mut Env, _marker: PhantomData } } } -impl<'a, A, R> Closure<'a, A, R> { - pub(super) fn call(&mut self, arg: A) -> R { - unsafe { (self.call)(self.env, arg) } +impl<'a> Closure<'a> { + pub(super) fn call(&mut self, arg: Buffer) -> Buffer { + (self.call)(self.env, arg) } } diff --git a/proc_macro/src/bridge/mod.rs b/proc_macro/src/bridge/mod.rs index 244ab7d81b022..72f4e2dcdd7c2 100644 --- a/proc_macro/src/bridge/mod.rs +++ b/proc_macro/src/bridge/mod.rs @@ -18,71 +18,67 @@ use crate::{Delimiter, Level}; /// Higher-order macro describing the server RPC API, allowing automatic /// generation of type-safe Rust APIs, both client-side and server-side. /// -/// `with_api!(MySelf, my_macro)` expands to: +/// `with_api!(my_macro, MyTokenStream, MySpan, MySymbol)` expands to: /// ```rust,ignore (pseudo-code) /// my_macro! { -/// fn lit_character(ch: char) -> MySelf::Literal; -/// fn lit_span(lit: &MySelf::Literal) -> MySelf::Span; -/// fn lit_set_span(lit: &mut MySelf::Literal, span: MySelf::Span); +/// fn ts_clone(stream: &MyTokenStream) -> MyTokenStream; +/// fn span_debug(span: &MySpan) -> String; /// // ... /// } /// ``` /// -/// The first argument serves to customize the argument/return types, -/// to enable several different usecases: -/// -/// If `MySelf` is just `Self`, then the types are only valid inside -/// a trait or a trait impl, where the trait has associated types -/// for each of the API types. If non-associated types are desired, -/// a module name (`self` in practice) can be used instead of `Self`. +/// The second (`TokenStream`), third (`Span`) and fourth (`Symbol`) +/// argument serve to customize the argument/return types that need +/// special handling, to enable several different representations of +/// these types. macro_rules! with_api { - ($S:ident, $m:ident) => { + ($m:ident, $TokenStream: path, $Span: path, $Symbol: path) => { $m! { fn injected_env_var(var: &str) -> Option; fn track_env_var(var: &str, value: Option<&str>); fn track_path(path: &str); - fn literal_from_str(s: &str) -> Result, ()>; - fn emit_diagnostic(diagnostic: Diagnostic<$S::Span>); - - fn ts_drop(stream: $S::TokenStream); - fn ts_clone(stream: &$S::TokenStream) -> $S::TokenStream; - fn ts_is_empty(stream: &$S::TokenStream) -> bool; - fn ts_expand_expr(stream: &$S::TokenStream) -> Result<$S::TokenStream, ()>; - fn ts_from_str(src: &str) -> $S::TokenStream; - fn ts_to_string(stream: &$S::TokenStream) -> String; + fn literal_from_str(s: &str) -> Result, String>; + fn emit_diagnostic(diagnostic: Diagnostic<$Span>); + + fn ts_drop(stream: $TokenStream); + fn ts_clone(stream: &$TokenStream) -> $TokenStream; + fn ts_is_empty(stream: &$TokenStream) -> bool; + fn ts_expand_expr(stream: &$TokenStream) -> Result<$TokenStream, ()>; + fn ts_from_str(src: &str) -> Result<$TokenStream, String>; + fn ts_to_string(stream: &$TokenStream) -> String; fn ts_from_token_tree( - tree: TokenTree<$S::TokenStream, $S::Span, $S::Symbol>, - ) -> $S::TokenStream; + tree: TokenTree<$TokenStream, $Span, $Symbol>, + ) -> $TokenStream; fn ts_concat_trees( - base: Option<$S::TokenStream>, - trees: Vec>, - ) -> $S::TokenStream; + base: Option<$TokenStream>, + trees: Vec>, + ) -> $TokenStream; fn ts_concat_streams( - base: Option<$S::TokenStream>, - streams: Vec<$S::TokenStream>, - ) -> $S::TokenStream; + base: Option<$TokenStream>, + streams: Vec<$TokenStream>, + ) -> $TokenStream; fn ts_into_trees( - stream: $S::TokenStream - ) -> Vec>; - - fn span_debug(span: $S::Span) -> String; - fn span_parent(span: $S::Span) -> Option<$S::Span>; - fn span_source(span: $S::Span) -> $S::Span; - fn span_byte_range(span: $S::Span) -> Range; - fn span_start(span: $S::Span) -> $S::Span; - fn span_end(span: $S::Span) -> $S::Span; - fn span_line(span: $S::Span) -> usize; - fn span_column(span: $S::Span) -> usize; - fn span_file(span: $S::Span) -> String; - fn span_local_file(span: $S::Span) -> Option; - fn span_join(span: $S::Span, other: $S::Span) -> Option<$S::Span>; - fn span_subspan(span: $S::Span, start: Bound, end: Bound) -> Option<$S::Span>; - fn span_resolved_at(span: $S::Span, at: $S::Span) -> $S::Span; - fn span_source_text(span: $S::Span) -> Option; - fn span_save_span(span: $S::Span) -> usize; - fn span_recover_proc_macro_span(id: usize) -> $S::Span; - - fn symbol_normalize_and_validate_ident(string: &str) -> Result<$S::Symbol, ()>; + stream: $TokenStream + ) -> Vec>; + + fn span_debug(span: $Span) -> String; + fn span_parent(span: $Span) -> Option<$Span>; + fn span_source(span: $Span) -> $Span; + fn span_byte_range(span: $Span) -> Range; + fn span_start(span: $Span) -> $Span; + fn span_end(span: $Span) -> $Span; + fn span_line(span: $Span) -> usize; + fn span_column(span: $Span) -> usize; + fn span_file(span: $Span) -> String; + fn span_local_file(span: $Span) -> Option; + fn span_join(span: $Span, other: $Span) -> Option<$Span>; + fn span_subspan(span: $Span, start: Bound, end: Bound) -> Option<$Span>; + fn span_resolved_at(span: $Span, at: $Span) -> $Span; + fn span_source_text(span: $Span) -> Option; + fn span_save_span(span: $Span) -> usize; + fn span_recover_proc_macro_span(id: usize) -> $Span; + + fn symbol_normalize_and_validate_ident(string: &str) -> Result<$Symbol, ()>; } }; } @@ -126,7 +122,7 @@ pub struct BridgeConfig<'a> { input: Buffer, /// Server-side function that the client uses to make requests. - dispatch: closure::Closure<'a, Buffer, Buffer>, + dispatch: closure::Closure<'a>, /// If 'true', always invoke the default panic hook force_show_panics: bool, @@ -137,7 +133,7 @@ impl !Sync for BridgeConfig<'_> {} macro_rules! declare_tags { ( - $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)* + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* ) => { #[allow(non_camel_case_types)] pub(super) enum ApiTags { @@ -146,7 +142,7 @@ macro_rules! declare_tags { rpc_encode_decode!(enum ApiTags { $($method),* }); } } -with_api!(self, declare_tags); +with_api!(declare_tags, __, __, __); /// Helper to wrap associated types to allow trait impl dispatch. /// That is, normally a pair of impls for `T::Foo` and `T::Bar` @@ -173,7 +169,7 @@ impl Mark for Marked { self.value } } -impl<'a, T, M> Mark for &'a Marked { +impl<'a, T> Mark for &'a Marked { type Unmarked = &'a T; fn mark(_: Self::Unmarked) -> Self { unreachable!() @@ -220,6 +216,8 @@ mark_noop! { Delimiter, LitKind, Level, + Bound, + Range, } rpc_encode_decode!( @@ -318,7 +316,7 @@ macro_rules! compound_traits { }; } -compound_traits!( +rpc_encode_decode!( enum Bound { Included(x), Excluded(x), @@ -390,7 +388,7 @@ pub struct Literal { pub span: Span, } -compound_traits!(struct Literal { kind, symbol, suffix, span }); +compound_traits!(struct Literal { kind, symbol, suffix, span }); #[derive(Clone)] pub enum TokenTree { @@ -434,6 +432,6 @@ compound_traits!( struct ExpnGlobals { def_site, call_site, mixed_site } ); -compound_traits!( +rpc_encode_decode!( struct Range { start, end } ); diff --git a/proc_macro/src/bridge/rpc.rs b/proc_macro/src/bridge/rpc.rs index 63329c8c02601..7fee8654bc788 100644 --- a/proc_macro/src/bridge/rpc.rs +++ b/proc_macro/src/bridge/rpc.rs @@ -52,45 +52,37 @@ macro_rules! rpc_encode_decode { } }; (enum $name:ident $(<$($T:ident),+>)? { $($variant:ident $(($field:ident))*),* $(,)? }) => { - impl),+)?> Encode for $name $(<$($T),+>)? { - fn encode(self, w: &mut Buffer, s: &mut S) { - // HACK(eddyb): `Tag` enum duplicated between the - // two impls as there's no other place to stash it. - #[allow(non_camel_case_types)] - #[repr(u8)] - enum Tag { $($variant),* } - - match self { - $($name::$variant $(($field))* => { - (Tag::$variant as u8).encode(w, s); - $($field.encode(w, s);)* - })* + #[allow(non_upper_case_globals, non_camel_case_types)] + const _: () = { + #[repr(u8)] enum Tag { $($variant),* } + + $(const $variant: u8 = Tag::$variant as u8;)* + + impl),+)?> Encode for $name $(<$($T),+>)? { + fn encode(self, w: &mut Buffer, s: &mut S) { + match self { + $($name::$variant $(($field))* => { + $variant.encode(w, s); + $($field.encode(w, s);)* + })* + } } } - } - impl<'a, S, $($($T: for<'s> Decode<'a, 's, S>),+)?> Decode<'a, '_, S> - for $name $(<$($T),+>)? - { - fn decode(r: &mut &'a [u8], s: &mut S) -> Self { - // HACK(eddyb): `Tag` enum duplicated between the - // two impls as there's no other place to stash it. - #[allow(non_upper_case_globals, non_camel_case_types)] - mod tag { - #[repr(u8)] enum Tag { $($variant),* } - - $(pub(crate) const $variant: u8 = Tag::$variant as u8;)* - } - - match u8::decode(r, s) { - $(tag::$variant => { - $(let $field = Decode::decode(r, s);)* - $name::$variant $(($field))* - })* - _ => unreachable!(), + impl<'a, S, $($($T: for<'s> Decode<'a, 's, S>),+)?> Decode<'a, '_, S> + for $name $(<$($T),+>)? + { + fn decode(r: &mut &'a [u8], s: &mut S) -> Self { + match u8::decode(r, s) { + $($variant => { + $(let $field = Decode::decode(r, s);)* + $name::$variant $(($field))* + })* + _ => unreachable!(), + } } } - } + }; } } diff --git a/proc_macro/src/bridge/selfless_reify.rs b/proc_macro/src/bridge/selfless_reify.rs index a53550e0b9e0c..1a9951af8c9f1 100644 --- a/proc_macro/src/bridge/selfless_reify.rs +++ b/proc_macro/src/bridge/selfless_reify.rs @@ -38,47 +38,27 @@ use std::mem; -// FIXME(eddyb) this could be `trait` impls except for the `const fn` requirement. -macro_rules! define_reify_functions { - ($( - fn $name:ident $(<$($param:ident),*>)? - for $(extern $abi:tt)? fn($($arg:ident: $arg_ty:ty),*) -> $ret_ty:ty; - )+) => { - $(pub(super) const fn $name< - $($($param,)*)? - F: Fn($($arg_ty),*) -> $ret_ty + Copy - >(f: F) -> $(extern $abi)? fn($($arg_ty),*) -> $ret_ty { - // FIXME(eddyb) describe the `F` type (e.g. via `type_name::`) once panic - // formatting becomes possible in `const fn`. - const { assert!(size_of::() == 0, "selfless_reify: closure must be zero-sized"); } - - $(extern $abi)? fn wrapper< - $($($param,)*)? - F: Fn($($arg_ty),*) -> $ret_ty + Copy - >($($arg: $arg_ty),*) -> $ret_ty { - let f = unsafe { - // SAFETY: `F` satisfies all criteria for "out of thin air" - // reconstructability (see module-level doc comment). - mem::MaybeUninit::::uninit().assume_init() - }; - f($($arg),*) - } - let _f_proof = f; - wrapper::< - $($($param,)*)? - F - > - })+ +pub(super) const fn reify_to_extern_c_fn_hrt_bridge< + R, + F: Fn(super::BridgeConfig<'_>) -> R + Copy, +>( + f: F, +) -> extern "C" fn(super::BridgeConfig<'_>) -> R { + // FIXME(eddyb) describe the `F` type (e.g. via `type_name::`) once panic + // formatting becomes possible in `const fn`. + const { + assert!(size_of::() == 0, "selfless_reify: closure must be zero-sized"); } -} - -define_reify_functions! { - fn _reify_to_extern_c_fn_unary for extern "C" fn(arg: A) -> R; - - // HACK(eddyb) this abstraction is used with `for<'a> fn(BridgeConfig<'a>) - // -> T` but that doesn't work with just `reify_to_extern_c_fn_unary` - // because of the `fn` pointer type being "higher-ranked" (i.e. the - // `for<'a>` binder). - // FIXME(eddyb) try to remove the lifetime from `BridgeConfig`, that'd help. - fn reify_to_extern_c_fn_hrt_bridge for extern "C" fn(bridge: super::BridgeConfig<'_>) -> R; + extern "C" fn wrapper) -> R + Copy>( + bridge: super::BridgeConfig<'_>, + ) -> R { + let f = unsafe { + // SAFETY: `F` satisfies all criteria for "out of thin air" + // reconstructability (see module-level doc comment). + mem::conjure_zst::() + }; + f(bridge) + } + let _f_proof = f; + wrapper:: } diff --git a/proc_macro/src/bridge/server.rs b/proc_macro/src/bridge/server.rs index 073ddb554994c..1151798fccf40 100644 --- a/proc_macro/src/bridge/server.rs +++ b/proc_macro/src/bridge/server.rs @@ -1,7 +1,7 @@ //! Server-side traits. use std::cell::Cell; -use std::marker::PhantomData; +use std::sync::mpsc; use super::*; @@ -53,17 +53,12 @@ impl Decode<'_, '_, HandleStore> for MarkedSpan { } } -struct Dispatcher { - handle_store: HandleStore, - server: S, -} - -macro_rules! define_server_dispatcher_impl { +macro_rules! define_server { ( - $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)* + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* ) => { pub trait Server { - type TokenStream: 'static + Clone; + type TokenStream: 'static + Clone + Default; type Span: 'static + Copy + Eq + Hash; type Symbol: 'static; @@ -77,22 +72,21 @@ macro_rules! define_server_dispatcher_impl { $(fn $method(&mut self, $($arg: $arg_ty),*) $(-> $ret_ty)?;)* } + } +} +with_api!(define_server, Self::TokenStream, Self::Span, Self::Symbol); - // FIXME(eddyb) `pub` only for `ExecutionStrategy` below. - pub trait DispatcherTrait { - // HACK(eddyb) these are here to allow `Self::$name` to work below. - type TokenStream; - type Span; - type Symbol; - - fn dispatch(&mut self, buf: Buffer) -> Buffer; - } - - impl DispatcherTrait for Dispatcher { - type TokenStream = MarkedTokenStream; - type Span = MarkedSpan; - type Symbol = MarkedSymbol; +// FIXME(eddyb) `pub` only for `ExecutionStrategy` below. +pub struct Dispatcher { + handle_store: HandleStore, + server: S, +} +macro_rules! define_dispatcher { + ( + $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)?;)* + ) => { + impl Dispatcher { fn dispatch(&mut self, mut buf: Buffer) -> Buffer { let Dispatcher { handle_store, server } = self; @@ -102,9 +96,7 @@ macro_rules! define_server_dispatcher_impl { let mut call_method = || { $(let $arg = <$arg_ty>::decode(&mut reader, handle_store).unmark();)* let r = server.$method($($arg),*); - $( - let r: $ret_ty = Mark::mark(r); - )* + $(let r: $ret_ty = Mark::mark(r);)? r }; // HACK(eddyb) don't use `panic::catch_unwind` in a panic. @@ -127,12 +119,15 @@ macro_rules! define_server_dispatcher_impl { } } } -with_api!(Self, define_server_dispatcher_impl); +with_api!(define_dispatcher, MarkedTokenStream, MarkedSpan, MarkedSymbol); +// This trait is currently only implemented and used once, inside of this crate. +// We keep it public to allow implementing more complex execution strategies in +// the future, such as wasm proc-macros. pub trait ExecutionStrategy { fn run_bridge_and_client( &self, - dispatcher: &mut impl DispatcherTrait, + dispatcher: &mut Dispatcher, input: Buffer, run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, force_show_panics: bool, @@ -171,110 +166,78 @@ impl Drop for RunningSameThreadGuard { } } -pub struct MaybeCrossThread

{ - cross_thread: bool, - marker: PhantomData

, +pub struct MaybeCrossThread { + pub cross_thread: bool, } -impl

MaybeCrossThread

{ - pub const fn new(cross_thread: bool) -> Self { - MaybeCrossThread { cross_thread, marker: PhantomData } - } -} +pub const SAME_THREAD: MaybeCrossThread = MaybeCrossThread { cross_thread: false }; +pub const CROSS_THREAD: MaybeCrossThread = MaybeCrossThread { cross_thread: true }; -impl

ExecutionStrategy for MaybeCrossThread

-where - P: MessagePipe + Send + 'static, -{ +impl ExecutionStrategy for MaybeCrossThread { fn run_bridge_and_client( &self, - dispatcher: &mut impl DispatcherTrait, + dispatcher: &mut Dispatcher, input: Buffer, run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, force_show_panics: bool, ) -> Buffer { if self.cross_thread || ALREADY_RUNNING_SAME_THREAD.get() { - >::new().run_bridge_and_client( - dispatcher, - input, - run_client, - force_show_panics, - ) - } else { - SameThread.run_bridge_and_client(dispatcher, input, run_client, force_show_panics) - } - } -} - -pub struct SameThread; - -impl ExecutionStrategy for SameThread { - fn run_bridge_and_client( - &self, - dispatcher: &mut impl DispatcherTrait, - input: Buffer, - run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, - force_show_panics: bool, - ) -> Buffer { - let _guard = RunningSameThreadGuard::new(); - - let mut dispatch = |buf| dispatcher.dispatch(buf); - - run_client(BridgeConfig { input, dispatch: (&mut dispatch).into(), force_show_panics }) - } -} - -pub struct CrossThread

(PhantomData

); - -impl

CrossThread

{ - pub const fn new() -> Self { - CrossThread(PhantomData) - } -} + let (mut server, mut client) = MessagePipe::new(); + + let join_handle = thread::spawn(move || { + let mut dispatch = |b: Buffer| -> Buffer { + client.send(b); + client.recv().expect("server died while client waiting for reply") + }; + + run_client(BridgeConfig { + input, + dispatch: (&mut dispatch).into(), + force_show_panics, + }) + }); + + while let Some(b) = server.recv() { + server.send(dispatcher.dispatch(b)); + } -impl

ExecutionStrategy for CrossThread

-where - P: MessagePipe + Send + 'static, -{ - fn run_bridge_and_client( - &self, - dispatcher: &mut impl DispatcherTrait, - input: Buffer, - run_client: extern "C" fn(BridgeConfig<'_>) -> Buffer, - force_show_panics: bool, - ) -> Buffer { - let (mut server, mut client) = P::new(); + join_handle.join().unwrap() + } else { + let _guard = RunningSameThreadGuard::new(); - let join_handle = thread::spawn(move || { - let mut dispatch = |b: Buffer| -> Buffer { - client.send(b); - client.recv().expect("server died while client waiting for reply") - }; + let mut dispatch = |buf| dispatcher.dispatch(buf); run_client(BridgeConfig { input, dispatch: (&mut dispatch).into(), force_show_panics }) - }); - - while let Some(b) = server.recv() { - server.send(dispatcher.dispatch(b)); } - - join_handle.join().unwrap() } } /// A message pipe used for communicating between server and client threads. -pub trait MessagePipe: Sized { +struct MessagePipe { + tx: mpsc::SyncSender, + rx: mpsc::Receiver, +} + +impl MessagePipe { /// Creates a new pair of endpoints for the message pipe. - fn new() -> (Self, Self); + fn new() -> (Self, Self) { + let (tx1, rx1) = mpsc::sync_channel(1); + let (tx2, rx2) = mpsc::sync_channel(1); + (MessagePipe { tx: tx1, rx: rx2 }, MessagePipe { tx: tx2, rx: rx1 }) + } /// Send a message to the other endpoint of this pipe. - fn send(&mut self, value: T); + fn send(&mut self, value: T) { + self.tx.send(value).unwrap(); + } /// Receive a message from the other endpoint of this pipe. /// /// Returns `None` if the other end of the pipe has been destroyed, and no /// message was received. - fn recv(&mut self) -> Option; + fn recv(&mut self) -> Option { + self.rx.recv().ok() + } } fn run_server< @@ -312,7 +275,6 @@ impl client::Client { ) -> Result where S: Server, - S::TokenStream: Default, { let client::Client { handle_counters, run, _marker } = *self; run_server( @@ -338,7 +300,6 @@ impl client::Client<(crate::TokenStream, crate::TokenStream), crate::TokenStream ) -> Result where S: Server, - S::TokenStream: Default, { let client::Client { handle_counters, run, _marker } = *self; run_server( diff --git a/proc_macro/src/lib.rs b/proc_macro/src/lib.rs index 49b6f2ae41f89..a01bf38a62dbf 100644 --- a/proc_macro/src/lib.rs +++ b/proc_macro/src/lib.rs @@ -27,6 +27,7 @@ #![feature(restricted_std)] #![feature(rustc_attrs)] #![feature(extend_one)] +#![feature(mem_conjure_zst)] #![recursion_limit = "256"] #![allow(internal_features)] #![deny(ffi_unwind_calls)] @@ -109,15 +110,18 @@ impl !Send for TokenStream {} impl !Sync for TokenStream {} /// Error returned from `TokenStream::from_str`. +/// +/// The contained error message is explicitly not guaranteed to be stable in any way, +/// and may change between Rust versions or across compilations. #[stable(feature = "proc_macro_lib", since = "1.15.0")] #[non_exhaustive] #[derive(Debug)] -pub struct LexError; +pub struct LexError(String); #[stable(feature = "proc_macro_lexerror_impls", since = "1.44.0")] impl fmt::Display for LexError { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - f.write_str("cannot parse string into token stream") + f.write_str(&self.0) } } @@ -196,7 +200,7 @@ impl FromStr for TokenStream { type Err = LexError; fn from_str(src: &str) -> Result { - Ok(TokenStream(Some(BridgeMethods::ts_from_str(src)))) + Ok(TokenStream(Some(BridgeMethods::ts_from_str(src).map_err(LexError)?))) } } @@ -1593,7 +1597,7 @@ impl FromStr for Literal { fn from_str(src: &str) -> Result { match BridgeMethods::literal_from_str(src) { Ok(literal) => Ok(Literal(literal)), - Err(()) => Err(LexError), + Err(msg) => Err(LexError(msg)), } } } diff --git a/rtstartup/rsbegin.rs b/rtstartup/rsbegin.rs index 62d247fafb7ad..6ee06cce5c630 100644 --- a/rtstartup/rsbegin.rs +++ b/rtstartup/rsbegin.rs @@ -90,12 +90,12 @@ pub mod eh_frames { unsafe extern "C" fn init() { // register unwind info on module startup - __register_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &mut OBJ as *mut _ as *mut u8); + __register_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &raw mut OBJ as *mut u8); } unsafe extern "C" fn uninit() { // unregister on shutdown - __deregister_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &mut OBJ as *mut _ as *mut u8); + __deregister_frame_info(&__EH_FRAME_BEGIN__ as *const u8, &raw mut OBJ as *mut u8); } // MinGW-specific init/uninit routine registration diff --git a/std/Cargo.toml b/std/Cargo.toml index f4cc8edc0c1da..1b7a41d697367 100644 --- a/std/Cargo.toml +++ b/std/Cargo.toml @@ -146,10 +146,6 @@ harness = false name = "sync" path = "tests/sync/lib.rs" -[[test]] -name = "floats" -path = "tests/floats/lib.rs" - [[test]] name = "thread_local" path = "tests/thread_local/lib.rs" diff --git a/std/src/env.rs b/std/src/env.rs index 1f0ced5d0fd0d..edf0127a665e3 100644 --- a/std/src/env.rs +++ b/std/src/env.rs @@ -670,6 +670,17 @@ pub fn home_dir() -> Option { /// /// On Windows, the behavior is equivalent to that of [`GetTempPath2`][GetTempPath2] / /// [`GetTempPath`][GetTempPath], which this function uses internally. +/// Specifically, for non-SYSTEM processes, the function checks for the +/// following environment variables in order and returns the first path found: +/// +/// 1. The path specified by the `TMP` environment variable. +/// 2. The path specified by the `TEMP` environment variable. +/// 3. The path specified by the `USERPROFILE` environment variable. +/// 4. The Windows directory. +/// +/// When called from a process running as SYSTEM, +/// [`GetTempPath2`][GetTempPath2] returns `C:\Windows\SystemTemp` +/// regardless of environment variables. /// /// Note that, this [may change in the future][changes]. /// @@ -712,28 +723,21 @@ pub fn temp_dir() -> PathBuf { /// /// # Security /// -/// The output of this function should not be trusted for anything -/// that might have security implications. Basically, if users can run -/// the executable, they can change the output arbitrarily. -/// -/// As an example, you can easily introduce a race condition. It goes -/// like this: -/// -/// 1. You get the path to the current executable using `current_exe()`, and -/// store it in a variable. -/// 2. Time passes. A malicious actor removes the current executable, and -/// replaces it with a malicious one. -/// 3. You then use the stored path to re-execute the current -/// executable. +/// The output of this function must be treated with care to avoid security +/// vulnerabilities, particularly in processes that run with privileges higher +/// than the user, such as setuid or setgid programs. /// -/// You expected to safely execute the current executable, but you're -/// instead executing something completely different. The code you -/// just executed runs with your privileges. +/// For example, on some Unix platforms, the result is calculated by +/// searching `$PATH` for an executable matching `argv[0]`, but both the +/// environment and arguments can be be set arbitrarily by the user who +/// invokes the program. /// -/// This sort of behavior has been known to [lead to privilege escalation] when -/// used incorrectly. +/// On Linux, if `fs.secure_hardlinks` is not set, an attacker who can +/// create hardlinks to the executable may be able to cause this function +/// to return an attacker-controlled path, which they later replace with +/// a different program. /// -/// [lead to privilege escalation]: https://securityvulns.com/Wdocument183.html +/// This list of illustrative example attacks is not exhaustive. /// /// # Examples /// diff --git a/std/src/ffi/os_str.rs b/std/src/ffi/os_str.rs index 4e4d377ae2708..ca910153e5260 100644 --- a/std/src/ffi/os_str.rs +++ b/std/src/ffi/os_str.rs @@ -1565,7 +1565,7 @@ impl Ord for OsStr { macro_rules! impl_cmp { ($lhs:ty, $rhs: ty) => { #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { ::eq(self, other) @@ -1573,7 +1573,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { ::eq(self, other) @@ -1581,7 +1581,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { ::partial_cmp(self, other) @@ -1589,7 +1589,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_os_str", since = "1.8.0")] - impl<'a, 'b> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { ::partial_cmp(self, other) @@ -1599,10 +1599,10 @@ macro_rules! impl_cmp { } impl_cmp!(OsString, OsStr); -impl_cmp!(OsString, &'a OsStr); -impl_cmp!(Cow<'a, OsStr>, OsStr); -impl_cmp!(Cow<'a, OsStr>, &'b OsStr); -impl_cmp!(Cow<'a, OsStr>, OsString); +impl_cmp!(OsString, &OsStr); +impl_cmp!(Cow<'_, OsStr>, OsStr); +impl_cmp!(Cow<'_, OsStr>, &OsStr); +impl_cmp!(Cow<'_, OsStr>, OsString); #[stable(feature = "rust1", since = "1.0.0")] impl Hash for OsStr { diff --git a/std/src/fs.rs b/std/src/fs.rs index a24baad615012..cf6f9594c0027 100644 --- a/std/src/fs.rs +++ b/std/src/fs.rs @@ -277,6 +277,7 @@ pub struct OpenOptions(fs_imp::OpenOptions); /// Representation of the various timestamps on a file. #[derive(Copy, Clone, Debug, Default)] #[stable(feature = "file_set_times", since = "1.75.0")] +#[must_use = "must be applied to a file via `File::set_times` to have any effect"] pub struct FileTimes(fs_imp::FileTimes); /// Representation of the various permissions on a file. diff --git a/std/src/lib.rs b/std/src/lib.rs index dcde208fac77b..346571a3d1372 100644 --- a/std/src/lib.rs +++ b/std/src/lib.rs @@ -289,7 +289,6 @@ #![feature(ffi_const)] #![feature(formatting_options)] #![feature(funnel_shifts)] -#![feature(if_let_guard)] #![feature(intra_doc_pointers)] #![feature(iter_advance_by)] #![feature(iter_next_chunk)] @@ -315,6 +314,7 @@ #![feature(try_blocks)] #![feature(try_trait_v2)] #![feature(type_alias_impl_trait)] +#![feature(uint_carryless_mul)] // tidy-alphabetical-end // // Library features (core): @@ -322,7 +322,6 @@ #![feature(bstr)] #![feature(bstr_internals)] #![feature(cast_maybe_uninit)] -#![feature(cfg_select)] #![feature(char_internals)] #![feature(clone_to_uninit)] #![feature(const_convert)] @@ -394,7 +393,6 @@ // // Only for re-exporting: // tidy-alphabetical-start -#![feature(assert_matches)] #![feature(async_iterator)] #![feature(c_variadic)] #![feature(cfg_accessible)] @@ -497,6 +495,8 @@ pub use core::cmp; pub use core::convert; #[stable(feature = "rust1", since = "1.0.0")] pub use core::default; +#[unstable(feature = "field_projections", issue = "145383")] +pub use core::field; #[stable(feature = "futures_api", since = "1.36.0")] pub use core::future; #[stable(feature = "core_hint", since = "1.27.0")] @@ -696,7 +696,7 @@ mod panicking; #[allow(dead_code, unused_attributes, fuzzy_provenance_casts, unsafe_op_in_unsafe_fn)] mod backtrace_rs; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "CURRENT_RUSTC_VERSION")] pub use core::cfg_select; #[unstable( feature = "concat_bytes", @@ -726,7 +726,7 @@ pub use core::{ assert_eq, assert_ne, debug_assert, debug_assert_eq, debug_assert_ne, r#try, unimplemented, unreachable, write, writeln, }; -#[unstable(feature = "assert_matches", issue = "82775")] +#[stable(feature = "assert_matches", since = "CURRENT_RUSTC_VERSION")] pub use core::{assert_matches, debug_assert_matches}; // Re-export unstable derive macro defined through core. diff --git a/std/src/num/f128.rs b/std/src/num/f128.rs index 6f1fd2975b714..2c8898a6aa86a 100644 --- a/std/src/num/f128.rs +++ b/std/src/num/f128.rs @@ -16,6 +16,7 @@ use crate::intrinsics; use crate::sys::cmath; #[cfg(not(test))] +#[doc(test(attr(allow(unused_features))))] impl f128 { /// Raises a number to a floating point power. /// diff --git a/std/src/num/f16.rs b/std/src/num/f16.rs index 20d0b4e1e552b..318a0b3af86a2 100644 --- a/std/src/num/f16.rs +++ b/std/src/num/f16.rs @@ -916,7 +916,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_gamma)] /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// @@ -952,7 +951,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_gamma)] /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// @@ -988,7 +986,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_erf)] /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// /// The error function relates what percent of a normal distribution lies @@ -1028,7 +1025,6 @@ impl f16 { /// /// ``` /// #![feature(f16)] - /// #![feature(float_erf)] /// # #[cfg(not(miri))] /// # #[cfg(target_has_reliable_f16_math)] { /// let x: f16 = 0.123; diff --git a/std/src/os/fd/mod.rs b/std/src/os/fd/mod.rs index 95cf4932e6e2c..473d7ae3e2ae6 100644 --- a/std/src/os/fd/mod.rs +++ b/std/src/os/fd/mod.rs @@ -16,6 +16,9 @@ mod owned; #[cfg(not(target_os = "trusty"))] mod net; +// Implementation of stdio file descriptor constants. +mod stdio; + #[cfg(test)] mod tests; @@ -24,3 +27,5 @@ mod tests; pub use owned::*; #[stable(feature = "os_fd", since = "1.66.0")] pub use raw::*; +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub use stdio::*; diff --git a/std/src/os/fd/stdio.rs b/std/src/os/fd/stdio.rs new file mode 100644 index 0000000000000..c50cbd39849b7 --- /dev/null +++ b/std/src/os/fd/stdio.rs @@ -0,0 +1,53 @@ +use super::BorrowedFd; + +/// The file descriptor for the standard input stream of the current process. +/// +/// See [`io::stdin()`][`crate::io::stdin`] for the higher level handle, which should be preferred +/// whenever possible. See [`STDERR`] for why the file descriptor might be required and caveats. +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub const STDIN: BorrowedFd<'static> = unsafe { BorrowedFd::borrow_raw(0) }; + +/// The file descriptor for the standard output stream of the current process. +/// +/// See [`io::stdout()`][`crate::io::stdout`] for the higher level handle, which should be preferred +/// whenever possible. See [`STDERR`] for why the file descriptor might be required and caveats. In +/// addition to the issues discussed there, note that [`Stdout`][`crate::io::Stdout`] is buffered by +/// default, and writing to the file descriptor will bypass this buffer. +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub const STDOUT: BorrowedFd<'static> = unsafe { BorrowedFd::borrow_raw(1) }; + +/// The file descriptor for the standard error stream of the current process. +/// +/// See [`io::stderr()`][`crate::io::stderr`] for the higher level handle, which should be preferred +/// whenever possible. However, there are situations where touching the `std::io` handles (or most +/// other parts of the standard library) risks deadlocks or other subtle bugs. For example: +/// +/// - Global allocators must be careful to [avoid reentrancy][global-alloc-reentrancy], and the +/// `std::io` handles may allocate memory on (some) accesses. +/// - Signal handlers must be *async-signal-safe*, which rules out panicking, taking locks (may +/// deadlock if the signal handler interrupted a thread holding that lock), allocating memory, or +/// anything else that is not explicitly declared async-signal-safe. +/// - `CommandExt::pre_exec` callbacks can safely panic (with some limitations), but otherwise must +/// abide by similar limitations as signal handlers. In particular, at the time these callbacks +/// run, the stdio file descriptors have already been replaced, but the locks protecting the +/// `std::io` handles may be permanently locked if another thread held the lock at `fork()` time. +/// +/// In these and similar cases, direct access to the file descriptor may be required. However, in +/// most cases, using the `std::io` handles and accessing the file descriptor via the `AsFd` +/// implementations is preferable, as it enables cooperation with the standard library's locking and +/// buffering. +/// +/// # I/O safety +/// +/// This is a `BorrowedFd<'static>` because the standard input/output/error streams are shared +/// resources that must remain available for the lifetime of the process. This is only true when +/// linking `std`, and may not always hold for [code running before `main()`][before-after-main] or +/// in `no_std` environments. It is [unsound][io-safety] to close these file descriptors. Safe +/// patterns for changing these file descriptors are available on Unix via the `StdioExt` extension +/// trait. +/// +/// [before-after-main]: ../../../std/index.html#use-before-and-after-main +/// [io-safety]: ../../../std/io/index.html#io-safety +/// [global-alloc-reentrancy]: ../../../std/alloc/trait.GlobalAlloc.html#re-entrance +#[unstable(feature = "stdio_fd_consts", issue = "150836")] +pub const STDERR: BorrowedFd<'static> = unsafe { BorrowedFd::borrow_raw(2) }; diff --git a/std/src/os/unix/process.rs b/std/src/os/unix/process.rs index fab1b20b8c0e9..a739d6ad2a90d 100644 --- a/std/src/os/unix/process.rs +++ b/std/src/os/unix/process.rs @@ -593,5 +593,5 @@ impl From for process::ChildStderr { #[must_use] #[stable(feature = "unix_ppid", since = "1.27.0")] pub fn parent_id() -> u32 { - crate::sys::os::getppid() + crate::sys::process::getppid() } diff --git a/std/src/os/windows/net/listener.rs b/std/src/os/windows/net/listener.rs index 332b116ee1a39..345cfe8d22ba9 100644 --- a/std/src/os/windows/net/listener.rs +++ b/std/src/os/windows/net/listener.rs @@ -12,6 +12,8 @@ use crate::{fmt, io}; /// A structure representing a Unix domain socket server. /// +/// Under Windows, it will only work starting from Windows 10 17063. +/// /// # Examples /// /// ```no_run diff --git a/std/src/os/windows/net/stream.rs b/std/src/os/windows/net/stream.rs index c31f03fdf53f8..f2d0f7c09e9f1 100644 --- a/std/src/os/windows/net/stream.rs +++ b/std/src/os/windows/net/stream.rs @@ -17,6 +17,8 @@ use crate::time::Duration; use crate::{fmt, io}; /// A Unix stream socket. /// +/// Under Windows, it will only work starting from Windows 10 17063. +/// /// # Examples /// /// ```no_run diff --git a/std/src/os/windows/process.rs b/std/src/os/windows/process.rs index b32c6cd442ffa..ff3ae8145e0f6 100644 --- a/std/src/os/windows/process.rs +++ b/std/src/os/windows/process.rs @@ -573,7 +573,8 @@ impl<'a> ProcThreadAttributeListBuilder<'a> { /// /// # Example /// - /// ``` + #[cfg_attr(target_vendor = "win7", doc = "```no_run")] + #[cfg_attr(not(target_vendor = "win7"), doc = "```")] /// #![feature(windows_process_extensions_raw_attribute)] /// use std::ffi::c_void; /// use std::os::windows::process::{CommandExt, ProcThreadAttributeList}; diff --git a/std/src/path.rs b/std/src/path.rs index 25bd7005b9942..bf27df7b04281 100644 --- a/std/src/path.rs +++ b/std/src/path.rs @@ -19,6 +19,20 @@ //! matter the platform or filesystem. An exception to this is made for Windows //! drive letters. //! +//! ## Path normalization +//! +//! Several methods in this module perform basic path normalization by disregarding +//! repeated separators, non-leading `.` components, and trailing separators. These include: +//! - Methods for iteration, such as [`Path::components`] and [`Path::iter`] +//! - Methods for inspection, such as [`Path::has_root`] +//! - Comparisons using [`PartialEq`], [`PartialOrd`], and [`Ord`] +//! +//! [`Path::join`] and [`PathBuf::push`] also disregard trailing slashes. +//! +// FIXME(normalize_lexically): mention normalize_lexically once stable +//! These methods **do not** resolve `..` components or symlinks. For full normalization +//! including `..` resolution, use [`Path::canonicalize`] (which does access the filesystem). +//! //! ## Simple usage //! //! Path manipulation includes both parsing components from slices and building @@ -3827,9 +3841,9 @@ impl<'a> IntoIterator for &'a Path { } macro_rules! impl_cmp { - (<$($life:lifetime),*> $lhs:ty, $rhs: ty) => { + ($lhs:ty, $rhs: ty) => { #[stable(feature = "partialeq_path", since = "1.6.0")] - impl<$($life),*> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { ::eq(self, other) @@ -3837,7 +3851,7 @@ macro_rules! impl_cmp { } #[stable(feature = "partialeq_path", since = "1.6.0")] - impl<$($life),*> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { ::eq(self, other) @@ -3845,7 +3859,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { ::partial_cmp(self, other) @@ -3853,7 +3867,7 @@ macro_rules! impl_cmp { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { ::partial_cmp(self, other) @@ -3862,16 +3876,16 @@ macro_rules! impl_cmp { }; } -impl_cmp!(<> PathBuf, Path); -impl_cmp!(<'a> PathBuf, &'a Path); -impl_cmp!(<'a> Cow<'a, Path>, Path); -impl_cmp!(<'a, 'b> Cow<'a, Path>, &'b Path); -impl_cmp!(<'a> Cow<'a, Path>, PathBuf); +impl_cmp!(PathBuf, Path); +impl_cmp!(PathBuf, &Path); +impl_cmp!(Cow<'_, Path>, Path); +impl_cmp!(Cow<'_, Path>, &Path); +impl_cmp!(Cow<'_, Path>, PathBuf); macro_rules! impl_cmp_os_str { - (<$($life:lifetime),*> $lhs:ty, $rhs: ty) => { + ($lhs:ty, $rhs: ty) => { #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialEq<$rhs> for $lhs { + impl PartialEq<$rhs> for $lhs { #[inline] fn eq(&self, other: &$rhs) -> bool { ::eq(self, other.as_ref()) @@ -3879,7 +3893,7 @@ macro_rules! impl_cmp_os_str { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialEq<$lhs> for $rhs { + impl PartialEq<$lhs> for $rhs { #[inline] fn eq(&self, other: &$lhs) -> bool { ::eq(self.as_ref(), other) @@ -3887,7 +3901,7 @@ macro_rules! impl_cmp_os_str { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$rhs> for $lhs { + impl PartialOrd<$rhs> for $lhs { #[inline] fn partial_cmp(&self, other: &$rhs) -> Option { ::partial_cmp(self, other.as_ref()) @@ -3895,7 +3909,7 @@ macro_rules! impl_cmp_os_str { } #[stable(feature = "cmp_path", since = "1.8.0")] - impl<$($life),*> PartialOrd<$lhs> for $rhs { + impl PartialOrd<$lhs> for $rhs { #[inline] fn partial_cmp(&self, other: &$lhs) -> Option { ::partial_cmp(self.as_ref(), other) @@ -3904,20 +3918,20 @@ macro_rules! impl_cmp_os_str { }; } -impl_cmp_os_str!(<> PathBuf, OsStr); -impl_cmp_os_str!(<'a> PathBuf, &'a OsStr); -impl_cmp_os_str!(<'a> PathBuf, Cow<'a, OsStr>); -impl_cmp_os_str!(<> PathBuf, OsString); -impl_cmp_os_str!(<> Path, OsStr); -impl_cmp_os_str!(<'a> Path, &'a OsStr); -impl_cmp_os_str!(<'a> Path, Cow<'a, OsStr>); -impl_cmp_os_str!(<> Path, OsString); -impl_cmp_os_str!(<'a> &'a Path, OsStr); -impl_cmp_os_str!(<'a, 'b> &'a Path, Cow<'b, OsStr>); -impl_cmp_os_str!(<'a> &'a Path, OsString); -impl_cmp_os_str!(<'a> Cow<'a, Path>, OsStr); -impl_cmp_os_str!(<'a, 'b> Cow<'a, Path>, &'b OsStr); -impl_cmp_os_str!(<'a> Cow<'a, Path>, OsString); +impl_cmp_os_str!(PathBuf, OsStr); +impl_cmp_os_str!(PathBuf, &OsStr); +impl_cmp_os_str!(PathBuf, Cow<'_, OsStr>); +impl_cmp_os_str!(PathBuf, OsString); +impl_cmp_os_str!(Path, OsStr); +impl_cmp_os_str!(Path, &OsStr); +impl_cmp_os_str!(Path, Cow<'_, OsStr>); +impl_cmp_os_str!(Path, OsString); +impl_cmp_os_str!(&Path, OsStr); +impl_cmp_os_str!(&Path, Cow<'_, OsStr>); +impl_cmp_os_str!(&Path, OsString); +impl_cmp_os_str!(Cow<'_, Path>, OsStr); +impl_cmp_os_str!(Cow<'_, Path>, &OsStr); +impl_cmp_os_str!(Cow<'_, Path>, OsString); #[stable(since = "1.7.0", feature = "strip_prefix")] impl fmt::Display for StripPrefixError { diff --git a/std/src/prelude/v1.rs b/std/src/prelude/v1.rs index af9d28ebad356..f17f11dec7f62 100644 --- a/std/src/prelude/v1.rs +++ b/std/src/prelude/v1.rs @@ -79,7 +79,7 @@ mod ambiguous_macros_only { #[doc(no_inline)] pub use self::ambiguous_macros_only::{vec, panic}; -#[unstable(feature = "cfg_select", issue = "115585")] +#[stable(feature = "cfg_select", since = "CURRENT_RUSTC_VERSION")] #[doc(no_inline)] pub use core::prelude::v1::cfg_select; diff --git a/std/src/process.rs b/std/src/process.rs index 6838bb422b0e0..1199403b1d5ab 100644 --- a/std/src/process.rs +++ b/std/src/process.rs @@ -2464,7 +2464,7 @@ impl Child { #[cfg_attr(not(test), rustc_diagnostic_item = "process_exit")] pub fn exit(code: i32) -> ! { crate::rt::cleanup(); - crate::sys::os::exit(code) + crate::sys::exit::exit(code) } /// Terminates the process in an abnormal fashion. @@ -2545,7 +2545,7 @@ pub fn abort() -> ! { #[must_use] #[stable(feature = "getpid", since = "1.26.0")] pub fn id() -> u32 { - crate::sys::os::getpid() + imp::getpid() } /// A trait for implementing arbitrary return types in the `main` function. diff --git a/std/src/random.rs b/std/src/random.rs index 3994c5cfaf6f4..a18dcf98ec7fc 100644 --- a/std/src/random.rs +++ b/std/src/random.rs @@ -37,7 +37,7 @@ use crate::sys::random as sys; /// Horizon, Cygwin | `getrandom` /// AIX, Hurd, L4Re, QNX | `/dev/urandom` /// Redox | `/scheme/rand` -/// RTEMS | [`arc4random_buf`](https://docs.rtems.org/branches/master/bsp-howto/getentropy.html) +/// RTEMS | [`arc4random_buf`](https://docs.rtems.org/branches/main/bsp-howto/getentropy.html) /// SGX | [`rdrand`](https://en.wikipedia.org/wiki/RDRAND) /// SOLID | `SOLID_RNG_SampleRandomBytes` /// TEEOS | `TEE_GenerateRandom` diff --git a/std/src/rt.rs b/std/src/rt.rs index 11c0a0b9daf7b..1e7de695ddae7 100644 --- a/std/src/rt.rs +++ b/std/src/rt.rs @@ -187,7 +187,7 @@ fn lang_start_internal( cleanup(); // Guard against multiple threads calling `libc::exit` concurrently. // See the documentation for `unique_thread_exit` for more information. - crate::sys::exit_guard::unique_thread_exit(); + crate::sys::exit::unique_thread_exit(); ret_code }) diff --git a/std/src/sync/poison/rwlock.rs b/std/src/sync/poison/rwlock.rs index acfeb96900cc9..c01ee17eecda3 100644 --- a/std/src/sync/poison/rwlock.rs +++ b/std/src/sync/poison/rwlock.rs @@ -56,24 +56,36 @@ use crate::sys::sync as sys; /// # Examples /// /// ``` -/// use std::sync::RwLock; +/// use std::sync::{Arc, RwLock}; +/// use std::thread; +/// use std::time::Duration; /// -/// let lock = RwLock::new(5); +/// let data = Arc::new(RwLock::new(5)); /// -/// // many reader locks can be held at once -/// { -/// let r1 = lock.read().unwrap(); -/// let r2 = lock.read().unwrap(); -/// assert_eq!(*r1, 5); -/// assert_eq!(*r2, 5); -/// } // read locks are dropped at this point +/// // Multiple readers can access in parallel. +/// for i in 0..3 { +/// let lock_clone = Arc::clone(&data); /// -/// // only one write lock may be held, however -/// { -/// let mut w = lock.write().unwrap(); -/// *w += 1; -/// assert_eq!(*w, 6); -/// } // write lock is dropped here +/// thread::spawn(move || { +/// let value = lock_clone.read().unwrap(); +/// +/// println!("Reader {}: Read value {}, now holding lock...", i, *value); +/// +/// // Simulating a long read operation +/// thread::sleep(Duration::from_secs(1)); +/// +/// println!("Reader {}: Dropping lock.", i); +/// // Read lock unlocked when going out of scope. +/// }); +/// } +/// +/// thread::sleep(Duration::from_millis(100)); // Wait for readers to start +/// +/// // While all readers can proceed, a call to .write() has to wait for +// // current active reader locks. +/// let mut writable_data = data.write().unwrap(); +/// println!("Writer proceeds..."); +/// *writable_data += 1; /// ``` /// /// [`Mutex`]: super::Mutex @@ -370,7 +382,8 @@ impl RwLock { /// /// # Panics /// - /// This function might panic when called if the lock is already held by the current thread. + /// This function might panic when called if the lock is already held by the current thread + /// in read or write mode. /// /// # Examples /// @@ -467,7 +480,8 @@ impl RwLock { /// /// # Panics /// - /// This function might panic when called if the lock is already held by the current thread. + /// This function might panic when called if the lock is already held by the current thread + /// in read or write mode. /// /// # Examples /// diff --git a/std/src/sys/args/unix.rs b/std/src/sys/args/unix.rs index 0dfbd5f03eba9..7a592c2b079dd 100644 --- a/std/src/sys/args/unix.rs +++ b/std/src/sys/args/unix.rs @@ -164,7 +164,7 @@ mod imp { // of this used `[[NSProcessInfo processInfo] arguments]`. #[cfg(target_vendor = "apple")] mod imp { - use crate::ffi::{c_char, c_int}; + use crate::ffi::c_char; pub unsafe fn init(_argc: isize, _argv: *const *const u8) { // No need to initialize anything in here, `libdyld.dylib` has already @@ -172,12 +172,6 @@ mod imp { } pub fn argc_argv() -> (isize, *const *const c_char) { - unsafe extern "C" { - // These functions are in crt_externs.h. - fn _NSGetArgc() -> *mut c_int; - fn _NSGetArgv() -> *mut *mut *mut c_char; - } - // SAFETY: The returned pointer points to a static initialized early // in the program lifetime by `libdyld.dylib`, and as such is always // valid. @@ -187,9 +181,9 @@ mod imp { // doesn't exist a lock that we can take. Instead, it is generally // expected that it's only modified in `main` / before other code // runs, so reading this here should be fine. - let argc = unsafe { _NSGetArgc().read() }; + let argc = unsafe { libc::_NSGetArgc().read() }; // SAFETY: Same as above. - let argv = unsafe { _NSGetArgv().read() }; + let argv = unsafe { libc::_NSGetArgv().read() }; // Cast from `*mut *mut c_char` to `*const *const c_char` (argc as isize, argv.cast()) diff --git a/std/src/sys/env/uefi.rs b/std/src/sys/env/uefi.rs index af16a02642a4c..bc2aed4231797 100644 --- a/std/src/sys/env/uefi.rs +++ b/std/src/sys/env/uefi.rs @@ -43,7 +43,20 @@ mod uefi_env { pub(crate) fn unset(key: &OsStr) -> io::Result<()> { let mut key_ptr = helpers::os_string_to_raw(key) .ok_or(io::const_error!(io::ErrorKind::InvalidInput, "invalid key"))?; - unsafe { set_raw(key_ptr.as_mut_ptr(), crate::ptr::null_mut()) } + let r = unsafe { set_raw(key_ptr.as_mut_ptr(), crate::ptr::null_mut()) }; + + // The UEFI Shell spec only lists `EFI_SUCCESS` as a possible return value for + // `SetEnv`, but the edk2 implementation can return errors. Allow most of these + // errors to bubble up to the caller, but ignore `NotFound` errors; deleting a + // nonexistent variable is not listed as an error condition of + // `std::env::remove_var`. + if let Err(err) = &r + && err.kind() == io::ErrorKind::NotFound + { + Ok(()) + } else { + r + } } pub(crate) fn get_all() -> io::Result> { diff --git a/std/src/sys/exit_guard.rs b/std/src/sys/exit.rs similarity index 60% rename from std/src/sys/exit_guard.rs rename to std/src/sys/exit.rs index e7d7a478a5baa..53fb92ba077e0 100644 --- a/std/src/sys/exit_guard.rs +++ b/std/src/sys/exit.rs @@ -19,8 +19,7 @@ cfg_select! { /// * If it is called again on the same thread as the first call, it will abort. /// * If it is called again on a different thread, it will wait in a loop /// (waiting for the process to exit). - #[cfg_attr(any(test, doctest), allow(dead_code))] - pub(crate) fn unique_thread_exit() { + pub fn unique_thread_exit() { use crate::ffi::c_int; use crate::ptr; use crate::sync::atomic::AtomicPtr; @@ -62,9 +61,83 @@ cfg_select! { /// /// Mitigation is ***NOT*** implemented on this platform, either because this platform /// is not affected, or because mitigation is not yet implemented for this platform. - #[cfg_attr(any(test, doctest), allow(dead_code))] - pub(crate) fn unique_thread_exit() { + #[cfg_attr(any(test, doctest), expect(dead_code))] + pub fn unique_thread_exit() { // Mitigation not required on platforms where `exit` is thread-safe. } } } + +pub fn exit(code: i32) -> ! { + cfg_select! { + target_os = "hermit" => { + unsafe { hermit_abi::exit(code) } + } + target_os = "linux" => { + unsafe { + unique_thread_exit(); + libc::exit(code) + } + } + target_os = "motor" => { + moto_rt::process::exit(code) + } + all(target_vendor = "fortanix", target_env = "sgx") => { + crate::sys::pal::abi::exit_with_code(code as _) + } + target_os = "solid_asp3" => { + rtabort!("exit({}) called", code) + } + target_os = "teeos" => { + let _ = code; + panic!("TA should not call `exit`") + } + target_os = "uefi" => { + use r_efi::base::Status; + + use crate::os::uefi::env; + + if let (Some(boot_services), Some(handle)) = + (env::boot_services(), env::try_image_handle()) + { + let boot_services = boot_services.cast::(); + let _ = unsafe { + ((*boot_services.as_ptr()).exit)( + handle.as_ptr(), + Status::from_usize(code as usize), + 0, + crate::ptr::null_mut(), + ) + }; + } + crate::intrinsics::abort() + } + any( + target_family = "unix", + target_os = "wasi", + ) => { + unsafe { libc::exit(code as crate::ffi::c_int) } + } + target_os = "vexos" => { + let _ = code; + + unsafe { + vex_sdk::vexSystemExitRequest(); + + loop { + vex_sdk::vexTasksRun(); + } + } + } + target_os = "windows" => { + unsafe { crate::sys::pal::c::ExitProcess(code as u32) } + } + target_os = "xous" => { + crate::os::xous::ffi::exit(code as u32) + } + _ => { + let _ = code; + crate::intrinsics::abort() + } + } +} diff --git a/std/src/sys/fs/unix.rs b/std/src/sys/fs/unix.rs index 3ca84db0f47fc..7db474544f04a 100644 --- a/std/src/sys/fs/unix.rs +++ b/std/src/sys/fs/unix.rs @@ -2132,9 +2132,6 @@ pub fn link(original: &CStr, link: &CStr) -> io::Result<()> { // Android has `linkat` on newer versions, but we happen to know // `link` always has the correct behavior, so it's here as well. target_os = "android", - // wasi-sdk-29-and-prior have a buggy `linkat` so use `link` instead - // until wasi-sdk is updated (see WebAssembly/wasi-libc#690) - target_os = "wasi", // Other misc platforms target_os = "horizon", target_os = "vita", diff --git a/std/src/sys/fs/vexos.rs b/std/src/sys/fs/vexos.rs index 81083a4fa81d3..5f75bcd92421b 100644 --- a/std/src/sys/fs/vexos.rs +++ b/std/src/sys/fs/vexos.rs @@ -12,8 +12,8 @@ use crate::sys::{unsupported, unsupported_err}; #[path = "unsupported.rs"] mod unsupported_fs; pub use unsupported_fs::{ - DirBuilder, FileTimes, canonicalize, link, readlink, remove_dir_all, rename, rmdir, symlink, - unlink, + Dir, DirBuilder, FileTimes, canonicalize, link, readlink, remove_dir_all, rename, rmdir, + symlink, unlink, }; /// VEXos file descriptor. diff --git a/std/src/sys/mod.rs b/std/src/sys/mod.rs index 5436c144d3330..5ad23972860bb 100644 --- a/std/src/sys/mod.rs +++ b/std/src/sys/mod.rs @@ -11,7 +11,7 @@ pub mod backtrace; pub mod cmath; pub mod env; pub mod env_consts; -pub mod exit_guard; +pub mod exit; pub mod fd; pub mod fs; pub mod io; diff --git a/std/src/sys/pal/hermit/os.rs b/std/src/sys/pal/hermit/os.rs index 48a7cdcd2f763..188caded55d48 100644 --- a/std/src/sys/pal/hermit/os.rs +++ b/std/src/sys/pal/hermit/os.rs @@ -1,4 +1,3 @@ -use super::hermit_abi; use crate::ffi::{OsStr, OsString}; use crate::marker::PhantomData; use crate::path::{self, PathBuf}; @@ -56,11 +55,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(code: i32) -> ! { - unsafe { hermit_abi::exit(code) } -} - -pub fn getpid() -> u32 { - unsafe { hermit_abi::getpid() as u32 } -} diff --git a/std/src/sys/pal/motor/os.rs b/std/src/sys/pal/motor/os.rs index cdf66e3958dbe..0af579303306e 100644 --- a/std/src/sys/pal/motor/os.rs +++ b/std/src/sys/pal/motor/os.rs @@ -62,11 +62,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(code: i32) -> ! { - moto_rt::process::exit(code) -} - -pub fn getpid() -> u32 { - panic!("Pids on Motor OS are u64.") -} diff --git a/std/src/sys/pal/sgx/abi/mod.rs b/std/src/sys/pal/sgx/abi/mod.rs index 1c6c681d4c179..3314f4f3b6223 100644 --- a/std/src/sys/pal/sgx/abi/mod.rs +++ b/std/src/sys/pal/sgx/abi/mod.rs @@ -96,7 +96,7 @@ extern "C" fn entry(p1: u64, p2: u64, p3: u64, secondary: bool, p4: u64, p5: u64 } } -pub(super) fn exit_with_code(code: isize) -> ! { +pub fn exit_with_code(code: isize) -> ! { if code != 0 { if let Some(mut out) = panic::SgxPanicOutput::new() { let _ = write!(out, "Exited with status code {code}"); diff --git a/std/src/sys/pal/sgx/os.rs b/std/src/sys/pal/sgx/os.rs index ba47af7ff88d7..5b0af37a3d373 100644 --- a/std/src/sys/pal/sgx/os.rs +++ b/std/src/sys/pal/sgx/os.rs @@ -55,11 +55,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(code: i32) -> ! { - super::abi::exit_with_code(code as _) -} - -pub fn getpid() -> u32 { - panic!("no pids in SGX") -} diff --git a/std/src/sys/pal/solid/os.rs b/std/src/sys/pal/solid/os.rs index c336a1042da40..4a07d240d2e66 100644 --- a/std/src/sys/pal/solid/os.rs +++ b/std/src/sys/pal/solid/os.rs @@ -62,11 +62,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(code: i32) -> ! { - rtabort!("exit({}) called", code); -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/pal/teeos/os.rs b/std/src/sys/pal/teeos/os.rs index a4b1d3c6ae670..c09b84f42bab9 100644 --- a/std/src/sys/pal/teeos/os.rs +++ b/std/src/sys/pal/teeos/os.rs @@ -66,11 +66,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(_code: i32) -> ! { - panic!("TA should not call `exit`") -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/pal/uefi/os.rs b/std/src/sys/pal/uefi/os.rs index 5b9785c8371e3..b25be430a3f83 100644 --- a/std/src/sys/pal/uefi/os.rs +++ b/std/src/sys/pal/uefi/os.rs @@ -1,13 +1,9 @@ -use r_efi::efi::Status; use r_efi::efi::protocols::{device_path, loaded_image_device_path}; use super::{helpers, unsupported_err}; use crate::ffi::{OsStr, OsString}; -use crate::marker::PhantomData; -use crate::os::uefi; use crate::os::uefi::ffi::{OsStrExt, OsStringExt}; use crate::path::{self, PathBuf}; -use crate::ptr::NonNull; use crate::{fmt, io}; const PATHS_SEP: u16 = b';' as u16; @@ -41,16 +37,37 @@ pub fn chdir(p: &path::Path) -> io::Result<()> { if r.is_error() { Err(io::Error::from_raw_os_error(r.as_usize())) } else { Ok(()) } } -pub struct SplitPaths<'a>(!, PhantomData<&'a ()>); +pub struct SplitPaths<'a> { + data: crate::os::uefi::ffi::EncodeWide<'a>, + must_yield: bool, +} -pub fn split_paths(_unparsed: &OsStr) -> SplitPaths<'_> { - panic!("unsupported") +pub fn split_paths(unparsed: &OsStr) -> SplitPaths<'_> { + SplitPaths { data: unparsed.encode_wide(), must_yield: true } } impl<'a> Iterator for SplitPaths<'a> { type Item = PathBuf; + fn next(&mut self) -> Option { - self.0 + let must_yield = self.must_yield; + self.must_yield = false; + + let mut in_progress = Vec::new(); + for b in self.data.by_ref() { + if b == PATHS_SEP { + self.must_yield = true; + break; + } else { + in_progress.push(b) + } + } + + if !must_yield && in_progress.is_empty() { + None + } else { + Some(PathBuf::from(OsString::from_wide(&in_progress))) + } } } @@ -104,24 +121,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(code: i32) -> ! { - if let (Some(boot_services), Some(handle)) = - (uefi::env::boot_services(), uefi::env::try_image_handle()) - { - let boot_services: NonNull = boot_services.cast(); - let _ = unsafe { - ((*boot_services.as_ptr()).exit)( - handle.as_ptr(), - Status::from_usize(code as usize), - 0, - crate::ptr::null_mut(), - ) - }; - } - crate::intrinsics::abort() -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/pal/unix/mod.rs b/std/src/sys/pal/unix/mod.rs index 6127bb98f80ef..0fbf37fda7fbf 100644 --- a/std/src/sys/pal/unix/mod.rs +++ b/std/src/sys/pal/unix/mod.rs @@ -169,15 +169,15 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { pub const SIG_DFL: u8 = 3; } - let (sigpipe_attr_specified, handler) = match sigpipe { + let (on_broken_pipe_used, handler) = match sigpipe { sigpipe::DEFAULT => (false, Some(libc::SIG_IGN)), sigpipe::INHERIT => (true, None), sigpipe::SIG_IGN => (true, Some(libc::SIG_IGN)), sigpipe::SIG_DFL => (true, Some(libc::SIG_DFL)), _ => unreachable!(), }; - if sigpipe_attr_specified { - ON_BROKEN_PIPE_FLAG_USED.store(true, crate::sync::atomic::Ordering::Relaxed); + if on_broken_pipe_used { + ON_BROKEN_PIPE_USED.store(true, crate::sync::atomic::Ordering::Relaxed); } if let Some(handler) = handler { rtassert!(signal(libc::SIGPIPE, handler) != libc::SIG_ERR); @@ -199,7 +199,7 @@ pub unsafe fn init(argc: isize, argv: *const *const u8, sigpipe: u8) { target_os = "vxworks", target_os = "vita", )))] -static ON_BROKEN_PIPE_FLAG_USED: crate::sync::atomic::Atomic = +static ON_BROKEN_PIPE_USED: crate::sync::atomic::Atomic = crate::sync::atomic::AtomicBool::new(false); #[cfg(not(any( @@ -211,8 +211,8 @@ static ON_BROKEN_PIPE_FLAG_USED: crate::sync::atomic::Atomic = target_os = "vita", target_os = "nuttx", )))] -pub(crate) fn on_broken_pipe_flag_used() -> bool { - ON_BROKEN_PIPE_FLAG_USED.load(crate::sync::atomic::Ordering::Relaxed) +pub(crate) fn on_broken_pipe_used() -> bool { + ON_BROKEN_PIPE_USED.load(crate::sync::atomic::Ordering::Relaxed) } // SAFETY: must be called only once during runtime cleanup. diff --git a/std/src/sys/pal/unix/os.rs b/std/src/sys/pal/unix/os.rs index b8280a8f29a02..d11282682d08d 100644 --- a/std/src/sys/pal/unix/os.rs +++ b/std/src/sys/pal/unix/os.rs @@ -533,19 +533,6 @@ pub fn home_dir() -> Option { } } -pub fn exit(code: i32) -> ! { - crate::sys::exit_guard::unique_thread_exit(); - unsafe { libc::exit(code as c_int) } -} - -pub fn getpid() -> u32 { - unsafe { libc::getpid() as u32 } -} - -pub fn getppid() -> u32 { - unsafe { libc::getppid() as u32 } -} - #[cfg(all(target_os = "linux", target_env = "gnu"))] pub fn glibc_version() -> Option<(usize, usize)> { unsafe extern "C" { diff --git a/std/src/sys/pal/unsupported/os.rs b/std/src/sys/pal/unsupported/os.rs index cb925ef4348db..fe8addeafd2bc 100644 --- a/std/src/sys/pal/unsupported/os.rs +++ b/std/src/sys/pal/unsupported/os.rs @@ -55,11 +55,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(_code: i32) -> ! { - crate::intrinsics::abort() -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/pal/vexos/mod.rs b/std/src/sys/pal/vexos/mod.rs index 16aa3f088f04b..d1380ab8dff14 100644 --- a/std/src/sys/pal/vexos/mod.rs +++ b/std/src/sys/pal/vexos/mod.rs @@ -1,3 +1,4 @@ +#[path = "../unsupported/os.rs"] pub mod os; #[expect(dead_code)] diff --git a/std/src/sys/pal/vexos/os.rs b/std/src/sys/pal/vexos/os.rs deleted file mode 100644 index 303b452a078ff..0000000000000 --- a/std/src/sys/pal/vexos/os.rs +++ /dev/null @@ -1,19 +0,0 @@ -#[expect(dead_code)] -#[path = "../unsupported/os.rs"] -mod unsupported_os; -pub use unsupported_os::{ - JoinPathsError, SplitPaths, chdir, current_exe, getcwd, getpid, home_dir, join_paths, - split_paths, temp_dir, -}; - -pub use super::unsupported; - -pub fn exit(_code: i32) -> ! { - unsafe { - vex_sdk::vexSystemExitRequest(); - - loop { - vex_sdk::vexTasksRun(); - } - } -} diff --git a/std/src/sys/pal/wasi/os.rs b/std/src/sys/pal/wasi/os.rs index 285be3ca9fda4..c8f3ddf692bcc 100644 --- a/std/src/sys/pal/wasi/os.rs +++ b/std/src/sys/pal/wasi/os.rs @@ -102,14 +102,6 @@ pub fn home_dir() -> Option { None } -pub fn exit(code: i32) -> ! { - unsafe { libc::exit(code) } -} - -pub fn getpid() -> u32 { - panic!("unsupported"); -} - #[doc(hidden)] pub trait IsMinusOne { fn is_minus_one(&self) -> bool; diff --git a/std/src/sys/pal/windows/os.rs b/std/src/sys/pal/windows/os.rs index 3eb6ec8278401..30cad2a05683c 100644 --- a/std/src/sys/pal/windows/os.rs +++ b/std/src/sys/pal/windows/os.rs @@ -188,11 +188,3 @@ pub fn home_dir() -> Option { .map(PathBuf::from) .or_else(home_dir_crt) } - -pub fn exit(code: i32) -> ! { - unsafe { c::ExitProcess(code as u32) } -} - -pub fn getpid() -> u32 { - unsafe { c::GetCurrentProcessId() } -} diff --git a/std/src/sys/pal/xous/os.rs b/std/src/sys/pal/xous/os.rs index cd7b7b59d1127..0f5a708863f72 100644 --- a/std/src/sys/pal/xous/os.rs +++ b/std/src/sys/pal/xous/os.rs @@ -118,11 +118,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(code: i32) -> ! { - crate::os::xous::ffi::exit(code as u32); -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/pal/zkvm/os.rs b/std/src/sys/pal/zkvm/os.rs index cb925ef4348db..fe8addeafd2bc 100644 --- a/std/src/sys/pal/zkvm/os.rs +++ b/std/src/sys/pal/zkvm/os.rs @@ -55,11 +55,3 @@ pub fn temp_dir() -> PathBuf { pub fn home_dir() -> Option { None } - -pub fn exit(_code: i32) -> ! { - crate::intrinsics::abort() -} - -pub fn getpid() -> u32 { - panic!("no pids on this platform") -} diff --git a/std/src/sys/process/mod.rs b/std/src/sys/process/mod.rs index 121d3bc9d5c3c..46f4ebf6db421 100644 --- a/std/src/sys/process/mod.rs +++ b/std/src/sys/process/mod.rs @@ -27,9 +27,11 @@ cfg_select! { mod env; pub use env::CommandEnvs; +#[cfg(target_family = "unix")] +pub use imp::getppid; pub use imp::{ ChildPipe, Command, CommandArgs, EnvKey, ExitCode, ExitStatus, ExitStatusError, Process, Stdio, - read_output, + getpid, read_output, }; #[cfg(any( diff --git a/std/src/sys/process/motor.rs b/std/src/sys/process/motor.rs index a5d0184478904..133633f7bc67b 100644 --- a/std/src/sys/process/motor.rs +++ b/std/src/sys/process/motor.rs @@ -327,3 +327,7 @@ pub fn read_output( ) -> io::Result<()> { Err(io::Error::from_raw_os_error(moto_rt::E_NOT_IMPLEMENTED.into())) } + +pub fn getpid() -> u32 { + panic!("Pids on Motor OS are u64.") +} diff --git a/std/src/sys/process/uefi.rs b/std/src/sys/process/uefi.rs index 31914aeb67c59..88dd4c899b377 100644 --- a/std/src/sys/process/uefi.rs +++ b/std/src/sys/process/uefi.rs @@ -900,3 +900,7 @@ fn env_changes(env: &CommandEnv) -> Option, O Some(result) } + +pub fn getpid() -> u32 { + panic!("no pids on this platform") +} diff --git a/std/src/sys/process/unix/common.rs b/std/src/sys/process/unix/common.rs index f6bbfed61ef31..2d83782b7d0b9 100644 --- a/std/src/sys/process/unix/common.rs +++ b/std/src/sys/process/unix/common.rs @@ -679,3 +679,11 @@ pub fn read_output( } } } + +pub fn getpid() -> u32 { + unsafe { libc::getpid() as u32 } +} + +pub fn getppid() -> u32 { + unsafe { libc::getppid() as u32 } +} diff --git a/std/src/sys/process/unix/mod.rs b/std/src/sys/process/unix/mod.rs index 1938e8f4b737c..dafe7c8c76da5 100644 --- a/std/src/sys/process/unix/mod.rs +++ b/std/src/sys/process/unix/mod.rs @@ -23,5 +23,7 @@ cfg_select! { pub use imp::{ExitStatus, ExitStatusError, Process}; -pub use self::common::{ChildPipe, Command, CommandArgs, ExitCode, Stdio, read_output}; +pub use self::common::{ + ChildPipe, Command, CommandArgs, ExitCode, Stdio, getpid, getppid, read_output, +}; pub use crate::ffi::OsString as EnvKey; diff --git a/std/src/sys/process/unix/unix.rs b/std/src/sys/process/unix/unix.rs index 62d6e0581e6c8..82ff94fb1e030 100644 --- a/std/src/sys/process/unix/unix.rs +++ b/std/src/sys/process/unix/unix.rs @@ -356,7 +356,7 @@ impl Command { // If -Zon-broken-pipe is not used, reset SIGPIPE to SIG_DFL for backward compatibility. // // -Zon-broken-pipe is an opportunity to change the default here. - if !crate::sys::pal::on_broken_pipe_flag_used() { + if !crate::sys::pal::on_broken_pipe_used() { #[cfg(target_os = "android")] // see issue #88585 { let mut action: libc::sigaction = mem::zeroed(); @@ -455,7 +455,7 @@ impl Command { use core::sync::atomic::{Atomic, AtomicU8, Ordering}; use crate::mem::MaybeUninit; - use crate::sys::{self, cvt_nz, on_broken_pipe_flag_used}; + use crate::sys::{self, cvt_nz, on_broken_pipe_used}; if self.get_gid().is_some() || self.get_uid().is_some() @@ -731,7 +731,7 @@ impl Command { // If -Zon-broken-pipe is not used, reset SIGPIPE to SIG_DFL for backward compatibility. // // -Zon-broken-pipe is an opportunity to change the default here. - if !on_broken_pipe_flag_used() { + if !on_broken_pipe_used() { let mut default_set = MaybeUninit::::uninit(); cvt(sigemptyset(default_set.as_mut_ptr()))?; cvt(sigaddset(default_set.as_mut_ptr(), libc::SIGPIPE))?; diff --git a/std/src/sys/process/unsupported.rs b/std/src/sys/process/unsupported.rs index 455c38e55b7ba..9ed66a559117c 100644 --- a/std/src/sys/process/unsupported.rs +++ b/std/src/sys/process/unsupported.rs @@ -327,3 +327,7 @@ pub fn read_output( ) -> io::Result<()> { match out.diverge() {} } + +pub fn getpid() -> u32 { + panic!("no pids on this platform") +} diff --git a/std/src/sys/process/windows.rs b/std/src/sys/process/windows.rs index b40833ad212c4..deb4243d314e2 100644 --- a/std/src/sys/process/windows.rs +++ b/std/src/sys/process/windows.rs @@ -976,3 +976,7 @@ impl<'a> fmt::Debug for CommandArgs<'a> { f.debug_list().entries(self.iter.clone()).finish() } } + +pub fn getpid() -> u32 { + unsafe { c::GetCurrentProcessId() } +} diff --git a/std/src/sys/sync/condvar/xous.rs b/std/src/sys/sync/condvar/xous.rs index 21a1587214a11..5d1b14443c62a 100644 --- a/std/src/sys/sync/condvar/xous.rs +++ b/std/src/sys/sync/condvar/xous.rs @@ -38,7 +38,7 @@ impl Condvar { // possible for `counter` to decrease due to a condvar timing out, in which // case the corresponding `timed_out` will increase accordingly. let Ok(waiter_count) = - self.counter.fetch_update(Ordering::Relaxed, Ordering::Relaxed, |counter| { + self.counter.try_update(Ordering::Relaxed, Ordering::Relaxed, |counter| { if counter == 0 { return None; } else { diff --git a/std/src/sys/sync/rwlock/futex.rs b/std/src/sys/sync/rwlock/futex.rs index 961819cae8d6e..0e8e954de0758 100644 --- a/std/src/sys/sync/rwlock/futex.rs +++ b/std/src/sys/sync/rwlock/futex.rs @@ -86,7 +86,7 @@ impl RwLock { #[inline] pub fn try_read(&self) -> bool { self.state - .fetch_update(Acquire, Relaxed, |s| is_read_lockable(s).then(|| s + READ_LOCKED)) + .try_update(Acquire, Relaxed, |s| is_read_lockable(s).then(|| s + READ_LOCKED)) .is_ok() } @@ -164,7 +164,7 @@ impl RwLock { #[inline] pub fn try_write(&self) -> bool { self.state - .fetch_update(Acquire, Relaxed, |s| is_unlocked(s).then(|| s + WRITE_LOCKED)) + .try_update(Acquire, Relaxed, |s| is_unlocked(s).then(|| s + WRITE_LOCKED)) .is_ok() } diff --git a/std/src/sys/sync/rwlock/queue.rs b/std/src/sys/sync/rwlock/queue.rs index 62f084acfd259..b41a65f7303b2 100644 --- a/std/src/sys/sync/rwlock/queue.rs +++ b/std/src/sys/sync/rwlock/queue.rs @@ -329,7 +329,7 @@ impl RwLock { #[inline] pub fn try_read(&self) -> bool { - self.state.fetch_update(Acquire, Relaxed, read_lock).is_ok() + self.state.try_update(Acquire, Relaxed, read_lock).is_ok() } #[inline] @@ -343,7 +343,7 @@ impl RwLock { pub fn try_write(&self) -> bool { // Atomically set the `LOCKED` bit. This is lowered to a single atomic instruction on most // modern processors (e.g. "lock bts" on x86 and "ldseta" on modern AArch64), and therefore - // is more efficient than `fetch_update(lock(true))`, which can spuriously fail if a new + // is more efficient than `try_update(lock(true))`, which can spuriously fail if a new // node is appended to the queue. self.state.fetch_or(LOCKED, Acquire).addr() & LOCKED == 0 } @@ -453,7 +453,7 @@ impl RwLock { #[inline] pub unsafe fn read_unlock(&self) { - match self.state.fetch_update(Release, Acquire, |state| { + match self.state.try_update(Release, Acquire, |state| { if state.addr() & QUEUED == 0 { // If there are no threads queued, simply decrement the reader count. let count = state.addr() - (SINGLE | LOCKED); diff --git a/std/src/sys/thread/unix.rs b/std/src/sys/thread/unix.rs index b758737d00c64..22f9bfef5a383 100644 --- a/std/src/sys/thread/unix.rs +++ b/std/src/sys/thread/unix.rs @@ -44,15 +44,6 @@ impl Thread { // unsafe: see thread::Builder::spawn_unchecked for safety requirements #[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces pub unsafe fn new(stack: usize, init: Box) -> io::Result { - // FIXME: remove this block once wasi-sdk is updated with the fix from - // https://github.com/WebAssembly/wasi-libc/pull/716 - // WASI does not support threading via pthreads. While wasi-libc provides - // pthread stubs, pthread_create returns EAGAIN, which causes confusing - // errors. We return UNSUPPORTED_PLATFORM directly instead. - if cfg!(all(target_os = "wasi", not(target_feature = "atomics"))) { - return Err(io::Error::UNSUPPORTED_PLATFORM); - } - let data = init; let mut attr: mem::MaybeUninit = mem::MaybeUninit::uninit(); assert_eq!(libc::pthread_attr_init(attr.as_mut_ptr()), 0); diff --git a/std/tests/env.rs b/std/tests/env.rs index b53fd69b7070b..9d624d5592ce7 100644 --- a/std/tests/env.rs +++ b/std/tests/env.rs @@ -59,6 +59,23 @@ fn split_paths_unix() { assert!(check_parse("/:/usr/local", &mut ["/", "/usr/local"])); } +#[test] +#[cfg(target_os = "uefi")] +fn split_paths_uefi() { + use std::path::PathBuf; + + fn check_parse(unparsed: &str, parsed: &[&str]) -> bool { + split_paths(unparsed).collect::>() + == parsed.iter().map(|s| PathBuf::from(*s)).collect::>() + } + + assert!(check_parse("", &mut [""])); + assert!(check_parse(";;", &mut ["", "", ""])); + assert!(check_parse(r"fs0:\", &mut [r"fs0:\"])); + assert!(check_parse(r"fs0:\;", &mut [r"fs0:\", ""])); + assert!(check_parse(r"fs0:\;fs0:\boot\", &mut [r"fs0:\", r"fs0:\boot\"])); +} + #[test] #[cfg(unix)] fn join_paths_unix() { diff --git a/std/tests/env_modify.rs b/std/tests/env_modify.rs index 4cd87bf7a0027..3404ca537acca 100644 --- a/std/tests/env_modify.rs +++ b/std/tests/env_modify.rs @@ -1,6 +1,5 @@ // These tests are in a separate integration test as they modify the environment, // and would otherwise cause some other tests to fail. -#![feature(cfg_select)] use std::env::*; use std::ffi::{OsStr, OsString}; diff --git a/std/tests/floats/f128.rs b/std/tests/floats/f128.rs deleted file mode 100644 index d20762023caf1..0000000000000 --- a/std/tests/floats/f128.rs +++ /dev/null @@ -1,320 +0,0 @@ -#![cfg(target_has_reliable_f128)] - -use std::f128::consts; -use std::ops::{Add, Div, Mul, Sub}; - -// Note these tolerances make sense around zero, but not for more extreme exponents. - -/// Default tolerances. Works for values that should be near precise but not exact. Roughly -/// the precision carried by `100 * 100`. -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -const TOL: f128 = 1e-12; - -/// For operations that are near exact, usually not involving math of different -/// signs. -const TOL_PRECISE: f128 = 1e-28; - -/// Tolerances for math that is allowed to be imprecise, usually due to multiple chained -/// operations. -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -const TOL_IMPR: f128 = 1e-10; - -/// Compare by representation -#[allow(unused_macros)] -macro_rules! assert_f128_biteq { - ($a:expr, $b:expr) => { - let (l, r): (&f128, &f128) = (&$a, &$b); - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l:?} is not bitequal to {r:?}.\na: {lb:#034x}\nb: {rb:#034x}"); - }; -} - -#[test] -fn test_num_f128() { - // FIXME(f128): replace with a `test_num` call once the required `fmodl`/`fmodf128` - // function is available on all platforms. - let ten = 10f128; - let two = 2f128; - assert_eq!(ten.add(two), ten + two); - assert_eq!(ten.sub(two), ten - two); - assert_eq!(ten.mul(two), ten * two); - assert_eq!(ten.div(two), ten / two); -} - -// Many math functions allow for less accurate results, so the next tolerance up is used - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_powf() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_eq!(1.0f128.powf(1.0), 1.0); - assert_approx_eq!(3.4f128.powf(4.5), 246.40818323761892815995637964326426756, TOL_IMPR); - assert_approx_eq!(2.7f128.powf(-3.2), 0.041652009108526178281070304373500889273, TOL_IMPR); - assert_approx_eq!((-3.1f128).powf(2.0), 9.6100000000000005506706202140776519387, TOL_IMPR); - assert_approx_eq!(5.9f128.powf(-2.0), 0.028727377190462507313100483690639638451, TOL_IMPR); - assert_eq!(8.3f128.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_exp() { - assert_eq!(1.0, 0.0f128.exp()); - assert_approx_eq!(consts::E, 1.0f128.exp(), TOL); - assert_approx_eq!(148.41315910257660342111558004055227962348775, 5.0f128.exp(), TOL); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_exp2() { - assert_eq!(32.0, 5.0f128.exp2()); - assert_eq!(1.0, 0.0f128.exp2()); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_ln() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_approx_eq!(1.0f128.exp().ln(), 1.0, TOL); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f128).ln().is_nan()); - assert_eq!((-0.0f128).ln(), neg_inf); - assert_eq!(0.0f128.ln(), neg_inf); - assert_approx_eq!(4.0f128.ln(), 1.3862943611198906188344642429163531366, TOL); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_log() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_eq!(10.0f128.log(10.0), 1.0); - assert_approx_eq!(2.3f128.log(3.5), 0.66485771361478710036766645911922010272, TOL); - assert_eq!(1.0f128.exp().log(1.0f128.exp()), 1.0); - assert!(1.0f128.log(1.0).is_nan()); - assert!(1.0f128.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f128).log(0.1).is_nan()); - assert_eq!((-0.0f128).log(2.0), neg_inf); - assert_eq!(0.0f128.log(7.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_log2() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_approx_eq!(10.0f128.log2(), 3.32192809488736234787031942948939017, TOL); - assert_approx_eq!(2.3f128.log2(), 1.2016338611696504130002982471978765921, TOL); - assert_approx_eq!(1.0f128.exp().log2(), 1.4426950408889634073599246810018921381, TOL); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f128).log2().is_nan()); - assert_eq!((-0.0f128).log2(), neg_inf); - assert_eq!(0.0f128.log2(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_log10() { - let nan: f128 = f128::NAN; - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - assert_eq!(10.0f128.log10(), 1.0); - assert_approx_eq!(2.3f128.log10(), 0.36172783601759284532595218865859309898, TOL); - assert_approx_eq!(1.0f128.exp().log10(), 0.43429448190325182765112891891660508222, TOL); - assert_eq!(1.0f128.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f128).log10().is_nan()); - assert_eq!((-0.0f128).log10(), neg_inf); - assert_eq!(0.0f128.log10(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_asinh() { - // Lower accuracy results are allowed, use increased tolerances - assert_eq!(0.0f128.asinh(), 0.0f128); - assert_eq!((-0.0f128).asinh(), -0.0f128); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f128).asinh().is_sign_negative()); - - // issue 63271 - assert_approx_eq!(2.0f128.asinh(), 1.443635475178810342493276740273105f128, TOL_IMPR); - assert_approx_eq!((-2.0f128).asinh(), -1.443635475178810342493276740273105f128, TOL_IMPR); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!( - (-67452098.07139316f128).asinh(), - -18.720075426274544393985484294000831757220, - TOL_IMPR - ); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f128, 60.0f128.sinh().asinh(), TOL_IMPR); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f128, 1e-15f128.sinh().asinh() * 1e15f128, TOL_IMPR); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_acosh() { - assert_eq!(1.0f128.acosh(), 0.0f128); - assert!(0.999f128.acosh().is_nan()); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f128.acosh(), 1.31695789692481670862504634730796844f128, TOL_IMPR); - assert_approx_eq!(3.0f128.acosh(), 1.76274717403908605046521864995958461f128, TOL_IMPR); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f128, 60.0f128.cosh().acosh(), TOL_IMPR); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_atanh() { - assert_eq!(0.0f128.atanh(), 0.0f128); - assert_eq!((-0.0f128).atanh(), -0.0f128); - - let inf: f128 = f128::INFINITY; - let neg_inf: f128 = f128::NEG_INFINITY; - let nan: f128 = f128::NAN; - assert_eq!(1.0f128.atanh(), inf); - assert_eq!((-1.0f128).atanh(), neg_inf); - assert!(2f128.atanh().atanh().is_nan()); - assert!((-2f128).atanh().atanh().is_nan()); - assert!(inf.atanh().is_nan()); - assert!(neg_inf.atanh().is_nan()); - assert!(nan.atanh().is_nan()); - assert_approx_eq!(0.5f128.atanh(), 0.54930614433405484569762261846126285f128, TOL_IMPR); - assert_approx_eq!((-0.5f128).atanh(), -0.54930614433405484569762261846126285f128, TOL_IMPR); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_gamma() { - // precision can differ among platforms - assert_approx_eq!(1.0f128.gamma(), 1.0f128, TOL_IMPR); - assert_approx_eq!(2.0f128.gamma(), 1.0f128, TOL_IMPR); - assert_approx_eq!(3.0f128.gamma(), 2.0f128, TOL_IMPR); - assert_approx_eq!(4.0f128.gamma(), 6.0f128, TOL_IMPR); - assert_approx_eq!(5.0f128.gamma(), 24.0f128, TOL_IMPR); - assert_approx_eq!(0.5f128.gamma(), consts::PI.sqrt(), TOL_IMPR); - assert_approx_eq!((-0.5f128).gamma(), -2.0 * consts::PI.sqrt(), TOL_IMPR); - assert_eq!(0.0f128.gamma(), f128::INFINITY); - assert_eq!((-0.0f128).gamma(), f128::NEG_INFINITY); - assert!((-1.0f128).gamma().is_nan()); - assert!((-2.0f128).gamma().is_nan()); - assert!(f128::NAN.gamma().is_nan()); - assert!(f128::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f128::INFINITY.gamma(), f128::INFINITY); - assert_eq!(1760.9f128.gamma(), f128::INFINITY); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f128_math)] -fn test_ln_gamma() { - assert_approx_eq!(1.0f128.ln_gamma().0, 0.0f128, TOL_IMPR); - assert_eq!(1.0f128.ln_gamma().1, 1); - assert_approx_eq!(2.0f128.ln_gamma().0, 0.0f128, TOL_IMPR); - assert_eq!(2.0f128.ln_gamma().1, 1); - assert_approx_eq!(3.0f128.ln_gamma().0, 2.0f128.ln(), TOL_IMPR); - assert_eq!(3.0f128.ln_gamma().1, 1); - assert_approx_eq!((-0.5f128).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln(), TOL_IMPR); - assert_eq!((-0.5f128).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f128 = consts::PI; - let frac_pi_2: f128 = consts::FRAC_PI_2; - let frac_pi_3: f128 = consts::FRAC_PI_3; - let frac_pi_4: f128 = consts::FRAC_PI_4; - let frac_pi_6: f128 = consts::FRAC_PI_6; - let frac_pi_8: f128 = consts::FRAC_PI_8; - let frac_1_pi: f128 = consts::FRAC_1_PI; - let frac_2_pi: f128 = consts::FRAC_2_PI; - - assert_approx_eq!(frac_pi_2, pi / 2f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_3, pi / 3f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_4, pi / 4f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_6, pi / 6f128, TOL_PRECISE); - assert_approx_eq!(frac_pi_8, pi / 8f128, TOL_PRECISE); - assert_approx_eq!(frac_1_pi, 1f128 / pi, TOL_PRECISE); - assert_approx_eq!(frac_2_pi, 2f128 / pi, TOL_PRECISE); - - #[cfg(not(miri))] - #[cfg(target_has_reliable_f128_math)] - { - let frac_2_sqrtpi: f128 = consts::FRAC_2_SQRT_PI; - let sqrt2: f128 = consts::SQRT_2; - let frac_1_sqrt2: f128 = consts::FRAC_1_SQRT_2; - let e: f128 = consts::E; - let log2_e: f128 = consts::LOG2_E; - let log10_e: f128 = consts::LOG10_E; - let ln_2: f128 = consts::LN_2; - let ln_10: f128 = consts::LN_10; - - assert_approx_eq!(frac_2_sqrtpi, 2f128 / pi.sqrt(), TOL_PRECISE); - assert_approx_eq!(sqrt2, 2f128.sqrt(), TOL_PRECISE); - assert_approx_eq!(frac_1_sqrt2, 1f128 / 2f128.sqrt(), TOL_PRECISE); - assert_approx_eq!(log2_e, e.log2(), TOL_PRECISE); - assert_approx_eq!(log10_e, e.log10(), TOL_PRECISE); - assert_approx_eq!(ln_2, 2f128.ln(), TOL_PRECISE); - assert_approx_eq!(ln_10, 10f128.ln(), TOL_PRECISE); - } -} diff --git a/std/tests/floats/f16.rs b/std/tests/floats/f16.rs deleted file mode 100644 index cc0960765f411..0000000000000 --- a/std/tests/floats/f16.rs +++ /dev/null @@ -1,297 +0,0 @@ -#![cfg(target_has_reliable_f16)] - -use std::f16::consts; - -/// Tolerance for results on the order of 10.0e-2 -#[allow(unused)] -const TOL_N2: f16 = 0.0001; - -/// Tolerance for results on the order of 10.0e+0 -#[allow(unused)] -const TOL_0: f16 = 0.01; - -/// Tolerance for results on the order of 10.0e+2 -#[allow(unused)] -const TOL_P2: f16 = 0.5; - -/// Tolerance for results on the order of 10.0e+4 -#[allow(unused)] -const TOL_P4: f16 = 10.0; - -/// Compare by representation -#[allow(unused_macros)] -macro_rules! assert_f16_biteq { - ($a:expr, $b:expr) => { - let (l, r): (&f16, &f16) = (&$a, &$b); - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l:?} ({lb:#04x}) is not bitequal to {r:?} ({rb:#04x})"); - }; -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_powf() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_eq!(1.0f16.powf(1.0), 1.0); - assert_approx_eq!(3.4f16.powf(4.5), 246.408183, TOL_P2); - assert_approx_eq!(2.7f16.powf(-3.2), 0.041652, TOL_N2); - assert_approx_eq!((-3.1f16).powf(2.0), 9.61, TOL_P2); - assert_approx_eq!(5.9f16.powf(-2.0), 0.028727, TOL_N2); - assert_eq!(8.3f16.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_exp() { - assert_eq!(1.0, 0.0f16.exp()); - assert_approx_eq!(2.718282, 1.0f16.exp(), TOL_0); - assert_approx_eq!(148.413159, 5.0f16.exp(), TOL_0); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_exp2() { - assert_eq!(32.0, 5.0f16.exp2()); - assert_eq!(1.0, 0.0f16.exp2()); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_ln() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_approx_eq!(1.0f16.exp().ln(), 1.0, TOL_0); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f16).ln().is_nan()); - assert_eq!((-0.0f16).ln(), neg_inf); - assert_eq!(0.0f16.ln(), neg_inf); - assert_approx_eq!(4.0f16.ln(), 1.386294, TOL_0); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_log() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_eq!(10.0f16.log(10.0), 1.0); - assert_approx_eq!(2.3f16.log(3.5), 0.664858, TOL_0); - assert_eq!(1.0f16.exp().log(1.0f16.exp()), 1.0); - assert!(1.0f16.log(1.0).is_nan()); - assert!(1.0f16.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f16).log(0.1).is_nan()); - assert_eq!((-0.0f16).log(2.0), neg_inf); - assert_eq!(0.0f16.log(7.0), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_log2() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_approx_eq!(10.0f16.log2(), 3.321928, TOL_0); - assert_approx_eq!(2.3f16.log2(), 1.201634, TOL_0); - assert_approx_eq!(1.0f16.exp().log2(), 1.442695, TOL_0); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f16).log2().is_nan()); - assert_eq!((-0.0f16).log2(), neg_inf); - assert_eq!(0.0f16.log2(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_log10() { - let nan: f16 = f16::NAN; - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - assert_eq!(10.0f16.log10(), 1.0); - assert_approx_eq!(2.3f16.log10(), 0.361728, TOL_0); - assert_approx_eq!(1.0f16.exp().log10(), 0.434294, TOL_0); - assert_eq!(1.0f16.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f16).log10().is_nan()); - assert_eq!((-0.0f16).log10(), neg_inf); - assert_eq!(0.0f16.log10(), neg_inf); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_asinh() { - assert_eq!(0.0f16.asinh(), 0.0f16); - assert_eq!((-0.0f16).asinh(), -0.0f16); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f16).asinh().is_sign_negative()); - // issue 63271 - assert_approx_eq!(2.0f16.asinh(), 1.443635475178810342493276740273105f16, TOL_0); - assert_approx_eq!((-2.0f16).asinh(), -1.443635475178810342493276740273105f16, TOL_0); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!((-200.0f16).asinh(), -5.991470797049389, TOL_0); - - // test for low accuracy from issue 104548 - assert_approx_eq!(10.0f16, 10.0f16.sinh().asinh(), TOL_0); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f16, 1e-3f16.sinh().asinh() * 1e3f16, TOL_0); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_acosh() { - assert_eq!(1.0f16.acosh(), 0.0f16); - assert!(0.999f16.acosh().is_nan()); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f16.acosh(), 1.31695789692481670862504634730796844f16, TOL_0); - assert_approx_eq!(3.0f16.acosh(), 1.76274717403908605046521864995958461f16, TOL_0); - - // test for low accuracy from issue 104548 - assert_approx_eq!(10.0f16, 10.0f16.cosh().acosh(), TOL_P2); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_atanh() { - assert_eq!(0.0f16.atanh(), 0.0f16); - assert_eq!((-0.0f16).atanh(), -0.0f16); - - let inf: f16 = f16::INFINITY; - let neg_inf: f16 = f16::NEG_INFINITY; - let nan: f16 = f16::NAN; - assert_eq!(1.0f16.atanh(), inf); - assert_eq!((-1.0f16).atanh(), neg_inf); - assert!(2f16.atanh().atanh().is_nan()); - assert!((-2f16).atanh().atanh().is_nan()); - assert!(inf.atanh().is_nan()); - assert!(neg_inf.atanh().is_nan()); - assert!(nan.atanh().is_nan()); - assert_approx_eq!(0.5f16.atanh(), 0.54930614433405484569762261846126285f16, TOL_0); - assert_approx_eq!((-0.5f16).atanh(), -0.54930614433405484569762261846126285f16, TOL_0); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_gamma() { - // precision can differ among platforms - assert_approx_eq!(1.0f16.gamma(), 1.0f16, TOL_0); - assert_approx_eq!(2.0f16.gamma(), 1.0f16, TOL_0); - assert_approx_eq!(3.0f16.gamma(), 2.0f16, TOL_0); - assert_approx_eq!(4.0f16.gamma(), 6.0f16, TOL_0); - assert_approx_eq!(5.0f16.gamma(), 24.0f16, TOL_0); - assert_approx_eq!(0.5f16.gamma(), consts::PI.sqrt(), TOL_0); - assert_approx_eq!((-0.5f16).gamma(), -2.0 * consts::PI.sqrt(), TOL_0); - assert_eq!(0.0f16.gamma(), f16::INFINITY); - assert_eq!((-0.0f16).gamma(), f16::NEG_INFINITY); - assert!((-1.0f16).gamma().is_nan()); - assert!((-2.0f16).gamma().is_nan()); - assert!(f16::NAN.gamma().is_nan()); - assert!(f16::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f16::INFINITY.gamma(), f16::INFINITY); - assert_eq!(171.71f16.gamma(), f16::INFINITY); -} - -#[test] -#[cfg(not(miri))] -#[cfg(target_has_reliable_f16_math)] -fn test_ln_gamma() { - assert_approx_eq!(1.0f16.ln_gamma().0, 0.0f16, TOL_0); - assert_eq!(1.0f16.ln_gamma().1, 1); - assert_approx_eq!(2.0f16.ln_gamma().0, 0.0f16, TOL_0); - assert_eq!(2.0f16.ln_gamma().1, 1); - assert_approx_eq!(3.0f16.ln_gamma().0, 2.0f16.ln(), TOL_0); - assert_eq!(3.0f16.ln_gamma().1, 1); - assert_approx_eq!((-0.5f16).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln(), TOL_0); - assert_eq!((-0.5f16).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f16 = consts::PI; - let frac_pi_2: f16 = consts::FRAC_PI_2; - let frac_pi_3: f16 = consts::FRAC_PI_3; - let frac_pi_4: f16 = consts::FRAC_PI_4; - let frac_pi_6: f16 = consts::FRAC_PI_6; - let frac_pi_8: f16 = consts::FRAC_PI_8; - let frac_1_pi: f16 = consts::FRAC_1_PI; - let frac_2_pi: f16 = consts::FRAC_2_PI; - - assert_approx_eq!(frac_pi_2, pi / 2f16, TOL_0); - assert_approx_eq!(frac_pi_3, pi / 3f16, TOL_0); - assert_approx_eq!(frac_pi_4, pi / 4f16, TOL_0); - assert_approx_eq!(frac_pi_6, pi / 6f16, TOL_0); - assert_approx_eq!(frac_pi_8, pi / 8f16, TOL_0); - assert_approx_eq!(frac_1_pi, 1f16 / pi, TOL_0); - assert_approx_eq!(frac_2_pi, 2f16 / pi, TOL_0); - - #[cfg(not(miri))] - #[cfg(target_has_reliable_f16_math)] - { - let frac_2_sqrtpi: f16 = consts::FRAC_2_SQRT_PI; - let sqrt2: f16 = consts::SQRT_2; - let frac_1_sqrt2: f16 = consts::FRAC_1_SQRT_2; - let e: f16 = consts::E; - let log2_e: f16 = consts::LOG2_E; - let log10_e: f16 = consts::LOG10_E; - let ln_2: f16 = consts::LN_2; - let ln_10: f16 = consts::LN_10; - - assert_approx_eq!(frac_2_sqrtpi, 2f16 / pi.sqrt(), TOL_0); - assert_approx_eq!(sqrt2, 2f16.sqrt(), TOL_0); - assert_approx_eq!(frac_1_sqrt2, 1f16 / 2f16.sqrt(), TOL_0); - assert_approx_eq!(log2_e, e.log2(), TOL_0); - assert_approx_eq!(log10_e, e.log10(), TOL_0); - assert_approx_eq!(ln_2, 2f16.ln(), TOL_0); - assert_approx_eq!(ln_10, 10f16.ln(), TOL_0); - } -} diff --git a/std/tests/floats/f32.rs b/std/tests/floats/f32.rs deleted file mode 100644 index 3acd067091415..0000000000000 --- a/std/tests/floats/f32.rs +++ /dev/null @@ -1,258 +0,0 @@ -use std::f32::consts; - -/// Miri adds some extra errors to float functions; make sure the tests still pass. -/// These values are purely used as a canary to test against and are thus not a stable guarantee Rust provides. -/// They serve as a way to get an idea of the real precision of floating point operations on different platforms. -const APPROX_DELTA: f32 = if cfg!(miri) { 1e-3 } else { 1e-6 }; - -#[allow(unused_macros)] -macro_rules! assert_f32_biteq { - ($left : expr, $right : expr) => { - let l: &f32 = &$left; - let r: &f32 = &$right; - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l} ({lb:#010x}) is not bitequal to {r} ({rb:#010x})"); - }; -} - -#[test] -fn test_powf() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_eq!(1.0f32.powf(1.0), 1.0); - assert_approx_eq!(3.4f32.powf(4.5), 246.408218, APPROX_DELTA); - assert_approx_eq!(2.7f32.powf(-3.2), 0.041652); - assert_approx_eq!((-3.1f32).powf(2.0), 9.61, APPROX_DELTA); - assert_approx_eq!(5.9f32.powf(-2.0), 0.028727); - assert_eq!(8.3f32.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -fn test_exp() { - assert_eq!(1.0, 0.0f32.exp()); - assert_approx_eq!(2.718282, 1.0f32.exp(), APPROX_DELTA); - assert_approx_eq!(148.413162, 5.0f32.exp(), APPROX_DELTA); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -fn test_exp2() { - assert_approx_eq!(32.0, 5.0f32.exp2(), APPROX_DELTA); - assert_eq!(1.0, 0.0f32.exp2()); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -fn test_ln() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(1.0f32.exp().ln(), 1.0); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f32).ln().is_nan()); - assert_eq!((-0.0f32).ln(), neg_inf); - assert_eq!(0.0f32.ln(), neg_inf); - assert_approx_eq!(4.0f32.ln(), 1.386294, APPROX_DELTA); -} - -#[test] -fn test_log() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(10.0f32.log(10.0), 1.0); - assert_approx_eq!(2.3f32.log(3.5), 0.664858); - assert_approx_eq!(1.0f32.exp().log(1.0f32.exp()), 1.0, APPROX_DELTA); - assert!(1.0f32.log(1.0).is_nan()); - assert!(1.0f32.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f32).log(0.1).is_nan()); - assert_eq!((-0.0f32).log(2.0), neg_inf); - assert_eq!(0.0f32.log(7.0), neg_inf); -} - -#[test] -fn test_log2() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(10.0f32.log2(), 3.321928, APPROX_DELTA); - assert_approx_eq!(2.3f32.log2(), 1.201634); - assert_approx_eq!(1.0f32.exp().log2(), 1.442695, APPROX_DELTA); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f32).log2().is_nan()); - assert_eq!((-0.0f32).log2(), neg_inf); - assert_eq!(0.0f32.log2(), neg_inf); -} - -#[test] -fn test_log10() { - let nan: f32 = f32::NAN; - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - assert_approx_eq!(10.0f32.log10(), 1.0); - assert_approx_eq!(2.3f32.log10(), 0.361728); - assert_approx_eq!(1.0f32.exp().log10(), 0.434294); - assert_eq!(1.0f32.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f32).log10().is_nan()); - assert_eq!((-0.0f32).log10(), neg_inf); - assert_eq!(0.0f32.log10(), neg_inf); -} - -#[test] -fn test_asinh() { - assert_eq!(0.0f32.asinh(), 0.0f32); - assert_eq!((-0.0f32).asinh(), -0.0f32); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f32).asinh().is_sign_negative()); // issue 63271 - assert_approx_eq!(2.0f32.asinh(), 1.443635475178810342493276740273105f32); - assert_approx_eq!((-2.0f32).asinh(), -1.443635475178810342493276740273105f32); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!((-3000.0f32).asinh(), -8.699514775987968673236893537700647f32, APPROX_DELTA); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f32, 60.0f32.sinh().asinh(), APPROX_DELTA); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f32, 1e-15f32.sinh().asinh() * 1e15f32); -} - -#[test] -fn test_acosh() { - assert_eq!(1.0f32.acosh(), 0.0f32); - assert!(0.999f32.acosh().is_nan()); - - let inf: f32 = f32::INFINITY; - let neg_inf: f32 = f32::NEG_INFINITY; - let nan: f32 = f32::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f32.acosh(), 1.31695789692481670862504634730796844f32); - assert_approx_eq!(3.0f32.acosh(), 1.76274717403908605046521864995958461f32); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f32, 60.0f32.cosh().acosh(), APPROX_DELTA); -} - -#[test] -fn test_atanh() { - assert_eq!(0.0f32.atanh(), 0.0f32); - assert_eq!((-0.0f32).atanh(), -0.0f32); - - let inf32: f32 = f32::INFINITY; - let neg_inf32: f32 = f32::NEG_INFINITY; - assert_eq!(1.0f32.atanh(), inf32); - assert_eq!((-1.0f32).atanh(), neg_inf32); - - assert!(2f64.atanh().atanh().is_nan()); - assert!((-2f64).atanh().atanh().is_nan()); - - let inf64: f32 = f32::INFINITY; - let neg_inf64: f32 = f32::NEG_INFINITY; - let nan32: f32 = f32::NAN; - assert!(inf64.atanh().is_nan()); - assert!(neg_inf64.atanh().is_nan()); - assert!(nan32.atanh().is_nan()); - - assert_approx_eq!(0.5f32.atanh(), 0.54930614433405484569762261846126285f32); - assert_approx_eq!((-0.5f32).atanh(), -0.54930614433405484569762261846126285f32); -} - -#[test] -fn test_gamma() { - // precision can differ between platforms - assert_approx_eq!(1.0f32.gamma(), 1.0f32, APPROX_DELTA); - assert_approx_eq!(2.0f32.gamma(), 1.0f32, APPROX_DELTA); - assert_approx_eq!(3.0f32.gamma(), 2.0f32, APPROX_DELTA); - assert_approx_eq!(4.0f32.gamma(), 6.0f32, APPROX_DELTA); - assert_approx_eq!(5.0f32.gamma(), 24.0f32, APPROX_DELTA); - assert_approx_eq!(0.5f32.gamma(), consts::PI.sqrt(), APPROX_DELTA); - assert_approx_eq!((-0.5f32).gamma(), -2.0 * consts::PI.sqrt(), APPROX_DELTA); - assert_eq!(0.0f32.gamma(), f32::INFINITY); - assert_eq!((-0.0f32).gamma(), f32::NEG_INFINITY); - assert!((-1.0f32).gamma().is_nan()); - assert!((-2.0f32).gamma().is_nan()); - assert!(f32::NAN.gamma().is_nan()); - assert!(f32::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f32::INFINITY.gamma(), f32::INFINITY); - assert_eq!(171.71f32.gamma(), f32::INFINITY); -} - -#[test] -fn test_ln_gamma() { - assert_approx_eq!(1.0f32.ln_gamma().0, 0.0f32); - assert_eq!(1.0f32.ln_gamma().1, 1); - assert_approx_eq!(2.0f32.ln_gamma().0, 0.0f32); - assert_eq!(2.0f32.ln_gamma().1, 1); - assert_approx_eq!(3.0f32.ln_gamma().0, 2.0f32.ln()); - assert_eq!(3.0f32.ln_gamma().1, 1); - assert_approx_eq!((-0.5f32).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln(), APPROX_DELTA); - assert_eq!((-0.5f32).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f32 = consts::PI; - let frac_pi_2: f32 = consts::FRAC_PI_2; - let frac_pi_3: f32 = consts::FRAC_PI_3; - let frac_pi_4: f32 = consts::FRAC_PI_4; - let frac_pi_6: f32 = consts::FRAC_PI_6; - let frac_pi_8: f32 = consts::FRAC_PI_8; - let frac_1_pi: f32 = consts::FRAC_1_PI; - let frac_2_pi: f32 = consts::FRAC_2_PI; - let frac_2_sqrtpi: f32 = consts::FRAC_2_SQRT_PI; - let sqrt2: f32 = consts::SQRT_2; - let frac_1_sqrt2: f32 = consts::FRAC_1_SQRT_2; - let e: f32 = consts::E; - let log2_e: f32 = consts::LOG2_E; - let log10_e: f32 = consts::LOG10_E; - let ln_2: f32 = consts::LN_2; - let ln_10: f32 = consts::LN_10; - - assert_approx_eq!(frac_pi_2, pi / 2f32); - assert_approx_eq!(frac_pi_3, pi / 3f32, APPROX_DELTA); - assert_approx_eq!(frac_pi_4, pi / 4f32); - assert_approx_eq!(frac_pi_6, pi / 6f32); - assert_approx_eq!(frac_pi_8, pi / 8f32); - assert_approx_eq!(frac_1_pi, 1f32 / pi); - assert_approx_eq!(frac_2_pi, 2f32 / pi); - assert_approx_eq!(frac_2_sqrtpi, 2f32 / pi.sqrt()); - assert_approx_eq!(sqrt2, 2f32.sqrt()); - assert_approx_eq!(frac_1_sqrt2, 1f32 / 2f32.sqrt()); - assert_approx_eq!(log2_e, e.log2()); - assert_approx_eq!(log10_e, e.log10()); - assert_approx_eq!(ln_2, 2f32.ln()); - assert_approx_eq!(ln_10, 10f32.ln(), APPROX_DELTA); -} diff --git a/std/tests/floats/f64.rs b/std/tests/floats/f64.rs deleted file mode 100644 index fccf20097278b..0000000000000 --- a/std/tests/floats/f64.rs +++ /dev/null @@ -1,249 +0,0 @@ -use std::f64::consts; - -#[allow(unused_macros)] -macro_rules! assert_f64_biteq { - ($left : expr, $right : expr) => { - let l: &f64 = &$left; - let r: &f64 = &$right; - let lb = l.to_bits(); - let rb = r.to_bits(); - assert_eq!(lb, rb, "float {l} ({lb:#018x}) is not bitequal to {r} ({rb:#018x})"); - }; -} - -#[test] -fn test_powf() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_eq!(1.0f64.powf(1.0), 1.0); - assert_approx_eq!(3.4f64.powf(4.5), 246.408183); - assert_approx_eq!(2.7f64.powf(-3.2), 0.041652); - assert_approx_eq!((-3.1f64).powf(2.0), 9.61); - assert_approx_eq!(5.9f64.powf(-2.0), 0.028727); - assert_eq!(8.3f64.powf(0.0), 1.0); - assert!(nan.powf(2.0).is_nan()); - assert_eq!(inf.powf(2.0), inf); - assert_eq!(neg_inf.powf(3.0), neg_inf); -} - -#[test] -fn test_exp() { - assert_eq!(1.0, 0.0f64.exp()); - assert_approx_eq!(2.718282, 1.0f64.exp()); - assert_approx_eq!(148.413159, 5.0f64.exp()); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf, inf.exp()); - assert_eq!(0.0, neg_inf.exp()); - assert!(nan.exp().is_nan()); -} - -#[test] -fn test_exp2() { - assert_approx_eq!(32.0, 5.0f64.exp2()); - assert_eq!(1.0, 0.0f64.exp2()); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf, inf.exp2()); - assert_eq!(0.0, neg_inf.exp2()); - assert!(nan.exp2().is_nan()); -} - -#[test] -fn test_ln() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(1.0f64.exp().ln(), 1.0); - assert!(nan.ln().is_nan()); - assert_eq!(inf.ln(), inf); - assert!(neg_inf.ln().is_nan()); - assert!((-2.3f64).ln().is_nan()); - assert_eq!((-0.0f64).ln(), neg_inf); - assert_eq!(0.0f64.ln(), neg_inf); - assert_approx_eq!(4.0f64.ln(), 1.386294); -} - -#[test] -fn test_log() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(10.0f64.log(10.0), 1.0); - assert_approx_eq!(2.3f64.log(3.5), 0.664858); - assert_approx_eq!(1.0f64.exp().log(1.0f64.exp()), 1.0); - assert!(1.0f64.log(1.0).is_nan()); - assert!(1.0f64.log(-13.9).is_nan()); - assert!(nan.log(2.3).is_nan()); - assert_eq!(inf.log(10.0), inf); - assert!(neg_inf.log(8.8).is_nan()); - assert!((-2.3f64).log(0.1).is_nan()); - assert_eq!((-0.0f64).log(2.0), neg_inf); - assert_eq!(0.0f64.log(7.0), neg_inf); -} - -#[test] -fn test_log2() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(10.0f64.log2(), 3.321928); - assert_approx_eq!(2.3f64.log2(), 1.201634); - assert_approx_eq!(1.0f64.exp().log2(), 1.442695); - assert!(nan.log2().is_nan()); - assert_eq!(inf.log2(), inf); - assert!(neg_inf.log2().is_nan()); - assert!((-2.3f64).log2().is_nan()); - assert_eq!((-0.0f64).log2(), neg_inf); - assert_eq!(0.0f64.log2(), neg_inf); -} - -#[test] -fn test_log10() { - let nan: f64 = f64::NAN; - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - assert_approx_eq!(10.0f64.log10(), 1.0); - assert_approx_eq!(2.3f64.log10(), 0.361728); - assert_approx_eq!(1.0f64.exp().log10(), 0.434294); - assert_eq!(1.0f64.log10(), 0.0); - assert!(nan.log10().is_nan()); - assert_eq!(inf.log10(), inf); - assert!(neg_inf.log10().is_nan()); - assert!((-2.3f64).log10().is_nan()); - assert_eq!((-0.0f64).log10(), neg_inf); - assert_eq!(0.0f64.log10(), neg_inf); -} - -#[test] -fn test_asinh() { - assert_eq!(0.0f64.asinh(), 0.0f64); - assert_eq!((-0.0f64).asinh(), -0.0f64); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf.asinh(), inf); - assert_eq!(neg_inf.asinh(), neg_inf); - assert!(nan.asinh().is_nan()); - assert!((-0.0f64).asinh().is_sign_negative()); - // issue 63271 - assert_approx_eq!(2.0f64.asinh(), 1.443635475178810342493276740273105f64); - assert_approx_eq!((-2.0f64).asinh(), -1.443635475178810342493276740273105f64); - // regression test for the catastrophic cancellation fixed in 72486 - assert_approx_eq!((-67452098.07139316f64).asinh(), -18.72007542627454439398548429400083); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f64, 60.0f64.sinh().asinh()); - // mul needed for approximate comparison to be meaningful - assert_approx_eq!(1.0f64, 1e-15f64.sinh().asinh() * 1e15f64); -} - -#[test] -fn test_acosh() { - assert_eq!(1.0f64.acosh(), 0.0f64); - assert!(0.999f64.acosh().is_nan()); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(inf.acosh(), inf); - assert!(neg_inf.acosh().is_nan()); - assert!(nan.acosh().is_nan()); - assert_approx_eq!(2.0f64.acosh(), 1.31695789692481670862504634730796844f64); - assert_approx_eq!(3.0f64.acosh(), 1.76274717403908605046521864995958461f64); - - // test for low accuracy from issue 104548 - assert_approx_eq!(60.0f64, 60.0f64.cosh().acosh()); -} - -#[test] -fn test_atanh() { - assert_eq!(0.0f64.atanh(), 0.0f64); - assert_eq!((-0.0f64).atanh(), -0.0f64); - - let inf: f64 = f64::INFINITY; - let neg_inf: f64 = f64::NEG_INFINITY; - let nan: f64 = f64::NAN; - assert_eq!(1.0f64.atanh(), inf); - assert_eq!((-1.0f64).atanh(), neg_inf); - assert!(2f64.atanh().atanh().is_nan()); - assert!((-2f64).atanh().atanh().is_nan()); - assert!(inf.atanh().is_nan()); - assert!(neg_inf.atanh().is_nan()); - assert!(nan.atanh().is_nan()); - assert_approx_eq!(0.5f64.atanh(), 0.54930614433405484569762261846126285f64); - assert_approx_eq!((-0.5f64).atanh(), -0.54930614433405484569762261846126285f64); -} - -#[test] -fn test_gamma() { - // precision can differ between platforms - assert_approx_eq!(1.0f64.gamma(), 1.0f64); - assert_approx_eq!(2.0f64.gamma(), 1.0f64); - assert_approx_eq!(3.0f64.gamma(), 2.0f64); - assert_approx_eq!(4.0f64.gamma(), 6.0f64); - assert_approx_eq!(5.0f64.gamma(), 24.0f64); - assert_approx_eq!(0.5f64.gamma(), consts::PI.sqrt()); - assert_approx_eq!((-0.5f64).gamma(), -2.0 * consts::PI.sqrt()); - assert_eq!(0.0f64.gamma(), f64::INFINITY); - assert_eq!((-0.0f64).gamma(), f64::NEG_INFINITY); - assert!((-1.0f64).gamma().is_nan()); - assert!((-2.0f64).gamma().is_nan()); - assert!(f64::NAN.gamma().is_nan()); - assert!(f64::NEG_INFINITY.gamma().is_nan()); - assert_eq!(f64::INFINITY.gamma(), f64::INFINITY); - assert_eq!(171.71f64.gamma(), f64::INFINITY); -} - -#[test] -fn test_ln_gamma() { - assert_approx_eq!(1.0f64.ln_gamma().0, 0.0f64); - assert_eq!(1.0f64.ln_gamma().1, 1); - assert_approx_eq!(2.0f64.ln_gamma().0, 0.0f64); - assert_eq!(2.0f64.ln_gamma().1, 1); - assert_approx_eq!(3.0f64.ln_gamma().0, 2.0f64.ln()); - assert_eq!(3.0f64.ln_gamma().1, 1); - assert_approx_eq!((-0.5f64).ln_gamma().0, (2.0 * consts::PI.sqrt()).ln()); - assert_eq!((-0.5f64).ln_gamma().1, -1); -} - -#[test] -fn test_real_consts() { - let pi: f64 = consts::PI; - let frac_pi_2: f64 = consts::FRAC_PI_2; - let frac_pi_3: f64 = consts::FRAC_PI_3; - let frac_pi_4: f64 = consts::FRAC_PI_4; - let frac_pi_6: f64 = consts::FRAC_PI_6; - let frac_pi_8: f64 = consts::FRAC_PI_8; - let frac_1_pi: f64 = consts::FRAC_1_PI; - let frac_2_pi: f64 = consts::FRAC_2_PI; - let frac_2_sqrtpi: f64 = consts::FRAC_2_SQRT_PI; - let sqrt2: f64 = consts::SQRT_2; - let frac_1_sqrt2: f64 = consts::FRAC_1_SQRT_2; - let e: f64 = consts::E; - let log2_e: f64 = consts::LOG2_E; - let log10_e: f64 = consts::LOG10_E; - let ln_2: f64 = consts::LN_2; - let ln_10: f64 = consts::LN_10; - - assert_approx_eq!(frac_pi_2, pi / 2f64); - assert_approx_eq!(frac_pi_3, pi / 3f64); - assert_approx_eq!(frac_pi_4, pi / 4f64); - assert_approx_eq!(frac_pi_6, pi / 6f64); - assert_approx_eq!(frac_pi_8, pi / 8f64); - assert_approx_eq!(frac_1_pi, 1f64 / pi); - assert_approx_eq!(frac_2_pi, 2f64 / pi); - assert_approx_eq!(frac_2_sqrtpi, 2f64 / pi.sqrt()); - assert_approx_eq!(sqrt2, 2f64.sqrt()); - assert_approx_eq!(frac_1_sqrt2, 1f64 / 2f64.sqrt()); - assert_approx_eq!(log2_e, e.log2()); - assert_approx_eq!(log10_e, e.log10()); - assert_approx_eq!(ln_2, 2f64.ln()); - assert_approx_eq!(ln_10, 10f64.ln()); -} diff --git a/std/tests/floats/lib.rs b/std/tests/floats/lib.rs deleted file mode 100644 index 8bb8eb4bfc1ae..0000000000000 --- a/std/tests/floats/lib.rs +++ /dev/null @@ -1,43 +0,0 @@ -#![feature(f16, f128, float_gamma, float_minimum_maximum, cfg_target_has_reliable_f16_f128)] -#![expect(internal_features)] // for reliable_f16_f128 - -use std::fmt; -use std::ops::{Add, Div, Mul, Rem, Sub}; - -/// Verify that floats are within a tolerance of each other, 1.0e-6 by default. -macro_rules! assert_approx_eq { - ($a:expr, $b:expr) => {{ assert_approx_eq!($a, $b, 1.0e-6) }}; - ($a:expr, $b:expr, $lim:expr) => {{ - let (a, b) = (&$a, &$b); - let diff = (*a - *b).abs(); - assert!( - diff <= $lim, - "{a:?} is not approximately equal to {b:?} (threshold {lim:?}, difference {diff:?})", - lim = $lim - ); - }}; -} - -/// Helper function for testing numeric operations -pub fn test_num(ten: T, two: T) -where - T: PartialEq - + Add - + Sub - + Mul - + Div - + Rem - + fmt::Debug - + Copy, -{ - assert_eq!(ten.add(two), ten + two); - assert_eq!(ten.sub(two), ten - two); - assert_eq!(ten.mul(two), ten * two); - assert_eq!(ten.div(two), ten / two); - assert_eq!(ten.rem(two), ten % two); -} - -mod f128; -mod f16; -mod f32; -mod f64; diff --git a/std/tests/path.rs b/std/tests/path.rs index 4094b7acd8749..8997b8ad192dc 100644 --- a/std/tests/path.rs +++ b/std/tests/path.rs @@ -2291,6 +2291,26 @@ fn display_format_flags() { assert_eq!(format!("a{:#<5}b", Path::new("a").display()), "aa####b"); } +#[test] +fn display_path_with_padding_no_align() { + assert_eq!(format!("{:10}", Path::new("/foo/bar").display()), "/foo/bar "); +} + +#[test] +fn display_path_with_padding_align_left() { + assert_eq!(format!("{:<10}", Path::new("/foo/bar").display()), "/foo/bar "); +} + +#[test] +fn display_path_with_padding_align_right() { + assert_eq!(format!("{:>10}", Path::new("/foo/bar").display()), " /foo/bar"); +} + +#[test] +fn display_path_with_padding_align_center() { + assert_eq!(format!("{:^10}", Path::new("/foo/bar").display()), " /foo/bar "); +} + #[test] fn into_rc() { let orig = "hello/world"; diff --git a/std/tests/sync/oneshot.rs b/std/tests/sync/oneshot.rs index 6a87c72b9cb5b..6eaacfbc6497d 100644 --- a/std/tests/sync/oneshot.rs +++ b/std/tests/sync/oneshot.rs @@ -89,15 +89,15 @@ fn send_before_recv_timeout() { assert!(sender.send(22i128).is_ok()); - let start = Instant::now(); - let timeout = Duration::from_secs(1); match receiver.recv_timeout(timeout) { Ok(22) => {} _ => panic!("expected Ok(22)"), } - assert!(start.elapsed() < timeout); + // FIXME(#152648): There previously was a timing assertion here. + // This was removed, because under load there's no guarantee that the main thread is + // scheduled and run before `timeout` expires } #[test] @@ -127,6 +127,7 @@ fn recv_before_send() { } #[test] +#[ignore = "Inherently flaky and has caused several CI failures"] fn recv_timeout_before_send() { let (sender, receiver) = oneshot::channel(); @@ -135,6 +136,8 @@ fn recv_timeout_before_send() { sender.send(99u128).unwrap(); }); + // FIXME(#152145): Under load, there's no guarantee that thread `t` has + // ever been scheduled and run before this timeout expires. match receiver.recv_timeout(Duration::from_secs(1)) { Ok(99) => {} _ => panic!("expected Ok(99)"), @@ -240,7 +243,9 @@ fn recv_deadline_passed() { } assert!(start.elapsed() >= timeout); - assert!(start.elapsed() < timeout * 3); + // FIXME(#152878): An upper-bound assertion on the elapsed time was removed, + // because CI runners can starve individual threads for a surprisingly long + // time, leading to flaky failures. } #[test] @@ -249,12 +254,16 @@ fn recv_time_passed() { let start = Instant::now(); let timeout = Duration::from_millis(100); + match receiver.recv_timeout(timeout) { Err(RecvTimeoutError::Timeout(_)) => {} _ => panic!("expected timeout error"), } + assert!(start.elapsed() >= timeout); - assert!(start.elapsed() < timeout * 3); + // FIXME(#152878): An upper-bound assertion on the elapsed time was removed, + // because CI runners can starve individual threads for a surprisingly long + // time, leading to flaky failures. } #[test] diff --git a/std/tests/volatile-fat-ptr.rs b/std/tests/volatile-fat-ptr.rs index b005c12c6187b..406eb7c80afb5 100644 --- a/std/tests/volatile-fat-ptr.rs +++ b/std/tests/volatile-fat-ptr.rs @@ -1,6 +1,3 @@ -#![allow(stable_features)] -#![feature(volatile)] - use std::ptr::{read_volatile, write_volatile}; #[test] diff --git a/std/tests/windows_unix_socket.rs b/std/tests/windows_unix_socket.rs index 1f20cf586ca25..1d16ec9ed8414 100644 --- a/std/tests/windows_unix_socket.rs +++ b/std/tests/windows_unix_socket.rs @@ -5,10 +5,24 @@ // in the future, will test both unix and windows uds use std::io::{Read, Write}; use std::os::windows::net::{UnixListener, UnixStream}; -use std::thread; +use std::{mem, thread}; + +macro_rules! skip_nonapplicable_oses { + () => { + // UDS have been available under Windows since Insider Preview Build + // 17063. "Redstone 4" (RS4, version 1803, build number 17134) is + // therefore the first official release to include it. + if !is_windows_10_v1803_or_greater() { + println!("Not running this test on too-old Windows."); + return; + } + }; +} #[test] fn win_uds_smoke_bind_connect() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let sock_path = tmp.join("rust-test-uds-smoke.sock"); let _ = std::fs::remove_file(&sock_path); @@ -32,6 +46,8 @@ fn win_uds_smoke_bind_connect() { #[test] fn win_uds_echo() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let sock_path = tmp.join("rust-test-uds-echo.sock"); let _ = std::fs::remove_file(&sock_path); @@ -68,14 +84,19 @@ fn win_uds_echo() { #[test] fn win_uds_path_too_long() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let long_path = tmp.join("a".repeat(200)); let result = UnixListener::bind(&long_path); assert!(result.is_err()); let _ = std::fs::remove_file(&long_path); } + #[test] fn win_uds_existing_bind() { + skip_nonapplicable_oses!(); + let tmp = std::env::temp_dir(); let sock_path = tmp.join("rust-test-uds-existing.sock"); let _ = std::fs::remove_file(&sock_path); @@ -85,3 +106,115 @@ fn win_uds_existing_bind() { drop(listener); let _ = std::fs::remove_file(&sock_path); } + +/// Returns true if we are currently running on Windows 10 v1803 (RS4) or greater. +fn is_windows_10_v1803_or_greater() -> bool { + is_windows_version_greater_or_equal(NTDDI_WIN10_RS4) +} + +/// Returns true if we are currently running on the given version of Windows +/// 10 (or newer). +fn is_windows_version_greater_or_equal(min_version: u32) -> bool { + is_windows_version_or_greater(HIBYTE(OSVER(min_version)), LOBYTE(OSVER(min_version)), 0, 0) +} + +/// Checks if we are running a version of Windows newer than the specified one. +fn is_windows_version_or_greater( + major: u8, + minor: u8, + service_pack: u8, + build_number: u32, +) -> bool { + let mut osvi = OSVERSIONINFOEXW { + dwOSVersionInfoSize: mem::size_of::() as _, + dwMajorVersion: u32::from(major), + dwMinorVersion: u32::from(minor), + wServicePackMajor: u16::from(service_pack), + dwBuildNumber: build_number, + ..OSVERSIONINFOEXW::default() + }; + + // SAFETY: this function is always safe to call. + let condmask = unsafe { + VerSetConditionMask( + VerSetConditionMask( + VerSetConditionMask( + VerSetConditionMask(0, VER_MAJORVERSION, VER_GREATER_EQUAL as _), + VER_MINORVERSION, + VER_GREATER_EQUAL as _, + ), + VER_SERVICEPACKMAJOR, + VER_GREATER_EQUAL as _, + ), + VER_BUILDNUMBER, + VER_GREATER_EQUAL as _, + ) + }; + + // SAFETY: osvi needs to point to a memory region valid for at least + // dwOSVersionInfoSize bytes, which is the case here. + (unsafe { + RtlVerifyVersionInfo( + &raw mut osvi, + VER_MAJORVERSION | VER_MINORVERSION | VER_SERVICEPACKMAJOR, + condmask, + ) + }) == STATUS_SUCCESS +} + +#[expect(non_snake_case)] +const fn HIBYTE(x: u16) -> u8 { + ((x >> 8) & 0xFF) as u8 +} + +#[expect(non_snake_case)] +const fn LOBYTE(x: u16) -> u8 { + (x & 0xFF) as u8 +} + +#[expect(non_snake_case)] +const fn OSVER(x: u32) -> u16 { + ((x & OSVERSION_MASK) >> 16) as u16 +} + +// Inlined bindings because outside of `std` here. + +type NTSTATUS = i32; +const STATUS_SUCCESS: NTSTATUS = 0; + +#[expect(non_camel_case_types)] +type VER_FLAGS = u32; +const VER_BUILDNUMBER: VER_FLAGS = 4u32; +const VER_GREATER_EQUAL: VER_FLAGS = 3u32; +const VER_MAJORVERSION: VER_FLAGS = 2u32; +const VER_MINORVERSION: VER_FLAGS = 1u32; +const VER_SERVICEPACKMAJOR: VER_FLAGS = 32u32; + +const OSVERSION_MASK: u32 = 4294901760u32; +const NTDDI_WIN10_RS4: u32 = 167772165u32; + +#[expect(non_snake_case)] +#[repr(C)] +#[derive(Clone, Copy)] +struct OSVERSIONINFOEXW { + pub dwOSVersionInfoSize: u32, + pub dwMajorVersion: u32, + pub dwMinorVersion: u32, + pub dwBuildNumber: u32, + pub dwPlatformId: u32, + pub szCSDVersion: [u16; 128], + pub wServicePackMajor: u16, + pub wServicePackMinor: u16, + pub wSuiteMask: u16, + pub wProductType: u8, + pub wReserved: u8, +} + +impl Default for OSVERSIONINFOEXW { + fn default() -> Self { + unsafe { core::mem::zeroed() } + } +} + +windows_link::link!("ntdll.dll" "system" fn RtlVerifyVersionInfo(versioninfo : *const OSVERSIONINFOEXW, typemask : u32, conditionmask : u64) -> NTSTATUS); +windows_link::link!("kernel32.dll" "system" fn VerSetConditionMask(conditionmask : u64, typemask : VER_FLAGS, condition : u8) -> u64); diff --git a/std_detect/src/lib.rs b/std_detect/src/lib.rs index 5e1d21bbfd17d..f9d79df670a0f 100644 --- a/std_detect/src/lib.rs +++ b/std_detect/src/lib.rs @@ -15,7 +15,7 @@ //! * `s390x`: [`is_s390x_feature_detected`] #![unstable(feature = "stdarch_internal", issue = "none")] -#![feature(staged_api, cfg_select, doc_cfg, allow_internal_unstable)] +#![feature(staged_api, doc_cfg, allow_internal_unstable)] #![deny(rust_2018_idioms)] #![allow(clippy::shadow_reuse)] #![cfg_attr(test, allow(unused_imports))] diff --git a/std_detect/tests/cpu-detection.rs b/std_detect/tests/cpu-detection.rs index 196abfdb7c4dd..0aad088af7de5 100644 --- a/std_detect/tests/cpu-detection.rs +++ b/std_detect/tests/cpu-detection.rs @@ -1,4 +1,4 @@ -#![allow(internal_features)] +#![allow(internal_features, unused_features)] #![feature(stdarch_internal)] #![cfg_attr(target_arch = "arm", feature(stdarch_arm_feature_detection))] #![cfg_attr( diff --git a/std_detect/tests/macro_trailing_commas.rs b/std_detect/tests/macro_trailing_commas.rs index 29bd3f1162a42..a60b34acb872f 100644 --- a/std_detect/tests/macro_trailing_commas.rs +++ b/std_detect/tests/macro_trailing_commas.rs @@ -1,4 +1,4 @@ -#![allow(internal_features)] +#![allow(internal_features, unused_features)] #![cfg_attr( any( target_arch = "arm", diff --git a/stdarch/.github/workflows/main.yml b/stdarch/.github/workflows/main.yml index 6cf0e9f02fe54..0ec355aa3ca4f 100644 --- a/stdarch/.github/workflows/main.yml +++ b/stdarch/.github/workflows/main.yml @@ -96,6 +96,8 @@ jobs: os: ubuntu-latest - tuple: loongarch64-unknown-linux-gnu os: ubuntu-latest + - tuple: hexagon-unknown-linux-musl + os: ubuntu-latest - tuple: wasm32-wasip1 os: ubuntu-latest @@ -207,6 +209,11 @@ jobs: tuple: amdgcn-amd-amdhsa os: ubuntu-latest norun: true + - target: + tuple: hexagon-unknown-linux-musl + os: ubuntu-latest + norun: true + build_std: true steps: - uses: actions/checkout@v4 @@ -300,7 +307,7 @@ jobs: # Check that the generated files agree with the checked-in versions. check-stdarch-gen: needs: [style] - name: Check stdarch-gen-{arm, loongarch} output + name: Check stdarch-gen-{arm, loongarch, hexagon} output runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 @@ -318,6 +325,10 @@ jobs: run: | cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lasx.spec git diff --exit-code + - name: Check hexagon + run: | + cargo run -p stdarch-gen-hexagon --release + git diff --exit-code conclusion: needs: diff --git a/stdarch/Cargo.lock b/stdarch/Cargo.lock index 70f09adf2c857..7e7cb592889a8 100644 --- a/stdarch/Cargo.lock +++ b/stdarch/Cargo.lock @@ -4,18 +4,18 @@ version = 4 [[package]] name = "aho-corasick" -version = "1.1.3" +version = "1.1.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916" +checksum = "ddd31a130427c27518df266943a5308ed92d4b226cc639f5a8f1002816174301" dependencies = [ "memchr", ] [[package]] name = "anstream" -version = "0.6.20" +version = "0.6.21" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3ae563653d1938f79b1ab1b5e668c87c76a9930414574a6583a7b7e11a8e6192" +checksum = "43d5b281e737544384e969a5ccad3f1cdd24b48086a0fc1b2a5262a26b8f4f4a" dependencies = [ "anstyle", "anstyle-parse", @@ -28,9 +28,9 @@ dependencies = [ [[package]] name = "anstyle" -version = "1.0.11" +version = "1.0.13" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "862ed96ca487e809f1c8e5a8447f6ee2cf102f846893800b20cebdf541fc6bbd" +checksum = "5192cca8006f1fd4f7237516f40fa183bb07f8fbdfedaa0036de5ea9b0b45e78" [[package]] name = "anstyle-parse" @@ -43,29 +43,29 @@ dependencies = [ [[package]] name = "anstyle-query" -version = "1.1.4" +version = "1.1.5" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9e231f6134f61b71076a3eab506c379d4f36122f2af15a9ff04415ea4c3339e2" +checksum = "40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc" dependencies = [ - "windows-sys 0.60.2", + "windows-sys", ] [[package]] name = "anstyle-wincon" -version = "3.0.10" +version = "3.0.11" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3e0633414522a32ffaac8ac6cc8f748e090c5717661fddeea04219e2344f5f2a" +checksum = "291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d" dependencies = [ "anstyle", "once_cell_polyfill", - "windows-sys 0.60.2", + "windows-sys", ] [[package]] name = "anyhow" -version = "1.0.99" +version = "1.0.101" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b0674a1ddeecb70197781e945de4b3b8ffb61fa939a5597bcf48503737663100" +checksum = "5f0e0fee31ef5ed1ba1316088939cea399010ed7731dba877ed44aeb407a75ea" [[package]] name = "assert-instr-macro" @@ -84,15 +84,15 @@ checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8" [[package]] name = "bitflags" -version = "2.9.4" +version = "2.10.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2261d10cca569e4643e526d8dc2e62e433cc8aba21ab764233731f8d369bf394" +checksum = "812e12b5285cc515a9c72a5c1d3b6d46a19dac5acfef5265968c166106e31dd3" [[package]] name = "cc" -version = "1.2.36" +version = "1.2.55" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5252b3d2648e5eedbc1a6f501e3c795e07025c1e93bbf8bbdd6eef7f447a6d54" +checksum = "47b26a0954ae34af09b50f0de26458fa95369a0d478d8236d3f93082b219bd29" dependencies = [ "find-msvc-tools", "shlex", @@ -100,15 +100,15 @@ dependencies = [ [[package]] name = "cfg-if" -version = "1.0.3" +version = "1.0.4" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2fd1289c04a9ea8cb22300a459a72a385d7c73d3259e2ed7dcb2af674838cfa9" +checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801" [[package]] name = "clap" -version = "4.5.47" +version = "4.5.58" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7eac00902d9d136acd712710d71823fb8ac8004ca445a89e73a41d45aa712931" +checksum = "63be97961acde393029492ce0be7a1af7e323e6bae9511ebfac33751be5e6806" dependencies = [ "clap_builder", "clap_derive", @@ -116,9 +116,9 @@ dependencies = [ [[package]] name = "clap_builder" -version = "4.5.47" +version = "4.5.58" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2ad9bbf750e73b5884fb8a211a9424a1906c1e156724260fdae972f31d70e1d6" +checksum = "7f13174bda5dfd69d7e947827e5af4b0f2f94a4a3ee92912fba07a66150f21e2" dependencies = [ "anstream", "anstyle", @@ -128,9 +128,9 @@ dependencies = [ [[package]] name = "clap_derive" -version = "4.5.47" +version = "4.5.55" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bbfd7eae0b0f1a6e63d4b13c9c478de77c2eb546fba158ad50b4203dc24b9f9c" +checksum = "a92793da1a46a5f2a02a6f4c46c6496b28c43638adea8306fcb0caa1634f24e5" dependencies = [ "heck", "proc-macro2", @@ -140,9 +140,9 @@ dependencies = [ [[package]] name = "clap_lex" -version = "0.7.5" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b94f61472cee1439c0b966b47e3aca9ae07e45d070759512cd390ea2bebc6675" +checksum = "3a822ea5bc7590f9d40f1ba12c0dc3c2760f3482c6984db1573ad11031420831" [[package]] name = "colorchoice" @@ -185,9 +185,9 @@ checksum = "d0a5c400df2834b80a4c3327b3aad3a4c4cd4de0629063962b03235697506a28" [[package]] name = "darling" -version = "0.20.11" +version = "0.21.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fc7f46116c46ff9ab3eb1597a45688b6715c6e628b5c133e288e709a29bcb4ee" +checksum = "9cdf337090841a411e2a7f3deb9187445851f91b309c0c0a29e05f74a00a48c0" dependencies = [ "darling_core", "darling_macro", @@ -195,9 +195,9 @@ dependencies = [ [[package]] name = "darling_core" -version = "0.20.11" +version = "0.21.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0d00b9596d185e565c2207a0b01f8bd1a135483d02d9b7b0a54b11da8d53412e" +checksum = "1247195ecd7e3c85f83c8d2a366e4210d588e802133e1e355180a9870b517ea4" dependencies = [ "fnv", "ident_case", @@ -209,9 +209,9 @@ dependencies = [ [[package]] name = "darling_macro" -version = "0.20.11" +version = "0.21.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "fc34b93ccb385b40dc71c6fceac4b2ad23662c7eeb248cf10d529b7e055b6ead" +checksum = "d38308df82d1080de0afee5d069fa14b0326a88c14f15c5ccda35b4a6c414c81" dependencies = [ "darling_core", "quote", @@ -231,10 +231,10 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "48c757948c5ede0e46177b7add2e67155f70e33c07fea8284df6576da70b3719" [[package]] -name = "env_logger" -version = "0.8.4" +name = "env_filter" +version = "1.0.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a19187fea3ac7e84da7dacf48de0c45d63c6a76f9490dae389aead16c243fce3" +checksum = "7a1c3cc8e57274ec99de65301228b537f1e4eedc1b8e0f9411c6caac8ae7308f" dependencies = [ "log", "regex", @@ -253,6 +253,16 @@ dependencies = [ "termcolor", ] +[[package]] +name = "env_logger" +version = "0.11.9" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b2daee4ea451f429a58296525ddf28b45a3b64f1acf6587e2067437bb11e218d" +dependencies = [ + "env_filter", + "log", +] + [[package]] name = "equivalent" version = "1.0.2" @@ -261,9 +271,9 @@ checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f" [[package]] name = "find-msvc-tools" -version = "0.1.1" +version = "0.1.9" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7fd99930f64d146689264c637b5af2f0233a933bef0d8570e2526bf9e083192d" +checksum = "5baebc0774151f905a1a2cc41989300b1e6fbb29aff0ceffa1064fdd3088d582" [[package]] name = "fnv" @@ -271,17 +281,37 @@ version = "1.0.7" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1" +[[package]] +name = "foldhash" +version = "0.1.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2" + [[package]] name = "getrandom" -version = "0.2.16" +version = "0.2.17" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "335ff9f135e4384c8150d6f27c6daed433577f86b4750418338c01a1a2528592" +checksum = "ff2abc00be7fca6ebc474524697ae276ad847ad0a6b3faa4bcb027e9a4614ad0" dependencies = [ "cfg-if", "libc", "wasi", ] +[[package]] +name = "getrandom" +version = "0.4.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "139ef39800118c7683f2fd3c98c1b23c09ae076556b435f8e9064ae108aaeeec" +dependencies = [ + "cfg-if", + "libc", + "r-efi", + "rand_core 0.10.0", + "wasip2", + "wasip3", +] + [[package]] name = "hashbrown" version = "0.12.3" @@ -293,6 +323,15 @@ name = "hashbrown" version = "0.15.5" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "9229cfe53dfd69f0609a49f65461bd93001ea1ef889cd5529dd176593f5338a1" +dependencies = [ + "foldhash", +] + +[[package]] +name = "hashbrown" +version = "0.16.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "841d1cc9bed7f9236f321df977030373f4a4163ae1a7dbfe1a51a2c1a51d9100" [[package]] name = "heck" @@ -308,9 +347,15 @@ checksum = "fc0fef456e4baa96da950455cd02c081ca953b141298e41db3fc7e36b1da849c" [[package]] name = "humantime" -version = "2.2.0" +version = "2.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9b112acc8b3adf4b107a8ec20977da0273a8c386765a3ec0229bd500a1443f9f" +checksum = "135b12329e5e3ce057a9f972339ea52bc954fe1e9358ef27f95e89716fbc5424" + +[[package]] +name = "id-arena" +version = "2.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "3d3067d79b975e8844ca9eb072e16b31c3c1c36928edf9c6789548c524d0d954" [[package]] name = "ident_case" @@ -330,12 +375,14 @@ dependencies = [ [[package]] name = "indexmap" -version = "2.11.0" +version = "2.13.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f2481980430f9f78649238835720ddccc57e52df14ffce1c6f37391d61b563e9" +checksum = "7714e70437a7dc3ac8eb7e6f8df75fd8eb422675fc7678aff7364301092b1017" dependencies = [ "equivalent", - "hashbrown 0.15.5", + "hashbrown 0.16.1", + "serde", + "serde_core", ] [[package]] @@ -357,20 +404,20 @@ dependencies = [ [[package]] name = "is-terminal" -version = "0.4.16" +version = "0.4.17" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e04d7f318608d35d4b61ddd75cbdaee86b023ebe2bd5a66ee0915f0bf93095a9" +checksum = "3640c1c38b8e4e43584d8df18be5fc6b0aa314ce6ebf51b53313d4306cca8e46" dependencies = [ "hermit-abi", "libc", - "windows-sys 0.59.0", + "windows-sys", ] [[package]] name = "is_terminal_polyfill" -version = "1.70.1" +version = "1.70.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7943c866cc5cd64cbc25b2e01621d07fa8eb2a1a23160ee81ce38704e97b8ecf" +checksum = "a6cb138bb79a146c1bd460005623e142ef0181e3d0219cb493e02f7d08a35695" [[package]] name = "itertools" @@ -383,15 +430,21 @@ dependencies = [ [[package]] name = "itoa" -version = "1.0.15" +version = "1.0.17" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "92ecc6618181def0457392ccd0ee51198e065e016d1d527a7ac1b6dc7c1f09d2" + +[[package]] +name = "leb128fmt" +version = "0.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4a5f13b858c8d314ee3e8f639011f7ccefe71f97f96e50151fb991f267928e2c" +checksum = "09edd9e8b54e49e587e4f6295a7d29c3ea94d469cb40ab8ca70b288248a81db2" [[package]] name = "libc" -version = "0.2.175" +version = "0.2.181" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6a82ae493e598baaea5209805c49bbf2ea7de956d50d7da0da1164f9c6d28543" +checksum = "459427e2af2b9c839b132acb702a1c654d95e10f8c326bfc2ad11310e458b1c5" [[package]] name = "linked-hash-map" @@ -401,21 +454,21 @@ checksum = "0717cef1bc8b636c6e1c1bbdefc09e6322da8a9321966e8928ef80d20f7f770f" [[package]] name = "log" -version = "0.4.28" +version = "0.4.29" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "34080505efa8e45a4b816c349525ebe327ceaa8559756f0356cba97ef3bf7432" +checksum = "5e5032e24019045c762d3c0f28f5b6b8bbf38563a65908389bf7978758920897" [[package]] name = "memchr" -version = "2.7.6" +version = "2.8.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f52b00d39961fc5b2736ea853c9cc86238e165017a493d1d5c8eac6bdc4cc273" +checksum = "f8ca58f447f06ed17d5fc4043ce1b10dd205e060fb3ce5b979b8ed8e59ff3f79" [[package]] name = "once_cell_polyfill" -version = "1.70.1" +version = "1.70.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a4895175b425cb1f87721b59f0f286c2092bd4af812243672510e1ac53e2e0ad" +checksum = "384b8ab6d37215f3c5301a95a4accb5d64aa607f1fcb26a11b5303878451b4fe" [[package]] name = "ppv-lite86" @@ -436,11 +489,21 @@ dependencies = [ "log", ] +[[package]] +name = "prettyplease" +version = "0.2.37" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "479ca8adacdd7ce8f1fb39ce9ecccbfe93a3f1344b3d0d97f20bc0196208f62b" +dependencies = [ + "proc-macro2", + "syn", +] + [[package]] name = "proc-macro2" -version = "1.0.101" +version = "1.0.106" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "89ae43fd86e4158d6db51ad8e2b80f313af9cc74f5c0e03ccb87de09998732de" +checksum = "8fd00f0bb2e90d81d1044c2b32617f68fcb9fa3bb7640c23e9c748e53fb30934" dependencies = [ "unicode-ident", ] @@ -467,24 +530,30 @@ dependencies = [ [[package]] name = "quickcheck" -version = "1.0.3" +version = "1.1.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "588f6378e4dd99458b60ec275b4477add41ce4fa9f64dcba6f15adccb19b50d6" +checksum = "95c589f335db0f6aaa168a7cd27b1fc6920f5e1470c804f814d9cd6e62a0f70b" dependencies = [ - "env_logger 0.8.4", + "env_logger 0.11.9", "log", - "rand", + "rand 0.10.0", ] [[package]] name = "quote" -version = "1.0.40" +version = "1.0.44" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1885c039570dc00dcb4ff087a89e185fd56bae234ddc7f056a945bf36467248d" +checksum = "21b2ebcf727b7760c461f091f9f0f539b77b8e87f2fd88131e7f1b433b3cece4" dependencies = [ "proc-macro2", ] +[[package]] +name = "r-efi" +version = "5.3.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "69cdb34c158ceb288df11e18b4bd39de994f6657d83847bdffdbd7f346754b0f" + [[package]] name = "rand" version = "0.8.5" @@ -493,7 +562,17 @@ checksum = "34af8d1a0e25924bc5b7c43c079c942339d8f0a8b57c39049bef581b46327404" dependencies = [ "libc", "rand_chacha", - "rand_core", + "rand_core 0.6.4", +] + +[[package]] +name = "rand" +version = "0.10.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bc266eb313df6c5c09c1c7b1fbe2510961e5bcd3add930c1e31f7ed9da0feff8" +dependencies = [ + "getrandom 0.4.1", + "rand_core 0.10.0", ] [[package]] @@ -503,7 +582,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "e6c10a63a0fa32252be49d21e7709d4d4baf8d231c2dbce1eaa8141b9b127d88" dependencies = [ "ppv-lite86", - "rand_core", + "rand_core 0.6.4", ] [[package]] @@ -512,9 +591,15 @@ version = "0.6.4" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c" dependencies = [ - "getrandom", + "getrandom 0.2.17", ] +[[package]] +name = "rand_core" +version = "0.10.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0c8d0fd677905edcbeedbf2edb6494d676f0e98d54d5cf9bda0b061cb8fb8aba" + [[package]] name = "rayon" version = "1.11.0" @@ -537,9 +622,9 @@ dependencies = [ [[package]] name = "regex" -version = "1.11.2" +version = "1.12.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "23d7fd106d8c02486a8d64e778353d1cffe08ce79ac2e82f540c86d0facf6912" +checksum = "e10754a14b9137dd7b1e3e5b0493cc9171fdd105e0ab477f51b72e7f3ac0e276" dependencies = [ "aho-corasick", "memchr", @@ -549,9 +634,9 @@ dependencies = [ [[package]] name = "regex-automata" -version = "0.4.10" +version = "0.4.14" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6b9458fa0bfeeac22b5ca447c63aaf45f28439a709ccd244698632f9aa6394d6" +checksum = "6e1dd4122fc1595e8162618945476892eefca7b88c52820e74af6262213cae8f" dependencies = [ "aho-corasick", "memchr", @@ -560,21 +645,21 @@ dependencies = [ [[package]] name = "regex-syntax" -version = "0.8.6" +version = "0.8.9" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "caf4aa5b0f434c91fe5c7f1ecb6a5ece2130b02ad2a590589dda5146df959001" +checksum = "a96887878f22d7bad8a3b6dc5b7440e0ada9a245242924394987b21cf2210a4c" [[package]] name = "rustc-demangle" -version = "0.1.26" +version = "0.1.27" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "56f7d92ca342cea22a06f2121d944b4fd82af56988c270852495420f961d4ace" +checksum = "b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d" [[package]] name = "ryu" -version = "1.0.20" +version = "1.0.23" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "28d3b2b1366ec20994f1fd18c3c594f05c5dd4bc44d8bb0c1c632c8d6829481f" +checksum = "9774ba4a74de5f7b1c1451ed6cd5285a32eddb5cccb8cc655a4e50009e06477f" [[package]] name = "same-file" @@ -587,36 +672,46 @@ dependencies = [ [[package]] name = "semver" -version = "1.0.26" +version = "1.0.27" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "56e6fa9c48d24d85fb3de5ad847117517440f6beceb7798af16b4a87d616b8d0" +checksum = "d767eb0aabc880b29956c35734170f26ed551a859dbd361d140cdbeca61ab1e2" [[package]] name = "serde" -version = "1.0.219" +version = "1.0.228" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5f0e2c6ed6606019b4e29e69dbaba95b11854410e5347d525002456dbbb786b6" +checksum = "9a8e94ea7f378bd32cbbd37198a4a91436180c5bb472411e48b5ec2e2124ae9e" dependencies = [ + "serde_core", "serde_derive", ] [[package]] name = "serde-xml-rs" -version = "0.8.1" +version = "0.8.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "53630160a98edebde0123eb4dfd0fce6adff091b2305db3154a9e920206eb510" +checksum = "cc2215ce3e6a77550b80a1c37251b7d294febaf42e36e21b7b411e0bf54d540d" dependencies = [ "log", "serde", "thiserror", - "xml-rs", + "xml", +] + +[[package]] +name = "serde_core" +version = "1.0.228" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "41d385c7d4ca58e59fc732af25c3983b67ac852c1a25000afe1175de458b67ad" +dependencies = [ + "serde_derive", ] [[package]] name = "serde_derive" -version = "1.0.219" +version = "1.0.228" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5b0276cf7f2c73365f7157c8123c21cd9a50fbbd844757af28ca1f5925fc2a00" +checksum = "d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79" dependencies = [ "proc-macro2", "quote", @@ -625,32 +720,32 @@ dependencies = [ [[package]] name = "serde_json" -version = "1.0.143" +version = "1.0.149" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d401abef1d108fbd9cbaebc3e46611f4b1021f714a0597a71f41ee463f5f4a5a" +checksum = "83fc039473c5595ace860d8c4fafa220ff474b3fc6bfdb4293327f1a37e94d86" dependencies = [ "itoa", "memchr", - "ryu", "serde", + "serde_core", + "zmij", ] [[package]] name = "serde_with" -version = "3.14.0" +version = "3.16.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f2c45cd61fefa9db6f254525d46e392b852e0e61d9a1fd36e5bd183450a556d5" +checksum = "4fa237f2807440d238e0364a218270b98f767a00d3dada77b1c53ae88940e2e7" dependencies = [ - "serde", - "serde_derive", + "serde_core", "serde_with_macros", ] [[package]] name = "serde_with_macros" -version = "3.14.0" +version = "3.16.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "de90945e6565ce0d9a25098082ed4ee4002e047cb59892c318d66821e14bb30f" +checksum = "52a8e3ca0ca629121f70ab50f95249e5a6f925cc0f6ffe8256c45b728875706c" dependencies = [ "darling", "proc-macro2", @@ -699,11 +794,18 @@ dependencies = [ "walkdir", ] +[[package]] +name = "stdarch-gen-hexagon" +version = "0.1.0" +dependencies = [ + "regex", +] + [[package]] name = "stdarch-gen-loongarch" version = "0.1.0" dependencies = [ - "rand", + "rand 0.8.5", ] [[package]] @@ -736,7 +838,7 @@ version = "0.0.0" dependencies = [ "core_arch", "quickcheck", - "rand", + "rand 0.8.5", ] [[package]] @@ -747,9 +849,9 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f" [[package]] name = "syn" -version = "2.0.106" +version = "2.0.115" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ede7c438028d4436d71104916910f5bb611972c5cfd7f89b8300a8186e6fada6" +checksum = "6e614ed320ac28113fa64972c4262d5dbc89deacdfd00c34a3e4cea073243c12" dependencies = [ "proc-macro2", "quote", @@ -773,18 +875,18 @@ dependencies = [ [[package]] name = "thiserror" -version = "1.0.69" +version = "2.0.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b6aaf5339b578ea85b50e080feb250a3e8ae8cfcdff9a461c9ec2904bc923f52" +checksum = "4288b5bcbc7920c07a1149a35cf9590a2aa808e0bc1eafaade0b80947865fbc4" dependencies = [ "thiserror-impl", ] [[package]] name = "thiserror-impl" -version = "1.0.69" +version = "2.0.18" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "4fee6c4efc90059e10f81e6d42c60a18f76588c3d74cb83a0b242a2b6c7504c1" +checksum = "ebc4ee7f67670e9b64d05fa4253e753e016c6c95ff35b89b7941d6b856dec1d5" dependencies = [ "proc-macro2", "quote", @@ -793,9 +895,15 @@ dependencies = [ [[package]] name = "unicode-ident" -version = "1.0.18" +version = "1.0.23" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "537dd038a89878be9b64dd4bd1b260315c1bb94f4d784956b81e27a088d9a09e" + +[[package]] +name = "unicode-xid" +version = "0.2.6" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5a5f39404a5da50712a4c1eecf25e90dd62b613502b7e925fd4e4d19b5c96512" +checksum = "ebc1c04c71510c7f702b52b7c350734c9ff1295c464a03335b00bb84fc54f853" [[package]] name = "utf8parse" @@ -820,194 +928,196 @@ source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b" [[package]] -name = "wasmparser" -version = "0.235.0" +name = "wasip2" +version = "1.0.2+wasi-0.2.9" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "161296c618fa2d63f6ed5fffd1112937e803cb9ec71b32b01a76321555660917" +checksum = "9517f9239f02c069db75e65f174b3da828fe5f5b945c4dd26bd25d89c03ebcf5" dependencies = [ - "bitflags", - "indexmap 2.11.0", - "semver", + "wit-bindgen", ] [[package]] -name = "wasmprinter" -version = "0.235.0" +name = "wasip3" +version = "0.4.0+wasi-0.3.0-rc-2026-01-06" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "75aa8e9076de6b9544e6dab4badada518cca0bf4966d35b131bbd057aed8fa0a" +checksum = "5428f8bf88ea5ddc08faddef2ac4a67e390b88186c703ce6dbd955e1c145aca5" dependencies = [ - "anyhow", - "termcolor", - "wasmparser", + "wit-bindgen", ] [[package]] -name = "winapi-util" -version = "0.1.10" +name = "wasm-encoder" +version = "0.244.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0978bf7171b3d90bac376700cb56d606feb40f251a475a5d6634613564460b22" +checksum = "990065f2fe63003fe337b932cfb5e3b80e0b4d0f5ff650e6985b1048f62c8319" dependencies = [ - "windows-sys 0.60.2", + "leb128fmt", + "wasmparser 0.244.0", ] [[package]] -name = "windows-link" -version = "0.1.3" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5e6ad25900d524eaabdbbb96d20b4311e1e7ae1699af4fb28c17ae66c80d798a" - -[[package]] -name = "windows-sys" -version = "0.59.0" +name = "wasm-metadata" +version = "0.244.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "1e38bc4d79ed67fd075bcc251a1c39b32a1776bbe92e5bef1f0bf1f8c531853b" +checksum = "bb0e353e6a2fbdc176932bbaab493762eb1255a7900fe0fea1a2f96c296cc909" dependencies = [ - "windows-targets 0.52.6", + "anyhow", + "indexmap 2.13.0", + "wasm-encoder", + "wasmparser 0.244.0", ] [[package]] -name = "windows-sys" -version = "0.60.2" +name = "wasmparser" +version = "0.235.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f2f500e4d28234f72040990ec9d39e3a6b950f9f22d3dba18416c35882612bcb" +checksum = "161296c618fa2d63f6ed5fffd1112937e803cb9ec71b32b01a76321555660917" dependencies = [ - "windows-targets 0.53.3", + "bitflags", + "indexmap 2.13.0", + "semver", ] [[package]] -name = "windows-targets" -version = "0.52.6" +name = "wasmparser" +version = "0.244.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9b724f72796e036ab90c1021d4780d4d3d648aca59e491e6b98e725b84e99973" +checksum = "47b807c72e1bac69382b3a6fb3dbe8ea4c0ed87ff5629b8685ae6b9a611028fe" dependencies = [ - "windows_aarch64_gnullvm 0.52.6", - "windows_aarch64_msvc 0.52.6", - "windows_i686_gnu 0.52.6", - "windows_i686_gnullvm 0.52.6", - "windows_i686_msvc 0.52.6", - "windows_x86_64_gnu 0.52.6", - "windows_x86_64_gnullvm 0.52.6", - "windows_x86_64_msvc 0.52.6", + "bitflags", + "hashbrown 0.15.5", + "indexmap 2.13.0", + "semver", ] [[package]] -name = "windows-targets" -version = "0.53.3" +name = "wasmprinter" +version = "0.235.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "d5fe6031c4041849d7c496a8ded650796e7b6ecc19df1a431c1a363342e5dc91" +checksum = "75aa8e9076de6b9544e6dab4badada518cca0bf4966d35b131bbd057aed8fa0a" dependencies = [ - "windows-link", - "windows_aarch64_gnullvm 0.53.0", - "windows_aarch64_msvc 0.53.0", - "windows_i686_gnu 0.53.0", - "windows_i686_gnullvm 0.53.0", - "windows_i686_msvc 0.53.0", - "windows_x86_64_gnu 0.53.0", - "windows_x86_64_gnullvm 0.53.0", - "windows_x86_64_msvc 0.53.0", + "anyhow", + "termcolor", + "wasmparser 0.235.0", ] [[package]] -name = "windows_aarch64_gnullvm" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "32a4622180e7a0ec044bb555404c800bc9fd9ec262ec147edd5989ccd0c02cd3" - -[[package]] -name = "windows_aarch64_gnullvm" -version = "0.53.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "86b8d5f90ddd19cb4a147a5fa63ca848db3df085e25fee3cc10b39b6eebae764" - -[[package]] -name = "windows_aarch64_msvc" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "09ec2a7bb152e2252b53fa7803150007879548bc709c039df7627cabbd05d469" - -[[package]] -name = "windows_aarch64_msvc" -version = "0.53.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c7651a1f62a11b8cbd5e0d42526e55f2c99886c77e007179efff86c2b137e66c" - -[[package]] -name = "windows_i686_gnu" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8e9b5ad5ab802e97eb8e295ac6720e509ee4c243f69d781394014ebfe8bbfa0b" - -[[package]] -name = "windows_i686_gnu" -version = "0.53.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "c1dc67659d35f387f5f6c479dc4e28f1d4bb90ddd1a5d3da2e5d97b42d6272c3" - -[[package]] -name = "windows_i686_gnullvm" -version = "0.52.6" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0eee52d38c090b3caa76c563b86c3a4bd71ef1a819287c19d586d7334ae8ed66" - -[[package]] -name = "windows_i686_gnullvm" -version = "0.53.0" +name = "winapi-util" +version = "0.1.11" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "9ce6ccbdedbf6d6354471319e781c0dfef054c81fbc7cf83f338a4296c0cae11" +checksum = "c2a7b1c03c876122aa43f3020e6c3c3ee5c05081c9a00739faf7503aeba10d22" +dependencies = [ + "windows-sys", +] [[package]] -name = "windows_i686_msvc" -version = "0.52.6" +name = "windows-link" +version = "0.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "240948bc05c5e7c6dabba28bf89d89ffce3e303022809e73deaefe4f6ec56c66" +checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5" [[package]] -name = "windows_i686_msvc" -version = "0.53.0" +name = "windows-sys" +version = "0.61.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "581fee95406bb13382d2f65cd4a908ca7b1e4c2f1917f143ba16efe98a589b5d" +checksum = "ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc" +dependencies = [ + "windows-link", +] [[package]] -name = "windows_x86_64_gnu" -version = "0.52.6" +name = "wit-bindgen" +version = "0.51.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "147a5c80aabfbf0c7d901cb5895d1de30ef2907eb21fbbab29ca94c5b08b1a78" +checksum = "d7249219f66ced02969388cf2bb044a09756a083d0fab1e566056b04d9fbcaa5" +dependencies = [ + "wit-bindgen-rust-macro", +] [[package]] -name = "windows_x86_64_gnu" -version = "0.53.0" +name = "wit-bindgen-core" +version = "0.51.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "2e55b5ac9ea33f2fc1716d1742db15574fd6fc8dadc51caab1c16a3d3b4190ba" +checksum = "ea61de684c3ea68cb082b7a88508a8b27fcc8b797d738bfc99a82facf1d752dc" +dependencies = [ + "anyhow", + "heck", + "wit-parser", +] [[package]] -name = "windows_x86_64_gnullvm" -version = "0.52.6" +name = "wit-bindgen-rust" +version = "0.51.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d" +checksum = "b7c566e0f4b284dd6561c786d9cb0142da491f46a9fbed79ea69cdad5db17f21" +dependencies = [ + "anyhow", + "heck", + "indexmap 2.13.0", + "prettyplease", + "syn", + "wasm-metadata", + "wit-bindgen-core", + "wit-component", +] [[package]] -name = "windows_x86_64_gnullvm" -version = "0.53.0" +name = "wit-bindgen-rust-macro" +version = "0.51.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0a6e035dd0599267ce1ee132e51c27dd29437f63325753051e71dd9e42406c57" +checksum = "0c0f9bfd77e6a48eccf51359e3ae77140a7f50b1e2ebfe62422d8afdaffab17a" +dependencies = [ + "anyhow", + "prettyplease", + "proc-macro2", + "quote", + "syn", + "wit-bindgen-core", + "wit-bindgen-rust", +] [[package]] -name = "windows_x86_64_msvc" -version = "0.52.6" +name = "wit-component" +version = "0.244.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec" +checksum = "9d66ea20e9553b30172b5e831994e35fbde2d165325bec84fc43dbf6f4eb9cb2" +dependencies = [ + "anyhow", + "bitflags", + "indexmap 2.13.0", + "log", + "serde", + "serde_derive", + "serde_json", + "wasm-encoder", + "wasm-metadata", + "wasmparser 0.244.0", + "wit-parser", +] [[package]] -name = "windows_x86_64_msvc" -version = "0.53.0" +name = "wit-parser" +version = "0.244.0" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "271414315aff87387382ec3d271b52d7ae78726f5d44ac98b4f4030c91880486" +checksum = "ecc8ac4bc1dc3381b7f59c34f00b67e18f910c2c0f50015669dde7def656a736" +dependencies = [ + "anyhow", + "id-arena", + "indexmap 2.13.0", + "log", + "semver", + "serde", + "serde_derive", + "serde_json", + "unicode-xid", + "wasmparser 0.244.0", +] [[package]] -name = "xml-rs" -version = "0.8.27" +name = "xml" +version = "1.2.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "6fd8403733700263c6eb89f192880191f1b83e332f7a20371ddcf421c4a337c7" +checksum = "b8aa498d22c9bbaf482329839bc5620c46be275a19a812e9a22a2b07529a642a" [[package]] name = "yaml-rust" @@ -1020,20 +1130,26 @@ dependencies = [ [[package]] name = "zerocopy" -version = "0.8.27" +version = "0.8.39" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "0894878a5fa3edfd6da3f88c4805f4c8558e2b996227a3d864f47fe11e38282c" +checksum = "db6d35d663eadb6c932438e763b262fe1a70987f9ae936e60158176d710cae4a" dependencies = [ "zerocopy-derive", ] [[package]] name = "zerocopy-derive" -version = "0.8.27" +version = "0.8.39" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "88d2b8d9c68ad2b9e4340d7832716a4d21a22a1154777ad56ea55c51a9cf3831" +checksum = "4122cd3169e94605190e77839c9a40d40ed048d305bfdc146e7df40ab0f3e517" dependencies = [ "proc-macro2", "quote", "syn", ] + +[[package]] +name = "zmij" +version = "1.0.21" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b8848ee67ecc8aedbaf3e4122217aff892639231befc6a1b58d29fff4c2cabaa" diff --git a/stdarch/ci/docker/hexagon-unknown-linux-musl/Dockerfile b/stdarch/ci/docker/hexagon-unknown-linux-musl/Dockerfile new file mode 100644 index 0000000000000..f6c0efd94629a --- /dev/null +++ b/stdarch/ci/docker/hexagon-unknown-linux-musl/Dockerfile @@ -0,0 +1,46 @@ +FROM ubuntu:25.10 + +RUN apt-get update && apt-get install -y --no-install-recommends \ + gcc \ + libc6-dev \ + ca-certificates \ + curl \ + zstd \ + file \ + make \ + libc++1 \ + libglib2.0-0t64 \ + libunwind-20 \ + liburing2 \ + llvm + +# The Hexagon toolchain requires libc++ and libunwind at runtime - create symlinks from versioned files +RUN cd /usr/lib/x86_64-linux-gnu && \ + for f in libc++.so.1.0.*; do ln -sf "$f" libc++.so.1; done && \ + for f in libc++abi.so.1.0.*; do ln -sf "$f" libc++abi.so.1; done && \ + for f in libunwind.so.1.0.*; do ln -sf "$f" libunwind.so.1; done + +# Download and install the Hexagon cross toolchain from +# https://github.com/quic/toolchain_for_hexagon/releases/tag/v21.1.8 +# Includes clang cross-compiler, musl sysroot, and qemu-hexagon. +# +# The tarball contains directories with restrictive (0700) permissions. +# In rootless Podman, chmod fails on tar-extracted files within the same +# layer due to overlayfs limitations in user namespaces. Splitting into +# two RUN steps lets chmod work via overlayfs copy-up from the lower layer. +RUN curl -L -o /tmp/hexagon-toolchain.tar.zst \ + https://artifacts.codelinaro.org/artifactory/codelinaro-toolchain-for-hexagon/21.1.8/clang+llvm-21.1.8-cross-hexagon-unknown-linux-musl.tar.zst && \ + mkdir -p /opt/hexagon-toolchain && \ + cd /opt/hexagon-toolchain && \ + (unzstd -c /tmp/hexagon-toolchain.tar.zst | tar -xf - --strip-components=2 --no-same-permissions || true) && \ + rm /tmp/hexagon-toolchain.tar.zst +RUN find /opt/hexagon-toolchain -type d -exec chmod a+rx {} + 2>/dev/null; \ + find /opt/hexagon-toolchain -type f -exec chmod a+r {} + 2>/dev/null; \ + find /opt/hexagon-toolchain -type f -perm /111 -exec chmod a+rx {} + 2>/dev/null; \ + /opt/hexagon-toolchain/bin/hexagon-unknown-linux-musl-clang --version + +ENV PATH="/opt/hexagon-toolchain/bin:${PATH}" \ + CARGO_TARGET_HEXAGON_UNKNOWN_LINUX_MUSL_LINKER=hexagon-unknown-linux-musl-clang \ + CARGO_TARGET_HEXAGON_UNKNOWN_LINUX_MUSL_RUNNER="qemu-hexagon -L /opt/hexagon-toolchain/target/hexagon-unknown-linux-musl" \ + CARGO_UNSTABLE_BUILD_STD_FEATURES=llvm-libunwind \ + OBJDUMP=llvm-objdump diff --git a/stdarch/ci/run.sh b/stdarch/ci/run.sh index 8a0b5fa26f66c..ea012b42f983b 100755 --- a/stdarch/ci/run.sh +++ b/stdarch/ci/run.sh @@ -50,6 +50,9 @@ case ${TARGET} in riscv*) export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+zk,+zks,+zbb,+zbc" ;; + hexagon*) + export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+hvxv60,+hvx-length128b" + ;; esac echo "RUSTFLAGS=${RUSTFLAGS}" diff --git a/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/stdarch/crates/core_arch/src/aarch64/neon/generated.rs index 9507b71106dd1..88afaae8b80d3 100644 --- a/stdarch/crates/core_arch/src/aarch64/neon/generated.rs +++ b/stdarch/crates/core_arch/src/aarch64/neon/generated.rs @@ -1565,7 +1565,7 @@ pub fn vceqh_f16(a: f16, b: f16) -> u16 { #[inline(always)] #[cfg_attr(test, assert_instr(fcmeq))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t { let b: f16x4 = f16x4::new(0.0, 0.0, 0.0, 0.0); @@ -1576,7 +1576,7 @@ pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcmeq))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t { let b: f16x8 = f16x8::new(0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0); @@ -4092,7 +4092,7 @@ pub fn vcmlaq_rot90_laneq_f32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_f32( @@ -4113,7 +4113,7 @@ pub fn vcopy_lane_f32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { @@ -4137,7 +4137,7 @@ pub fn vcopy_lane_s8(a: int8x8_t, b: int8x8_ #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { @@ -4157,7 +4157,7 @@ pub fn vcopy_lane_s16(a: int16x4_t, b: int16 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { @@ -4175,7 +4175,7 @@ pub fn vcopy_lane_s32(a: int32x2_t, b: int32 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { @@ -4199,7 +4199,7 @@ pub fn vcopy_lane_u8(a: uint8x8_t, b: uint8x #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u16( @@ -4222,7 +4222,7 @@ pub fn vcopy_lane_u16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_u32( @@ -4243,7 +4243,7 @@ pub fn vcopy_lane_u32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { @@ -4267,7 +4267,7 @@ pub fn vcopy_lane_p8(a: poly8x8_t, b: poly8x #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_lane_p16( @@ -4290,7 +4290,7 @@ pub fn vcopy_lane_p16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_f32( @@ -4312,7 +4312,7 @@ pub fn vcopy_laneq_f32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s8(a: int8x8_t, b: int8x16_t) -> int8x8_t { @@ -4338,7 +4338,7 @@ pub fn vcopy_laneq_s8(a: int8x8_t, b: int8x1 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s16( @@ -4362,7 +4362,7 @@ pub fn vcopy_laneq_s16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_s32( @@ -4384,7 +4384,7 @@ pub fn vcopy_laneq_s32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u8( @@ -4413,7 +4413,7 @@ pub fn vcopy_laneq_u8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u16( @@ -4437,7 +4437,7 @@ pub fn vcopy_laneq_u16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_u32( @@ -4459,7 +4459,7 @@ pub fn vcopy_laneq_u32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_p8( @@ -4488,7 +4488,7 @@ pub fn vcopy_laneq_p8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopy_laneq_p16( @@ -4624,7 +4624,7 @@ pub fn vcopyq_lane_p64( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s8(a: int8x16_t, b: int8x8_t) -> int8x16_t { @@ -4994,7 +4994,7 @@ pub fn vcopyq_lane_s8(a: int8x16_t, b: int8x #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s16( @@ -5022,7 +5022,7 @@ pub fn vcopyq_lane_s16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_s32( @@ -5046,7 +5046,7 @@ pub fn vcopyq_lane_s32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u8( @@ -5419,7 +5419,7 @@ pub fn vcopyq_lane_u8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u16( @@ -5447,7 +5447,7 @@ pub fn vcopyq_lane_u16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_u32( @@ -5471,7 +5471,7 @@ pub fn vcopyq_lane_u32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_p8( @@ -5844,7 +5844,7 @@ pub fn vcopyq_lane_p8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_lane_p16( @@ -5872,7 +5872,7 @@ pub fn vcopyq_lane_p16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_f32( @@ -5895,7 +5895,7 @@ pub fn vcopyq_laneq_f32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_f64( @@ -5916,7 +5916,7 @@ pub fn vcopyq_laneq_f64( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s8( @@ -6287,7 +6287,7 @@ pub fn vcopyq_laneq_s8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s16( @@ -6314,7 +6314,7 @@ pub fn vcopyq_laneq_s16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s32( @@ -6337,7 +6337,7 @@ pub fn vcopyq_laneq_s32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_s64( @@ -6358,7 +6358,7 @@ pub fn vcopyq_laneq_s64( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u8( @@ -6729,7 +6729,7 @@ pub fn vcopyq_laneq_u8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u16( @@ -6756,7 +6756,7 @@ pub fn vcopyq_laneq_u16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u32( @@ -6779,7 +6779,7 @@ pub fn vcopyq_laneq_u32( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_u64( @@ -6800,7 +6800,7 @@ pub fn vcopyq_laneq_u64( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p8( @@ -7171,7 +7171,7 @@ pub fn vcopyq_laneq_p8( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p16( @@ -7198,7 +7198,7 @@ pub fn vcopyq_laneq_p16( #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"] #[inline(always)] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vcopyq_laneq_p64( @@ -7283,7 +7283,7 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtn2))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t { vcombine_f16(a, vcvt_f16_f32(b)) @@ -7293,7 +7293,7 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtl2))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t { vcvt_f32_f16(vget_high_f16(a)) @@ -7532,7 +7532,7 @@ pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -7549,7 +7549,7 @@ pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtas))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -7630,7 +7630,7 @@ pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -7647,7 +7647,7 @@ pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtau))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -8218,7 +8218,7 @@ pub fn vcvth_u64_f16(a: f16) -> u64 { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -8235,7 +8235,7 @@ pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtms))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -8316,7 +8316,7 @@ pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -8333,7 +8333,7 @@ pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtmu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -8566,7 +8566,7 @@ pub fn vcvtmd_u64_f64(a: f64) -> u64 { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -8583,7 +8583,7 @@ pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtns))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -8664,7 +8664,7 @@ pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -8681,7 +8681,7 @@ pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtnu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -8914,7 +8914,7 @@ pub fn vcvtnd_u64_f64(a: f64) -> u64 { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t { unsafe extern "unadjusted" { @@ -8931,7 +8931,7 @@ pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtps))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t { unsafe extern "unadjusted" { @@ -9012,7 +9012,7 @@ pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t { unsafe extern "unadjusted" { @@ -9029,7 +9029,7 @@ pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fcvtpu))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t { unsafe extern "unadjusted" { @@ -9493,7 +9493,7 @@ pub fn vcvtxd_f32_f64(a: f64) -> f32 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fdiv))] pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -9503,7 +9503,7 @@ pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fdiv))] pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -10108,7 +10108,7 @@ pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfma_lane_f16( a: float16x4_t, @@ -10124,7 +10124,7 @@ pub fn vfma_lane_f16( #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfma_laneq_f16( a: float16x4_t, @@ -10140,7 +10140,7 @@ pub fn vfma_laneq_f16( #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmaq_lane_f16( a: float16x8_t, @@ -10156,7 +10156,7 @@ pub fn vfmaq_lane_f16( #[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmaq_laneq_f16( a: float16x8_t, @@ -10434,7 +10434,7 @@ pub fn vfmad_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal2))] pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10452,7 +10452,7 @@ pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3 #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal2))] pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10472,7 +10472,7 @@ pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_lane_high_f16( r: float32x2_t, @@ -10489,7 +10489,7 @@ pub fn vfmlal_lane_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_laneq_high_f16( r: float32x2_t, @@ -10506,7 +10506,7 @@ pub fn vfmlal_laneq_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_lane_high_f16( r: float32x4_t, @@ -10523,7 +10523,7 @@ pub fn vfmlalq_lane_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_laneq_high_f16( r: float32x4_t, @@ -10540,7 +10540,7 @@ pub fn vfmlalq_laneq_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_lane_low_f16( r: float32x2_t, @@ -10557,7 +10557,7 @@ pub fn vfmlal_lane_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlal_laneq_low_f16( r: float32x2_t, @@ -10574,7 +10574,7 @@ pub fn vfmlal_laneq_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_lane_low_f16( r: float32x4_t, @@ -10591,7 +10591,7 @@ pub fn vfmlalq_lane_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlalq_laneq_low_f16( r: float32x4_t, @@ -10606,7 +10606,7 @@ pub fn vfmlalq_laneq_low_f16( #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal))] pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10624,7 +10624,7 @@ pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32 #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlal))] pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10642,7 +10642,7 @@ pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3 #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl2))] pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10660,7 +10660,7 @@ pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3 #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl2))] pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10680,7 +10680,7 @@ pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_lane_high_f16( r: float32x2_t, @@ -10697,7 +10697,7 @@ pub fn vfmlsl_lane_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_laneq_high_f16( r: float32x2_t, @@ -10714,7 +10714,7 @@ pub fn vfmlsl_laneq_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_lane_high_f16( r: float32x4_t, @@ -10731,7 +10731,7 @@ pub fn vfmlslq_lane_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_laneq_high_f16( r: float32x4_t, @@ -10748,7 +10748,7 @@ pub fn vfmlslq_laneq_high_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_lane_low_f16( r: float32x2_t, @@ -10765,7 +10765,7 @@ pub fn vfmlsl_lane_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlsl_laneq_low_f16( r: float32x2_t, @@ -10782,7 +10782,7 @@ pub fn vfmlsl_laneq_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_lane_low_f16( r: float32x4_t, @@ -10799,7 +10799,7 @@ pub fn vfmlslq_lane_low_f16( #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmlslq_laneq_low_f16( r: float32x4_t, @@ -10814,7 +10814,7 @@ pub fn vfmlslq_laneq_low_f16( #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl))] pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32x2_t { @@ -10832,7 +10832,7 @@ pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32 #[inline(always)] #[target_feature(enable = "neon,fp16")] #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmlsl))] pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float32x4_t { @@ -10863,7 +10863,7 @@ pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfms_lane_f16( a: float16x4_t, @@ -10879,7 +10879,7 @@ pub fn vfms_lane_f16( #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfms_laneq_f16( a: float16x4_t, @@ -10895,7 +10895,7 @@ pub fn vfms_laneq_f16( #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmsq_lane_f16( a: float16x8_t, @@ -10911,7 +10911,7 @@ pub fn vfmsq_lane_f16( #[cfg_attr(test, assert_instr(fmls, LANE = 0))] #[rustc_legacy_const_generics(3)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vfmsq_laneq_f16( a: float16x8_t, @@ -11488,16 +11488,9 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v1f64.p0" - )] - fn _vld1_f64_x2(a: *const f64) -> float64x1x2_t; - } - _vld1_f64_x2(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1_f64_x2(ptr: *const f64) -> float64x1x2_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"] @@ -11506,16 +11499,9 @@ pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v1f64.p0" - )] - fn _vld1_f64_x3(a: *const f64) -> float64x1x3_t; - } - _vld1_f64_x3(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1_f64_x3(ptr: *const f64) -> float64x1x3_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"] @@ -11524,16 +11510,9 @@ pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v1f64.p0" - )] - fn _vld1_f64_x4(a: *const f64) -> float64x1x4_t; - } - _vld1_f64_x4(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1_f64_x4(ptr: *const f64) -> float64x1x4_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"] @@ -11542,16 +11521,9 @@ pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2f64.p0" - )] - fn _vld1q_f64_x2(a: *const f64) -> float64x2x2_t; - } - _vld1q_f64_x2(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1q_f64_x2(ptr: *const f64) -> float64x2x2_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"] @@ -11560,16 +11532,9 @@ pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2f64.p0" - )] - fn _vld1q_f64_x3(a: *const f64) -> float64x2x3_t; - } - _vld1q_f64_x3(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1q_f64_x3(ptr: *const f64) -> float64x2x3_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"] @@ -11578,16 +11543,9 @@ pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld1))] -pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2f64.p0" - )] - fn _vld1q_f64_x4(a: *const f64) -> float64x2x4_t; - } - _vld1q_f64_x4(a) +#[cfg_attr(test, assert_instr(ld))] +pub unsafe fn vld1q_f64_x4(ptr: *const f64) -> float64x2x4_t { + crate::ptr::read_unaligned(ptr.cast()) } #[doc = "Load single 2-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"] @@ -11652,14 +11610,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld2.v1f64.p0" - )] - fn _vld2_f64(ptr: *const float64x1_t) -> float64x1x2_t; - } - _vld2_f64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"] @@ -11962,28 +11913,12 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld2))] pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { transmute(vld2q_s64(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld2))] -pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { - let mut ret_val: uint64x2x2_t = transmute(vld2q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} #[doc = "Load single 3-element structure and replicate to all lanes of three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"] #[doc = "## Safety"] @@ -12047,14 +11982,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v1f64.p0" - )] - fn _vld3_f64(ptr: *const float64x1_t) -> float64x1x3_t; - } - _vld3_f64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"] @@ -12389,29 +12317,12 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { transmute(vld3q_s64(transmute(a))) } -#[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld3))] -pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { - let mut ret_val: uint64x2x3_t = transmute(vld3q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} #[doc = "Load single 4-element structure and replicate to all lanes of four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"] #[doc = "## Safety"] @@ -12475,14 +12386,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v1f64.p0" - )] - fn _vld4_f64(ptr: *const float64x1_t) -> float64x1x4_t; - } - _vld4_f64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"] @@ -12825,30 +12729,12 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { transmute(vld4q_s64(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(ld4))] -pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { - let mut ret_val: uint64x2x4_t = transmute(vld4q_s64(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"] #[doc = "## Safety"] @@ -12858,6 +12744,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) -> int64x1_t { static_assert!(LANE == 0); let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64); @@ -12876,6 +12763,7 @@ pub unsafe fn vldap1_lane_s64(ptr: *const i64, src: int64x1_t) #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64); @@ -12894,6 +12782,7 @@ pub unsafe fn vldap1q_lane_s64(ptr: *const i64, src: int64x2_t) #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12907,6 +12796,7 @@ pub unsafe fn vldap1q_lane_f64(ptr: *const f64, src: float64x2_ #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) -> uint64x1_t { static_assert!(LANE == 0); transmute(vldap1_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12920,6 +12810,7 @@ pub unsafe fn vldap1_lane_u64(ptr: *const u64, src: uint64x1_t) #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12933,6 +12824,7 @@ pub unsafe fn vldap1q_lane_u64(ptr: *const u64, src: uint64x2_t #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) -> poly64x1_t { static_assert!(LANE == 0); transmute(vldap1_lane_s64::(ptr as *mut i64, transmute(src))) @@ -12946,6 +12838,7 @@ pub unsafe fn vldap1_lane_p64(ptr: *const p64, src: poly64x1_t) #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub unsafe fn vldap1q_lane_p64(ptr: *const p64, src: poly64x2_t) -> poly64x2_t { static_assert_uimm_bits!(LANE, 1); transmute(vldap1q_lane_s64::(ptr as *mut i64, transmute(src))) @@ -15078,7 +14971,7 @@ pub fn vmul_lane_f64(a: float64x1_t, b: float64x1_t) -> float64 #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmul_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); @@ -15095,7 +14988,7 @@ pub fn vmul_laneq_f16(a: float16x4_t, b: float16x8_t) -> float1 #[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); @@ -15602,7 +15495,7 @@ pub fn vmuld_laneq_f64(a: f64, b: float64x2_t) -> f64 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmulx))] pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -15619,7 +15512,7 @@ pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmulx))] pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -15702,7 +15595,7 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulx_lane_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 2); @@ -15719,7 +15612,7 @@ pub fn vmulx_lane_f16(a: float16x4_t, b: float16x4_t) -> float1 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulx_laneq_f16(a: float16x4_t, b: float16x8_t) -> float16x4_t { static_assert_uimm_bits!(LANE, 3); @@ -15736,7 +15629,7 @@ pub fn vmulx_laneq_f16(a: float16x4_t, b: float16x8_t) -> float #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxq_lane_f16(a: float16x8_t, b: float16x4_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 2); @@ -15766,7 +15659,7 @@ pub fn vmulxq_lane_f16(a: float16x8_t, b: float16x4_t) -> float #[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vmulxq_laneq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { static_assert_uimm_bits!(LANE, 3); @@ -16128,18 +16021,15 @@ pub fn vpaddd_u64(a: uint64x2_t) -> u64 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(faddp))] pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v8f16" - )] - fn _vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + simd_add(even, odd) } - unsafe { _vpaddq_f16(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"] @@ -16148,14 +16038,11 @@ pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v4f32" - )] - fn _vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + simd_add(even, odd) } - unsafe { _vpaddq_f32(a, b) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"] @@ -16164,14 +16051,11 @@ pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(faddp))] pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.faddp.v2f64" - )] - fn _vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + simd_add(even, odd) } - unsafe { _vpaddq_f64(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"] @@ -16180,14 +16064,11 @@ pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v16i8" - )] - fn _vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>()); + simd_add(even, odd) } - unsafe { _vpaddq_s8(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"] @@ -16196,14 +16077,11 @@ pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v8i16" - )] - fn _vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + simd_add(even, odd) } - unsafe { _vpaddq_s16(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"] @@ -16212,14 +16090,11 @@ pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v4i32" - )] - fn _vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + simd_add(even, odd) } - unsafe { _vpaddq_s32(a, b) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"] @@ -16228,126 +16103,69 @@ pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.addp.v2i64" - )] - fn _vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + unsafe { + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + simd_add(even, odd) } - unsafe { _vpaddq_s64(a, b) } -} -#[doc = "Add Pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(addp))] -pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - unsafe { transmute(vpaddq_s8(transmute(a), transmute(b))) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; unsafe { - let ret_val: uint8x16_t = transmute(vpaddq_s8(transmute(a), transmute(b))); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<16>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<16>()); + simd_add(even, odd) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"] #[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(addp))] -pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - unsafe { transmute(vpaddq_s16(transmute(a), transmute(b))) } -} -#[doc = "Add Pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"] -#[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - let a: uint16x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint16x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; unsafe { - let ret_val: uint16x8_t = transmute(vpaddq_s16(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<8>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<8>()); + simd_add(even, odd) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"] #[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(addp))] -pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - unsafe { transmute(vpaddq_s32(transmute(a), transmute(b))) } -} -#[doc = "Add Pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"] -#[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) }; - let b: uint32x4_t = unsafe { simd_shuffle!(b, b, [3, 2, 1, 0]) }; unsafe { - let ret_val: uint32x4_t = transmute(vpaddq_s32(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0]) + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<4>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<4>()); + simd_add(even, odd) } } #[doc = "Add Pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"] #[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -#[cfg_attr(test, assert_instr(addp))] -pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - unsafe { transmute(vpaddq_s64(transmute(a), transmute(b))) } -} -#[doc = "Add Pairwise"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"] -#[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(addp))] pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - let a: uint64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) }; - let b: uint64x2_t = unsafe { simd_shuffle!(b, b, [1, 0]) }; unsafe { - let ret_val: uint64x2_t = transmute(vpaddq_s64(transmute(a), transmute(b))); - simd_shuffle!(ret_val, ret_val, [1, 0]) + let even = simd_shuffle!(a, b, crate::core_arch::macros::even::<2>()); + let odd = simd_shuffle!(a, b, crate::core_arch::macros::odd::<2>()); + simd_add(even, odd) } } #[doc = "Floating-point add pairwise"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxp))] pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16364,7 +16182,7 @@ pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxp))] pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -16381,7 +16199,7 @@ pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16398,7 +16216,7 @@ pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fmaxnmp))] pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -16655,7 +16473,7 @@ pub fn vpmaxs_f32(a: float32x2_t) -> f32 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminp))] pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16672,7 +16490,7 @@ pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminp))] pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -16689,7 +16507,7 @@ pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnmp))] pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -16706,7 +16524,7 @@ pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(fminnmp))] pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -19732,7 +19550,6 @@ pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19740,38 +19557,8 @@ pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19779,43 +19566,8 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t { - let mut a: uint8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19823,38 +19575,8 @@ pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl2(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(a.0), transmute(a.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19862,41 +19584,7 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t { - let mut a: poly8x16x2_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(vqtbl2q(transmute(a.0), transmute(a.1), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"] #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] @@ -19948,7 +19636,6 @@ pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -19956,46 +19643,8 @@ pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = - transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20003,51 +19652,8 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t { - let mut a: uint8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = - transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20055,46 +19661,8 @@ pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = - transmute(vqtbl3(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20102,48 +19670,6 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t { - let mut a: poly8x16x3_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = - transmute(vqtbl3q(transmute(a.0), transmute(a.1), transmute(a.2), b)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -20208,7 +19734,6 @@ pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20224,58 +19749,8 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( - a.3, - a.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20291,63 +19766,8 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t { - let mut a: uint8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( - a.3, - a.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vqtbl4q( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20363,58 +19783,8 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( - a.3, - a.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl4( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20429,60 +19799,6 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { )) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t { - let mut a: poly8x16x4_t = a; - a.0 = unsafe { - simd_shuffle!( - a.0, - a.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.1 = unsafe { - simd_shuffle!( - a.1, - a.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.2 = unsafe { - simd_shuffle!( - a.2, - a.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - a.3 = unsafe { - simd_shuffle!( - a.3, - a.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let b: uint8x16_t = - unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(vqtbl4q( - transmute(a.0), - transmute(a.1), - transmute(a.2), - transmute(a.3), - b, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1)"] #[inline(always)] @@ -20622,7 +19938,6 @@ pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20630,39 +19945,8 @@ pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] #[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x16x2_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] -#[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20670,46 +19954,8 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t { - let mut b: uint8x16x2_t = b; - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = - transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20717,39 +19963,8 @@ pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x16x2_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbx2(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20757,43 +19972,6 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { unsafe { transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t { - let mut b: poly8x16x2_t = b; - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = - transmute(vqtbx2q(transmute(a), transmute(b.0), transmute(b.1), c)); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -20853,7 +20031,6 @@ pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20869,52 +20046,8 @@ pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x16x3_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20930,58 +20063,8 @@ pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t { - let mut b: uint8x16x3_t = b; - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vqtbx3q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -20997,52 +20080,8 @@ pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x16x3_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbx3( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21058,55 +20097,6 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t { - let mut b: poly8x16x3_t = b; - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x16_t = transmute(vqtbx3q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -21187,7 +20177,6 @@ pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21204,60 +20193,8 @@ pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x16x4_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( - b.3, - b.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21274,66 +20211,8 @@ pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t { - let mut b: uint8x16x4_t = b; - let a: uint8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( - b.3, - b.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x16_t = transmute(vqtbx4q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -21350,130 +20229,21 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x16x4_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( - b.3, - b.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbx4( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { - unsafe { - transmute(vqtbx4q( - transmute(a), - transmute(b.0), - transmute(b.1), - transmute(b.2), - transmute(b.3), - c, - )) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t { - let mut b: poly8x16x4_t = b; - let a: poly8x16_t = - unsafe { simd_shuffle!(a, a, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { - simd_shuffle!( - b.0, - b.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.1 = unsafe { - simd_shuffle!( - b.1, - b.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.2 = unsafe { - simd_shuffle!( - b.2, - b.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - b.3 = unsafe { - simd_shuffle!( - b.3, - b.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - let c: uint8x16_t = - unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) }; unsafe { - let ret_val: poly8x16_t = transmute(vqtbx4q( + transmute(vqtbx4q( transmute(a), transmute(b.0), transmute(b.1), transmute(b.2), transmute(b.3), c, - )); - simd_shuffle!( - ret_val, - ret_val, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) + )) } } #[doc = "Rotate and exclusive OR"] @@ -21832,7 +20602,7 @@ pub fn vrecpxh_f16(a: f16) -> f16 { #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { @@ -21843,7 +20613,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { @@ -21855,7 +20625,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t { #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { @@ -21866,7 +20636,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { @@ -21881,7 +20651,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t { #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { @@ -21892,7 +20662,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { @@ -21906,7 +20676,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t { #[inline(always)] #[cfg(target_endian = "little")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { @@ -21917,7 +20687,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { #[inline(always)] #[cfg(target_endian = "big")] #[target_feature(enable = "neon")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(nop))] pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t { @@ -23496,7 +22266,7 @@ pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintz))] pub fn vrnd_f16(a: float16x4_t) -> float16x4_t { @@ -23506,7 +22276,7 @@ pub fn vrnd_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintz))] pub fn vrndq_f16(a: float16x8_t) -> float16x8_t { @@ -23552,7 +22322,7 @@ pub fn vrndq_f64(a: float64x2_t) -> float64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinta))] pub fn vrnda_f16(a: float16x4_t) -> float16x4_t { @@ -23562,7 +22332,7 @@ pub fn vrnda_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinta))] pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t { @@ -23628,7 +22398,7 @@ pub fn vrndh_f16(a: f16) -> f16 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinti))] pub fn vrndi_f16(a: float16x4_t) -> float16x4_t { @@ -23645,7 +22415,7 @@ pub fn vrndi_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frinti))] pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t { @@ -23743,7 +22513,7 @@ pub fn vrndih_f16(a: f16) -> f16 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintm))] pub fn vrndm_f16(a: float16x4_t) -> float16x4_t { @@ -23753,7 +22523,7 @@ pub fn vrndm_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintm))] pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t { @@ -23874,7 +22644,7 @@ pub fn vrndns_f32(a: f32) -> f32 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintp))] pub fn vrndp_f16(a: float16x4_t) -> float16x4_t { @@ -23884,7 +22654,7 @@ pub fn vrndp_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintp))] pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t { @@ -23940,7 +22710,7 @@ pub fn vrndph_f16(a: f16) -> f16 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintx))] pub fn vrndx_f16(a: float16x4_t) -> float16x4_t { @@ -23950,7 +22720,7 @@ pub fn vrndx_f16(a: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(test, assert_instr(frintx))] pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t { @@ -25453,7 +24223,7 @@ pub fn vsqadds_u32(a: u32, b: i32) -> u32 { #[inline(always)] #[cfg_attr(test, assert_instr(fsqrt))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t { unsafe { simd_fsqrt(a) } @@ -25463,7 +24233,7 @@ pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t { #[inline(always)] #[cfg_attr(test, assert_instr(fsqrt))] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t { unsafe { simd_fsqrt(a) } @@ -25523,14 +24293,7 @@ pub fn vsqrth_f16(a: f16) -> f16 { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v8i8" - )] - fn _vsri_n_s8(a: int8x8_t, b: int8x8_t, n: i32) -> int8x8_t; - } - unsafe { _vsri_n_s8(a, b, N) } + unsafe { super::shift_right_and_insert!(u8, 8, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"] @@ -25541,14 +24304,7 @@ pub fn vsri_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v16i8" - )] - fn _vsriq_n_s8(a: int8x16_t, b: int8x16_t, n: i32) -> int8x16_t; - } - unsafe { _vsriq_n_s8(a, b, N) } + unsafe { super::shift_right_and_insert!(u8, 16, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"] @@ -25559,14 +24315,7 @@ pub fn vsriq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v4i16" - )] - fn _vsri_n_s16(a: int16x4_t, b: int16x4_t, n: i32) -> int16x4_t; - } - unsafe { _vsri_n_s16(a, b, N) } + unsafe { super::shift_right_and_insert!(u16, 4, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"] @@ -25577,14 +24326,7 @@ pub fn vsri_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v8i16" - )] - fn _vsriq_n_s16(a: int16x8_t, b: int16x8_t, n: i32) -> int16x8_t; - } - unsafe { _vsriq_n_s16(a, b, N) } + unsafe { super::shift_right_and_insert!(u16, 8, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"] @@ -25595,14 +24337,7 @@ pub fn vsriq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v2i32" - )] - fn _vsri_n_s32(a: int32x2_t, b: int32x2_t, n: i32) -> int32x2_t; - } - unsafe { _vsri_n_s32(a, b, N) } + unsafe { super::shift_right_and_insert!(u32, 2, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"] @@ -25613,14 +24348,7 @@ pub fn vsri_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v4i32" - )] - fn _vsriq_n_s32(a: int32x4_t, b: int32x4_t, n: i32) -> int32x4_t; - } - unsafe { _vsriq_n_s32(a, b, N) } + unsafe { super::shift_right_and_insert!(u32, 4, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"] @@ -25631,14 +24359,7 @@ pub fn vsriq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { static_assert!(N >= 1 && N <= 64); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v1i64" - )] - fn _vsri_n_s64(a: int64x1_t, b: int64x1_t, n: i32) -> int64x1_t; - } - unsafe { _vsri_n_s64(a, b, N) } + unsafe { super::shift_right_and_insert!(u64, 1, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"] @@ -25649,14 +24370,7 @@ pub fn vsri_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub fn vsriq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { static_assert!(N >= 1 && N <= 64); - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.vsri.v2i64" - )] - fn _vsriq_n_s64(a: int64x2_t, b: int64x2_t, n: i32) -> int64x2_t; - } - unsafe { _vsriq_n_s64(a, b, N) } + unsafe { super::shift_right_and_insert!(u64, 2, N, a, b) } } #[doc = "Shift Right and Insert (immediate)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"] @@ -25818,7 +24532,7 @@ pub fn vsriq_n_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(bfxil, N = 2))] pub fn vsrid_n_s64(a: i64, b: i64) -> i64 { static_assert!(N >= 1 && N <= 64); unsafe { transmute(vsri_n_s64::(transmute(a), transmute(b))) } @@ -25829,7 +24543,7 @@ pub fn vsrid_n_s64(a: i64, b: i64) -> i64 { #[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[rustc_legacy_const_generics(2)] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(bfxil, N = 2))] pub fn vsrid_n_u64(a: u64, b: u64) -> u64 { static_assert!(N >= 1 && N <= 64); unsafe { transmute(vsri_n_u64::(transmute(a), transmute(b))) } @@ -27122,6 +25836,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { static_assert!(LANE == 0); unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27133,6 +25848,7 @@ pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { static_assert_uimm_bits!(LANE, 1); unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27144,6 +25860,7 @@ pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { static_assert!(LANE == 0); unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27155,6 +25872,7 @@ pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { static_assert_uimm_bits!(LANE, 1); unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27166,6 +25884,7 @@ pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { static_assert!(LANE == 0); unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27177,6 +25896,7 @@ pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { static_assert_uimm_bits!(LANE, 1); unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } @@ -27188,6 +25908,7 @@ pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { static_assert!(LANE == 0); let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; @@ -27203,6 +25924,7 @@ pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] +#[cfg(target_has_atomic = "64")] pub fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { static_assert_uimm_bits!(LANE, 1); let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; @@ -27462,7 +26184,6 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27470,26 +26191,8 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x2_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl1(transmute(vcombine_u8(a.0, a.1)), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27497,23 +26200,6 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x2_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl1(transmute(vcombine_p8(a.0, a.1)), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -27529,7 +26215,6 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27541,31 +26226,8 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x3_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = uint8x16x2_t( - vcombine_u8(a.0, a.1), - vcombine_u8(a.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27577,28 +26239,6 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x3_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = poly8x16x2_t( - vcombine_p8(a.0, a.1), - vcombine_p8(a.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -27611,7 +26251,6 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t { #[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27620,29 +26259,8 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } #[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t { - let mut a: uint8x8x4_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = uint8x16x2_t(vcombine_u8(a.0, a.1), vcombine_u8(a.2, a.3)); - unsafe { - let ret_val: uint8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27650,26 +26268,6 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3)); unsafe { transmute(vqtbl2(transmute(x.0), transmute(x.1), b)) } } -#[doc = "Table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t { - let mut a: poly8x8x4_t = a; - a.0 = unsafe { simd_shuffle!(a.0, a.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.1 = unsafe { simd_shuffle!(a.1, a.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.2 = unsafe { simd_shuffle!(a.2, a.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - a.3 = unsafe { simd_shuffle!(a.3, a.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = poly8x16x2_t(vcombine_p8(a.0, a.1), vcombine_p8(a.2, a.3)); - unsafe { - let ret_val: poly8x8_t = transmute(vqtbl2(transmute(x.0), transmute(x.1), b)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"] #[inline(always)] @@ -27739,7 +26337,6 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27747,28 +26344,8 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x2_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = - transmute(vqtbx1(transmute(a), transmute(vcombine_u8(b.0, b.1)), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27776,25 +26353,6 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { unsafe { transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)) } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x2_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = - transmute(vqtbx1(transmute(a), transmute(vcombine_p8(b.0, b.1)), c)); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -27821,7 +26379,6 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27839,36 +26396,8 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x3_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = uint8x16x2_t( - vcombine_u8(b.0, b.1), - vcombine_u8(b.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { - let ret_val: uint8x8_t = transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), - a, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27886,33 +26415,6 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x3_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let x = poly8x16x2_t( - vcombine_p8(b.0, b.1), - vcombine_p8(b.2, unsafe { crate::mem::zeroed() }), - ); - unsafe { - let ret_val: poly8x8_t = transmute(simd_select( - simd_lt::(transmute(c), transmute(u8x8::splat(24))), - transmute(vqtbx2(transmute(a), transmute(x.0), transmute(x.1), c)), - a, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"] #[inline(always)] #[target_feature(enable = "neon")] @@ -27931,7 +26433,6 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t { #[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27946,34 +26447,8 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { } } #[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t { - let mut b: uint8x8x4_t = b; - let a: uint8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: uint8x8_t = transmute(vqtbx2( - transmute(a), - transmute(vcombine_u8(b.0, b.1)), - transmute(vcombine_u8(b.2, b.3)), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} -#[doc = "Extended table look-up"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(tbx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] @@ -27987,36 +26462,11 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { )) } } -#[doc = "Extended table look-up"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tbx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { - let mut b: poly8x8x4_t = b; - let a: poly8x8_t = unsafe { simd_shuffle!(a, a, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.0 = unsafe { simd_shuffle!(b.0, b.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.1 = unsafe { simd_shuffle!(b.1, b.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.2 = unsafe { simd_shuffle!(b.2, b.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - b.3 = unsafe { simd_shuffle!(b.3, b.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - let c: uint8x8_t = unsafe { simd_shuffle!(c, c, [7, 6, 5, 4, 3, 2, 1, 0]) }; - unsafe { - let ret_val: poly8x8_t = transmute(vqtbx2( - transmute(a), - transmute(vcombine_p8(b.0, b.1)), - transmute(vcombine_p8(b.2, b.3)), - c, - )); - simd_shuffle!(ret_val, ret_val, [7, 6, 5, 4, 3, 2, 1, 0]) - } -} #[doc = "Transpose vectors"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -28026,7 +26476,7 @@ pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -28252,7 +26702,7 @@ pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -28262,7 +26712,7 @@ pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -28762,7 +27212,7 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -28772,7 +27222,7 @@ pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -28998,7 +27448,7 @@ pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -29008,7 +27458,7 @@ pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -29252,7 +27702,7 @@ pub fn vxarq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -29262,7 +27712,7 @@ pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { @@ -29488,7 +27938,7 @@ pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { @@ -29498,7 +27948,7 @@ pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"] #[inline(always)] #[target_feature(enable = "neon,fp16")] -#[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] #[cfg(not(target_arch = "arm64ec"))] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t { diff --git a/stdarch/crates/core_arch/src/aarch64/neon/mod.rs b/stdarch/crates/core_arch/src/aarch64/neon/mod.rs index b172b57f32543..2df4ba7443314 100644 --- a/stdarch/crates/core_arch/src/aarch64/neon/mod.rs +++ b/stdarch/crates/core_arch/src/aarch64/neon/mod.rs @@ -70,6 +70,30 @@ pub struct float64x2x4_t( pub float64x2_t, ); +/// Helper for the 'shift right and insert' functions. +macro_rules! shift_right_and_insert { + ($ty:ty, $width:literal, $N:expr, $a:expr, $b:expr) => {{ + type V = Simd<$ty, $width>; + + if $N as u32 == <$ty>::BITS { + $a + } else { + let a: V = transmute($a); + let b: V = transmute($b); + + let mask = <$ty>::MAX >> $N; + let kept: V = simd_and(a, V::splat(!mask)); + + let shift_counts = V::splat($N as $ty); + let shifted = simd_shr(b, shift_counts); + + transmute(simd_or(kept, shifted)) + } + }}; +} + +pub(crate) use shift_right_and_insert; + /// Duplicate vector element to vector or scalar #[inline] #[target_feature(enable = "neon")] @@ -569,47 +593,46 @@ mod tests { use crate::core_arch::aarch64::test_support::*; use crate::core_arch::arm_shared::test_support::*; use crate::core_arch::{aarch64::neon::*, aarch64::*, simd::*}; - use std::mem::transmute; use stdarch_test::simd_test; #[simd_test(enable = "neon")] - unsafe fn test_vadd_f64() { - let a = 1.; - let b = 8.; - let e = 9.; - let r: f64 = transmute(vadd_f64(transmute(a), transmute(b))); + fn test_vadd_f64() { + let a = f64x1::from_array([1.]); + let b = f64x1::from_array([8.]); + let e = f64x1::from_array([9.]); + let r = f64x1::from(vadd_f64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vaddq_f64() { + fn test_vaddq_f64() { let a = f64x2::new(1., 2.); let b = f64x2::new(8., 7.); let e = f64x2::new(9., 9.); - let r: f64x2 = transmute(vaddq_f64(transmute(a), transmute(b))); + let r = f64x2::from(vaddq_f64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vadd_s64() { - let a = 1_i64; - let b = 8_i64; - let e = 9_i64; - let r: i64 = transmute(vadd_s64(transmute(a), transmute(b))); + fn test_vadd_s64() { + let a = i64x1::from_array([1]); + let b = i64x1::from_array([8]); + let e = i64x1::from_array([9]); + let r = i64x1::from(vadd_s64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vadd_u64() { - let a = 1_u64; - let b = 8_u64; - let e = 9_u64; - let r: u64 = transmute(vadd_u64(transmute(a), transmute(b))); + fn test_vadd_u64() { + let a = u64x1::from_array([1]); + let b = u64x1::from_array([8]); + let e = u64x1::from_array([9]); + let r = u64x1::from(vadd_u64(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vaddd_s64() { + fn test_vaddd_s64() { let a = 1_i64; let b = 8_i64; let e = 9_i64; @@ -618,7 +641,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vaddd_u64() { + fn test_vaddd_u64() { let a = 1_u64; let b = 8_u64; let e = 9_u64; @@ -627,25 +650,25 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vext_p64() { - let a: i64x1 = i64x1::new(0); - let b: i64x1 = i64x1::new(1); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vext_p64::<0>(transmute(a), transmute(b))); + fn test_vext_p64() { + let a = u64x1::new(0); + let b = u64x1::new(1); + let e = u64x1::new(0); + let r = u64x1::from(vext_p64::<0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vext_f64() { - let a: f64x1 = f64x1::new(0.); - let b: f64x1 = f64x1::new(1.); - let e: f64x1 = f64x1::new(0.); - let r: f64x1 = transmute(vext_f64::<0>(transmute(a), transmute(b))); + fn test_vext_f64() { + let a = f64x1::new(0.); + let b = f64x1::new(1.); + let e = f64x1::new(0.); + let r = f64x1::from(vext_f64::<0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vshld_n_s64() { + fn test_vshld_n_s64() { let a: i64 = 1; let e: i64 = 4; let r: i64 = vshld_n_s64::<2>(a); @@ -653,7 +676,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vshld_n_u64() { + fn test_vshld_n_u64() { let a: u64 = 1; let e: u64 = 4; let r: u64 = vshld_n_u64::<2>(a); @@ -661,7 +684,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vshrd_n_s64() { + fn test_vshrd_n_s64() { let a: i64 = 4; let e: i64 = 1; let r: i64 = vshrd_n_s64::<2>(a); @@ -669,7 +692,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vshrd_n_u64() { + fn test_vshrd_n_u64() { let a: u64 = 4; let e: u64 = 1; let r: u64 = vshrd_n_u64::<2>(a); @@ -677,7 +700,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vsrad_n_s64() { + fn test_vsrad_n_s64() { let a: i64 = 1; let b: i64 = 4; let e: i64 = 2; @@ -686,7 +709,7 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vsrad_n_u64() { + fn test_vsrad_n_u64() { let a: u64 = 1; let b: u64 = 4; let e: u64 = 2; @@ -695,298 +718,567 @@ mod tests { } #[simd_test(enable = "neon")] - unsafe fn test_vdup_n_f64() { + fn test_vdup_n_f64() { let a: f64 = 3.3; let e = f64x1::new(3.3); - let r: f64x1 = transmute(vdup_n_f64(a)); + let r = f64x1::from(vdup_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vdup_n_p64() { + fn test_vdup_n_p64() { let a: u64 = 3; let e = u64x1::new(3); - let r: u64x1 = transmute(vdup_n_p64(a)); + let r = u64x1::from(vdup_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vdupq_n_f64() { + fn test_vdupq_n_f64() { let a: f64 = 3.3; let e = f64x2::new(3.3, 3.3); - let r: f64x2 = transmute(vdupq_n_f64(a)); + let r = f64x2::from(vdupq_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vdupq_n_p64() { + fn test_vdupq_n_p64() { let a: u64 = 3; let e = u64x2::new(3, 3); - let r: u64x2 = transmute(vdupq_n_p64(a)); + let r = u64x2::from(vdupq_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmov_n_p64() { + fn test_vmov_n_p64() { let a: u64 = 3; let e = u64x1::new(3); - let r: u64x1 = transmute(vmov_n_p64(a)); + let r = u64x1::from(vmov_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmov_n_f64() { + fn test_vmov_n_f64() { let a: f64 = 3.3; let e = f64x1::new(3.3); - let r: f64x1 = transmute(vmov_n_f64(a)); + let r = f64x1::from(vmov_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmovq_n_p64() { + fn test_vmovq_n_p64() { let a: u64 = 3; let e = u64x2::new(3, 3); - let r: u64x2 = transmute(vmovq_n_p64(a)); + let r = u64x2::from(vmovq_n_p64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vmovq_n_f64() { + fn test_vmovq_n_f64() { let a: f64 = 3.3; let e = f64x2::new(3.3, 3.3); - let r: f64x2 = transmute(vmovq_n_f64(a)); + let r = f64x2::from(vmovq_n_f64(a)); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_high_f64() { + fn test_vget_high_f64() { let a = f64x2::new(1.0, 2.0); let e = f64x1::new(2.0); - let r: f64x1 = transmute(vget_high_f64(transmute(a))); + let r = f64x1::from(vget_high_f64(a.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_high_p64() { + fn test_vget_high_p64() { let a = u64x2::new(1, 2); let e = u64x1::new(2); - let r: u64x1 = transmute(vget_high_p64(transmute(a))); + let r = u64x1::from(vget_high_p64(a.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_low_f64() { + fn test_vget_low_f64() { let a = f64x2::new(1.0, 2.0); let e = f64x1::new(1.0); - let r: f64x1 = transmute(vget_low_f64(transmute(a))); + let r = f64x1::from(vget_low_f64(a.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_low_p64() { + fn test_vget_low_p64() { let a = u64x2::new(1, 2); let e = u64x1::new(1); - let r: u64x1 = transmute(vget_low_p64(transmute(a))); + let r = u64x1::from(vget_low_p64(a.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vget_lane_f64() { + fn test_vget_lane_f64() { let v = f64x1::new(1.0); - let r = vget_lane_f64::<0>(transmute(v)); + let r = vget_lane_f64::<0>(v.into()); assert_eq!(r, 1.0); } #[simd_test(enable = "neon")] - unsafe fn test_vgetq_lane_f64() { + fn test_vgetq_lane_f64() { let v = f64x2::new(0.0, 1.0); - let r = vgetq_lane_f64::<1>(transmute(v)); + let r = vgetq_lane_f64::<1>(v.into()); assert_eq!(r, 1.0); - let r = vgetq_lane_f64::<0>(transmute(v)); + let r = vgetq_lane_f64::<0>(v.into()); assert_eq!(r, 0.0); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_lane_s64::<0, 0>(transmute(a), transmute(b))); + fn test_vcopy_lane_s64() { + let a = i64x1::new(1); + let b = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let r = i64x1::from(vcopy_lane_s64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcopy_lane_u64::<0, 0>(transmute(a), transmute(b))); + fn test_vcopy_lane_u64() { + let a = u64x1::new(1); + let b = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); + let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); + let r = u64x1::from(vcopy_lane_u64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_p64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_lane_p64::<0, 0>(transmute(a), transmute(b))); + fn test_vcopy_lane_p64() { + let a = u64x1::new(1); + let b = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let r = u64x1::from(vcopy_lane_p64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_f64() { - let a: f64 = 1.; - let b: f64 = 0.; - let e: f64 = 0.; - let r: f64 = transmute(vcopy_lane_f64::<0, 0>(transmute(a), transmute(b))); + fn test_vcopy_lane_f64() { + let a = f64x1::from_array([1.]); + let b = f64x1::from_array([0.]); + let e = f64x1::from_array([0.]); + let r = f64x1::from(vcopy_lane_f64::<0, 0>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_laneq_s64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_laneq_s64() { + let a = i64x1::new(1); + let b = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); + let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let r = i64x1::from(vcopy_laneq_s64::<0, 1>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcopy_laneq_u64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_laneq_u64() { + let a = u64x1::new(1); + let b = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); + let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); + let r = u64x1::from(vcopy_laneq_u64::<0, 1>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_p64() { - let a: i64x1 = i64x1::new(1); - let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vcopy_laneq_p64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_laneq_p64() { + let a = u64x1::new(1); + let b = u64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); + let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); + let r = u64x1::from(vcopy_laneq_p64::<0, 1>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_f64() { - let a: f64 = 1.; - let b: f64x2 = f64x2::new(0., 0.5); - let e: f64 = 0.5; - let r: f64 = transmute(vcopy_laneq_f64::<0, 1>(transmute(a), transmute(b))); + fn test_vcopy_laneq_f64() { + let a = f64x1::from_array([1.]); + let b = f64x2::from_array([0., 0.5]); + let e = f64x1::from_array([0.5]); + let r = f64x1::from(vcopy_laneq_f64::<0, 1>(a.into(), b.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vbsl_f64() { + fn test_vbsl_f64() { let a = u64x1::new(0x8000000000000000); let b = f64x1::new(-1.23f64); let c = f64x1::new(2.34f64); let e = f64x1::new(-2.34f64); - let r: f64x1 = transmute(vbsl_f64(transmute(a), transmute(b), transmute(c))); + let r = f64x1::from(vbsl_f64(a.into(), b.into(), c.into())); assert_eq!(r, e); } + #[simd_test(enable = "neon")] - unsafe fn test_vbsl_p64() { + fn test_vbsl_p64() { let a = u64x1::new(1); let b = u64x1::new(u64::MAX); let c = u64x1::new(u64::MIN); let e = u64x1::new(1); - let r: u64x1 = transmute(vbsl_p64(transmute(a), transmute(b), transmute(c))); + let r = u64x1::from(vbsl_p64(a.into(), b.into(), c.into())); assert_eq!(r, e); } + #[simd_test(enable = "neon")] - unsafe fn test_vbslq_f64() { + fn test_vbslq_f64() { let a = u64x2::new(1, 0x8000000000000000); let b = f64x2::new(f64::MAX, -1.23f64); let c = f64x2::new(f64::MIN, 2.34f64); let e = f64x2::new(f64::MIN, -2.34f64); - let r: f64x2 = transmute(vbslq_f64(transmute(a), transmute(b), transmute(c))); + let r = f64x2::from(vbslq_f64(a.into(), b.into(), c.into())); assert_eq!(r, e); } + #[simd_test(enable = "neon")] - unsafe fn test_vbslq_p64() { + fn test_vbslq_p64() { let a = u64x2::new(u64::MAX, 1); let b = u64x2::new(u64::MAX, u64::MAX); let c = u64x2::new(u64::MIN, u64::MIN); let e = u64x2::new(u64::MAX, 1); - let r: u64x2 = transmute(vbslq_p64(transmute(a), transmute(b), transmute(c))); + let r = u64x2::from(vbslq_p64(a.into(), b.into(), c.into())); assert_eq!(r, e); } #[simd_test(enable = "neon")] - unsafe fn test_vld1_f64() { + fn test_vld1_f64() { let a: [f64; 2] = [0., 1.]; let e = f64x1::new(1.); - let r: f64x1 = transmute(vld1_f64(a[1..].as_ptr())); + let r = unsafe { f64x1::from(vld1_f64(a[1..].as_ptr())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1q_f64() { + fn test_vld1q_f64() { let a: [f64; 3] = [0., 1., 2.]; let e = f64x2::new(1., 2.); - let r: f64x2 = transmute(vld1q_f64(a[1..].as_ptr())); + let r = unsafe { f64x2::from(vld1q_f64(a[1..].as_ptr())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1_dup_f64() { + fn test_vld1_dup_f64() { let a: [f64; 2] = [1., 42.]; let e = f64x1::new(42.); - let r: f64x1 = transmute(vld1_dup_f64(a[1..].as_ptr())); + let r = unsafe { f64x1::from(vld1_dup_f64(a[1..].as_ptr())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1q_dup_f64() { + fn test_vld1q_dup_f64() { let elem: f64 = 42.; let e = f64x2::new(42., 42.); - let r: f64x2 = transmute(vld1q_dup_f64(&elem)); + let r = unsafe { f64x2::from(vld1q_dup_f64(&elem)) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1_lane_f64() { + fn test_vld1_lane_f64() { let a = f64x1::new(0.); let elem: f64 = 42.; let e = f64x1::new(42.); - let r: f64x1 = transmute(vld1_lane_f64::<0>(&elem, transmute(a))); + let r = unsafe { f64x1::from(vld1_lane_f64::<0>(&elem, a.into())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vld1q_lane_f64() { + fn test_vld1q_lane_f64() { let a = f64x2::new(0., 1.); let elem: f64 = 42.; let e = f64x2::new(0., 42.); - let r: f64x2 = transmute(vld1q_lane_f64::<1>(&elem, transmute(a))); + let r = unsafe { f64x2::from(vld1q_lane_f64::<1>(&elem, a.into())) }; assert_eq!(r, e) } #[simd_test(enable = "neon")] - unsafe fn test_vst1_f64() { + fn test_vst1_f64() { let mut vals = [0_f64; 2]; let a = f64x1::new(1.); - vst1_f64(vals[1..].as_mut_ptr(), transmute(a)); + unsafe { + vst1_f64(vals[1..].as_mut_ptr(), a.into()); + } assert_eq!(vals[0], 0.); assert_eq!(vals[1], 1.); } #[simd_test(enable = "neon")] - unsafe fn test_vst1q_f64() { + fn test_vst1q_f64() { let mut vals = [0_f64; 3]; let a = f64x2::new(1., 2.); - vst1q_f64(vals[1..].as_mut_ptr(), transmute(a)); + unsafe { + vst1q_f64(vals[1..].as_mut_ptr(), a.into()); + } assert_eq!(vals[0], 0.); assert_eq!(vals[1], 1.); assert_eq!(vals[2], 2.); } + + macro_rules! wide_store_load_roundtrip { + ($elem_ty:ty, $len:expr, $vec_ty:ty, $store:expr, $load:expr) => { + let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty); + let a: $vec_ty = transmute(vals); + let mut tmp = [0 as $elem_ty; $len]; + $store(tmp.as_mut_ptr().cast(), a); + let r: $vec_ty = $load(tmp.as_ptr().cast()); + let out: [$elem_ty; $len] = transmute(r); + assert_eq!(out, vals); + }; + } + + macro_rules! wide_store_load_roundtrip_fp16 { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[simd_test(enable = "neon,fp16")] + #[cfg(not(target_arch = "arm64ec"))] + unsafe fn $name() { + wide_store_load_roundtrip! $args; + } + )* + }; + } + + wide_store_load_roundtrip_fp16! { + test_vld1_f16_x2(f16, 8, float16x4x2_t, vst1_f16_x2, vld1_f16_x2); + test_vld1_f16_x3(f16, 12, float16x4x3_t, vst1_f16_x3, vld1_f16_x3); + test_vld1_f16_x4(f16, 16, float16x4x4_t, vst1_f16_x4, vld1_f16_x4); + + test_vld1q_f16_x2(f16, 16, float16x8x2_t, vst1q_f16_x2, vld1q_f16_x2); + test_vld1q_f16_x3(f16, 24, float16x8x3_t, vst1q_f16_x3, vld1q_f16_x3); + test_vld1q_f16_x4(f16, 32, float16x8x4_t, vst1q_f16_x4, vld1q_f16_x4); + } + + macro_rules! wide_store_load_roundtrip_aes { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[simd_test(enable = "neon,aes")] + unsafe fn $name() { + wide_store_load_roundtrip! $args; + } + )* + }; + } + + wide_store_load_roundtrip_aes! { + test_vld1_p64_x2(p64, 2, poly64x1x2_t, vst1_p64_x2, vld1_p64_x2); + test_vld1_p64_x3(p64, 3, poly64x1x3_t, vst1_p64_x3, vld1_p64_x3); + test_vld1_p64_x4(p64, 4, poly64x1x4_t, vst1_p64_x4, vld1_p64_x4); + + test_vld1q_p64_x2(p64, 4, poly64x2x2_t, vst1q_p64_x2, vld1q_p64_x2); + test_vld1q_p64_x3(p64, 6, poly64x2x3_t, vst1q_p64_x3, vld1q_p64_x3); + test_vld1q_p64_x4(p64, 8, poly64x2x4_t, vst1q_p64_x4, vld1q_p64_x4); + } + + macro_rules! wide_store_load_roundtrip_neon { + ($( $name:ident $args:tt);* $(;)?) => { + $( + #[simd_test(enable = "neon")] + unsafe fn $name() { + wide_store_load_roundtrip! $args; + } + )* + }; + } + + wide_store_load_roundtrip_neon! { + test_vld1_f32_x2(f32, 4, float32x2x2_t, vst1_f32_x2, vld1_f32_x2); + test_vld1_f32_x3(f32, 6, float32x2x3_t, vst1_f32_x3, vld1_f32_x3); + test_vld1_f32_x4(f32, 8, float32x2x4_t, vst1_f32_x4, vld1_f32_x4); + + test_vld1q_f32_x2(f32, 8, float32x4x2_t, vst1q_f32_x2, vld1q_f32_x2); + test_vld1q_f32_x3(f32, 12, float32x4x3_t, vst1q_f32_x3, vld1q_f32_x3); + test_vld1q_f32_x4(f32, 16, float32x4x4_t, vst1q_f32_x4, vld1q_f32_x4); + + test_vld1_f64_x2(f64, 2, float64x1x2_t, vst1_f64_x2, vld1_f64_x2); + test_vld1_f64_x3(f64, 3, float64x1x3_t, vst1_f64_x3, vld1_f64_x3); + test_vld1_f64_x4(f64, 4, float64x1x4_t, vst1_f64_x4, vld1_f64_x4); + + test_vld1q_f64_x2(f64, 4, float64x2x2_t, vst1q_f64_x2, vld1q_f64_x2); + test_vld1q_f64_x3(f64, 6, float64x2x3_t, vst1q_f64_x3, vld1q_f64_x3); + test_vld1q_f64_x4(f64, 8, float64x2x4_t, vst1q_f64_x4, vld1q_f64_x4); + + test_vld1_s8_x2(i8, 16, int8x8x2_t, vst1_s8_x2, vld1_s8_x2); + test_vld1_s8_x3(i8, 24, int8x8x3_t, vst1_s8_x3, vld1_s8_x3); + test_vld1_s8_x4(i8, 32, int8x8x4_t, vst1_s8_x4, vld1_s8_x4); + + test_vld1q_s8_x2(i8, 32, int8x16x2_t, vst1q_s8_x2, vld1q_s8_x2); + test_vld1q_s8_x3(i8, 48, int8x16x3_t, vst1q_s8_x3, vld1q_s8_x3); + test_vld1q_s8_x4(i8, 64, int8x16x4_t, vst1q_s8_x4, vld1q_s8_x4); + + test_vld1_s16_x2(i16, 8, int16x4x2_t, vst1_s16_x2, vld1_s16_x2); + test_vld1_s16_x3(i16, 12, int16x4x3_t, vst1_s16_x3, vld1_s16_x3); + test_vld1_s16_x4(i16, 16, int16x4x4_t, vst1_s16_x4, vld1_s16_x4); + + test_vld1q_s16_x2(i16, 16, int16x8x2_t, vst1q_s16_x2, vld1q_s16_x2); + test_vld1q_s16_x3(i16, 24, int16x8x3_t, vst1q_s16_x3, vld1q_s16_x3); + test_vld1q_s16_x4(i16, 32, int16x8x4_t, vst1q_s16_x4, vld1q_s16_x4); + + test_vld1_s32_x2(i32, 4, int32x2x2_t, vst1_s32_x2, vld1_s32_x2); + test_vld1_s32_x3(i32, 6, int32x2x3_t, vst1_s32_x3, vld1_s32_x3); + test_vld1_s32_x4(i32, 8, int32x2x4_t, vst1_s32_x4, vld1_s32_x4); + + test_vld1q_s32_x2(i32, 8, int32x4x2_t, vst1q_s32_x2, vld1q_s32_x2); + test_vld1q_s32_x3(i32, 12, int32x4x3_t, vst1q_s32_x3, vld1q_s32_x3); + test_vld1q_s32_x4(i32, 16, int32x4x4_t, vst1q_s32_x4, vld1q_s32_x4); + + test_vld1_s64_x2(i64, 2, int64x1x2_t, vst1_s64_x2, vld1_s64_x2); + test_vld1_s64_x3(i64, 3, int64x1x3_t, vst1_s64_x3, vld1_s64_x3); + test_vld1_s64_x4(i64, 4, int64x1x4_t, vst1_s64_x4, vld1_s64_x4); + + test_vld1q_s64_x2(i64, 4, int64x2x2_t, vst1q_s64_x2, vld1q_s64_x2); + test_vld1q_s64_x3(i64, 6, int64x2x3_t, vst1q_s64_x3, vld1q_s64_x3); + test_vld1q_s64_x4(i64, 8, int64x2x4_t, vst1q_s64_x4, vld1q_s64_x4); + + test_vld1_u8_x2(u8, 16, uint8x8x2_t, vst1_u8_x2, vld1_u8_x2); + test_vld1_u8_x3(u8, 24, uint8x8x3_t, vst1_u8_x3, vld1_u8_x3); + test_vld1_u8_x4(u8, 32, uint8x8x4_t, vst1_u8_x4, vld1_u8_x4); + + test_vld1q_u8_x2(u8, 32, uint8x16x2_t, vst1q_u8_x2, vld1q_u8_x2); + test_vld1q_u8_x3(u8, 48, uint8x16x3_t, vst1q_u8_x3, vld1q_u8_x3); + test_vld1q_u8_x4(u8, 64, uint8x16x4_t, vst1q_u8_x4, vld1q_u8_x4); + + test_vld1_u16_x2(u16, 8, uint16x4x2_t, vst1_u16_x2, vld1_u16_x2); + test_vld1_u16_x3(u16, 12, uint16x4x3_t, vst1_u16_x3, vld1_u16_x3); + test_vld1_u16_x4(u16, 16, uint16x4x4_t, vst1_u16_x4, vld1_u16_x4); + + test_vld1q_u16_x2(u16, 16, uint16x8x2_t, vst1q_u16_x2, vld1q_u16_x2); + test_vld1q_u16_x3(u16, 24, uint16x8x3_t, vst1q_u16_x3, vld1q_u16_x3); + test_vld1q_u16_x4(u16, 32, uint16x8x4_t, vst1q_u16_x4, vld1q_u16_x4); + + test_vld1_u32_x2(u32, 4, uint32x2x2_t, vst1_u32_x2, vld1_u32_x2); + test_vld1_u32_x3(u32, 6, uint32x2x3_t, vst1_u32_x3, vld1_u32_x3); + test_vld1_u32_x4(u32, 8, uint32x2x4_t, vst1_u32_x4, vld1_u32_x4); + + test_vld1q_u32_x2(u32, 8, uint32x4x2_t, vst1q_u32_x2, vld1q_u32_x2); + test_vld1q_u32_x3(u32, 12, uint32x4x3_t, vst1q_u32_x3, vld1q_u32_x3); + test_vld1q_u32_x4(u32, 16, uint32x4x4_t, vst1q_u32_x4, vld1q_u32_x4); + + test_vld1_u64_x2(u64, 2, uint64x1x2_t, vst1_u64_x2, vld1_u64_x2); + test_vld1_u64_x3(u64, 3, uint64x1x3_t, vst1_u64_x3, vld1_u64_x3); + test_vld1_u64_x4(u64, 4, uint64x1x4_t, vst1_u64_x4, vld1_u64_x4); + + test_vld1q_u64_x2(u64, 4, uint64x2x2_t, vst1q_u64_x2, vld1q_u64_x2); + test_vld1q_u64_x3(u64, 6, uint64x2x3_t, vst1q_u64_x3, vld1q_u64_x3); + test_vld1q_u64_x4(u64, 8, uint64x2x4_t, vst1q_u64_x4, vld1q_u64_x4); + + test_vld1_p8_x2(p8, 16, poly8x8x2_t, vst1_p8_x2, vld1_p8_x2); + test_vld1_p8_x3(p8, 24, poly8x8x3_t, vst1_p8_x3, vld1_p8_x3); + test_vld1_p8_x4(p8, 32, poly8x8x4_t, vst1_p8_x4, vld1_p8_x4); + + test_vld1q_p8_x2(p8, 32, poly8x16x2_t, vst1q_p8_x2, vld1q_p8_x2); + test_vld1q_p8_x3(p8, 48, poly8x16x3_t, vst1q_p8_x3, vld1q_p8_x3); + test_vld1q_p8_x4(p8, 64, poly8x16x4_t, vst1q_p8_x4, vld1q_p8_x4); + + test_vld1_p16_x2(p16, 8, poly16x4x2_t, vst1_p16_x2, vld1_p16_x2); + test_vld1_p16_x3(p16, 12, poly16x4x3_t, vst1_p16_x3, vld1_p16_x3); + test_vld1_p16_x4(p16, 16, poly16x4x4_t, vst1_p16_x4, vld1_p16_x4); + + test_vld1q_p16_x2(p16, 16, poly16x8x2_t, vst1q_p16_x2, vld1q_p16_x2); + test_vld1q_p16_x3(p16, 24, poly16x8x3_t, vst1q_p16_x3, vld1q_p16_x3); + test_vld1q_p16_x4(p16, 32, poly16x8x4_t, vst1q_p16_x4, vld1q_p16_x4); + } + + wide_store_load_roundtrip_neon! { + test_vld2_f32_x2(f32, 4, float32x2x2_t, vst2_f32, vld2_f32); + test_vld2_f32_x3(f32, 6, float32x2x3_t, vst3_f32, vld3_f32); + test_vld2_f32_x4(f32, 8, float32x2x4_t, vst4_f32, vld4_f32); + + test_vld2q_f32_x2(f32, 8, float32x4x2_t, vst2q_f32, vld2q_f32); + test_vld3q_f32_x3(f32, 12, float32x4x3_t, vst3q_f32, vld3q_f32); + test_vld4q_f32_x4(f32, 16, float32x4x4_t, vst4q_f32, vld4q_f32); + + test_vld2_f64_x2(f64, 2, float64x1x2_t, vst2_f64, vld2_f64); + test_vld2_f64_x3(f64, 3, float64x1x3_t, vst3_f64, vld3_f64); + test_vld2_f64_x4(f64, 4, float64x1x4_t, vst4_f64, vld4_f64); + + test_vld2q_f64_x2(f64, 4, float64x2x2_t, vst2q_f64, vld2q_f64); + test_vld3q_f64_x3(f64, 6, float64x2x3_t, vst3q_f64, vld3q_f64); + test_vld4q_f64_x4(f64, 8, float64x2x4_t, vst4q_f64, vld4q_f64); + + test_vld2_s8_x2(i8, 16, int8x8x2_t, vst2_s8, vld2_s8); + test_vld2_s8_x3(i8, 24, int8x8x3_t, vst3_s8, vld3_s8); + test_vld2_s8_x4(i8, 32, int8x8x4_t, vst4_s8, vld4_s8); + + test_vld2q_s8_x2(i8, 32, int8x16x2_t, vst2q_s8, vld2q_s8); + test_vld3q_s8_x3(i8, 48, int8x16x3_t, vst3q_s8, vld3q_s8); + test_vld4q_s8_x4(i8, 64, int8x16x4_t, vst4q_s8, vld4q_s8); + + test_vld2_s16_x2(i16, 8, int16x4x2_t, vst2_s16, vld2_s16); + test_vld2_s16_x3(i16, 12, int16x4x3_t, vst3_s16, vld3_s16); + test_vld2_s16_x4(i16, 16, int16x4x4_t, vst4_s16, vld4_s16); + + test_vld2q_s16_x2(i16, 16, int16x8x2_t, vst2q_s16, vld2q_s16); + test_vld3q_s16_x3(i16, 24, int16x8x3_t, vst3q_s16, vld3q_s16); + test_vld4q_s16_x4(i16, 32, int16x8x4_t, vst4q_s16, vld4q_s16); + + test_vld2_s32_x2(i32, 4, int32x2x2_t, vst2_s32, vld2_s32); + test_vld2_s32_x3(i32, 6, int32x2x3_t, vst3_s32, vld3_s32); + test_vld2_s32_x4(i32, 8, int32x2x4_t, vst4_s32, vld4_s32); + + test_vld2q_s32_x2(i32, 8, int32x4x2_t, vst2q_s32, vld2q_s32); + test_vld3q_s32_x3(i32, 12, int32x4x3_t, vst3q_s32, vld3q_s32); + test_vld4q_s32_x4(i32, 16, int32x4x4_t, vst4q_s32, vld4q_s32); + + test_vld2_s64_x2(i64, 2, int64x1x2_t, vst2_s64, vld2_s64); + test_vld2_s64_x3(i64, 3, int64x1x3_t, vst3_s64, vld3_s64); + test_vld2_s64_x4(i64, 4, int64x1x4_t, vst4_s64, vld4_s64); + + test_vld2q_s64_x2(i64, 4, int64x2x2_t, vst2q_s64, vld2q_s64); + test_vld3q_s64_x3(i64, 6, int64x2x3_t, vst3q_s64, vld3q_s64); + test_vld4q_s64_x4(i64, 8, int64x2x4_t, vst4q_s64, vld4q_s64); + + test_vld2_u8_x2(u8, 16, uint8x8x2_t, vst2_u8, vld2_u8); + test_vld2_u8_x3(u8, 24, uint8x8x3_t, vst3_u8, vld3_u8); + test_vld2_u8_x4(u8, 32, uint8x8x4_t, vst4_u8, vld4_u8); + + test_vld2q_u8_x2(u8, 32, uint8x16x2_t, vst2q_u8, vld2q_u8); + test_vld3q_u8_x3(u8, 48, uint8x16x3_t, vst3q_u8, vld3q_u8); + test_vld4q_u8_x4(u8, 64, uint8x16x4_t, vst4q_u8, vld4q_u8); + + test_vld2_u16_x2(u16, 8, uint16x4x2_t, vst2_u16, vld2_u16); + test_vld2_u16_x3(u16, 12, uint16x4x3_t, vst3_u16, vld3_u16); + test_vld2_u16_x4(u16, 16, uint16x4x4_t, vst4_u16, vld4_u16); + + test_vld2q_u16_x2(u16, 16, uint16x8x2_t, vst2q_u16, vld2q_u16); + test_vld3q_u16_x3(u16, 24, uint16x8x3_t, vst3q_u16, vld3q_u16); + test_vld4q_u16_x4(u16, 32, uint16x8x4_t, vst4q_u16, vld4q_u16); + + test_vld2_u32_x2(u32, 4, uint32x2x2_t, vst2_u32, vld2_u32); + test_vld2_u32_x3(u32, 6, uint32x2x3_t, vst3_u32, vld3_u32); + test_vld2_u32_x4(u32, 8, uint32x2x4_t, vst4_u32, vld4_u32); + + test_vld2q_u32_x2(u32, 8, uint32x4x2_t, vst2q_u32, vld2q_u32); + test_vld3q_u32_x3(u32, 12, uint32x4x3_t, vst3q_u32, vld3q_u32); + test_vld4q_u32_x4(u32, 16, uint32x4x4_t, vst4q_u32, vld4q_u32); + + test_vld2_u64_x2(u64, 2, uint64x1x2_t, vst2_u64, vld2_u64); + test_vld2_u64_x3(u64, 3, uint64x1x3_t, vst3_u64, vld3_u64); + test_vld2_u64_x4(u64, 4, uint64x1x4_t, vst4_u64, vld4_u64); + + test_vld2q_u64_x2(u64, 4, uint64x2x2_t, vst2q_u64, vld2q_u64); + test_vld3q_u64_x3(u64, 6, uint64x2x3_t, vst3q_u64, vld3q_u64); + test_vld4q_u64_x4(u64, 8, uint64x2x4_t, vst4q_u64, vld4q_u64); + + test_vld2_p8_x2(p8, 16, poly8x8x2_t, vst2_p8, vld2_p8); + test_vld2_p8_x3(p8, 24, poly8x8x3_t, vst3_p8, vld3_p8); + test_vld2_p8_x4(p8, 32, poly8x8x4_t, vst4_p8, vld4_p8); + + test_vld2q_p8_x2(p8, 32, poly8x16x2_t, vst2q_p8, vld2q_p8); + test_vld3q_p8_x3(p8, 48, poly8x16x3_t, vst3q_p8, vld3q_p8); + test_vld4q_p8_x4(p8, 64, poly8x16x4_t, vst4q_p8, vld4q_p8); + + test_vld2_p16_x2(p16, 8, poly16x4x2_t, vst2_p16, vld2_p16); + test_vld2_p16_x3(p16, 12, poly16x4x3_t, vst3_p16, vld3_p16); + test_vld2_p16_x4(p16, 16, poly16x4x4_t, vst4_p16, vld4_p16); + + test_vld2q_p16_x2(p16, 16, poly16x8x2_t, vst2q_p16, vld2q_p16); + test_vld3q_p16_x3(p16, 24, poly16x8x3_t, vst3q_p16, vld3q_p16); + test_vld4q_p16_x4(p16, 32, poly16x8x4_t, vst4q_p16, vld4q_p16); + } } #[cfg(test)] diff --git a/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs index 3b67208182cb0..45c83b880e907 100644 --- a/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs @@ -821,7 +821,7 @@ pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -851,7 +851,7 @@ pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1422,7 +1422,7 @@ pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1444,7 +1444,7 @@ pub fn vabs_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1673,7 +1673,7 @@ pub fn vabsh_f16(a: f16) -> f16 { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -1695,7 +1695,7 @@ pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -3879,7 +3879,7 @@ pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -3907,7 +3907,7 @@ pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4529,7 +4529,7 @@ pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4559,7 +4559,7 @@ pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4647,7 +4647,7 @@ pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4677,7 +4677,7 @@ pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4765,7 +4765,7 @@ pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4787,7 +4787,7 @@ pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4851,7 +4851,7 @@ pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4873,7 +4873,7 @@ pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4937,7 +4937,7 @@ pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -4959,7 +4959,7 @@ pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5317,7 +5317,7 @@ pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5339,7 +5339,7 @@ pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5655,7 +5655,7 @@ pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5678,7 +5678,7 @@ pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5701,7 +5701,7 @@ pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -5723,7 +5723,7 @@ pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6039,7 +6039,7 @@ pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6062,7 +6062,7 @@ pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6085,7 +6085,7 @@ pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6107,7 +6107,7 @@ pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6423,7 +6423,7 @@ pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6446,7 +6446,7 @@ pub fn vclez_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6769,7 +6769,7 @@ pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -6791,7 +6791,7 @@ pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -7107,7 +7107,7 @@ pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -7130,7 +7130,7 @@ pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -7812,7 +7812,7 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8041,7 +8041,7 @@ pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8065,7 +8065,7 @@ pub fn vcreate_f16(a: u64) -> float16x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8577,7 +8577,7 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8599,7 +8599,7 @@ pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8621,7 +8621,7 @@ pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8643,7 +8643,7 @@ pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8665,7 +8665,7 @@ pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8688,7 +8688,7 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8795,7 +8795,7 @@ pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8830,7 +8830,7 @@ pub fn vcvt_n_f16_s16(a: int16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8865,7 +8865,7 @@ pub fn vcvtq_n_f16_s16(a: int16x8_t) -> float16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -8900,7 +8900,7 @@ pub fn vcvt_n_f16_u16(a: uint16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9087,7 +9087,7 @@ pub fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9122,7 +9122,7 @@ pub fn vcvt_n_s16_f16(a: float16x4_t) -> int16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9233,7 +9233,7 @@ pub fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9268,7 +9268,7 @@ pub fn vcvt_n_u16_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9378,7 +9378,7 @@ pub fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9400,7 +9400,7 @@ pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9480,7 +9480,7 @@ pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -9502,7 +9502,7 @@ pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -10140,7 +10140,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -10165,7 +10165,7 @@ pub fn vdup_lane_f16(a: float16x4_t) -> float16x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -10719,7 +10719,7 @@ pub fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -10744,7 +10744,7 @@ pub fn vdup_laneq_f16(a: float16x8_t) -> float16x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -12261,7 +12261,7 @@ pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -12640,7 +12640,7 @@ pub fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13228,7 +13228,7 @@ pub fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13250,7 +13250,7 @@ pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13357,7 +13357,7 @@ pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13383,7 +13383,7 @@ pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13494,7 +13494,7 @@ pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -13513,7 +13513,7 @@ pub fn vget_high_f16(a: float16x8_t) -> float16x4_t { #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -15808,21 +15808,13 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f16.p0")] - fn _vld1_f16_x2(a: *const f16) -> float16x4x2_t; - } - _vld1_f16_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"] @@ -15834,21 +15826,13 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f16.p0")] - fn _vld1_f16_x3(a: *const f16) -> float16x4x3_t; - } - _vld1_f16_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"] @@ -15860,21 +15844,13 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f16.p0")] - fn _vld1_f16_x4(a: *const f16) -> float16x4x4_t; - } - _vld1_f16_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"] @@ -15886,21 +15862,13 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v8f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8f16.p0")] - fn _vld1q_f16_x2(a: *const f16) -> float16x8x2_t; - } - _vld1q_f16_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"] @@ -15912,21 +15880,13 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v8f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8f16.p0")] - fn _vld1q_f16_x3(a: *const f16) -> float16x8x3_t; - } - _vld1q_f16_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"] @@ -15938,21 +15898,13 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))] #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v8f16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8f16.p0")] - fn _vld1q_f16_x4(a: *const f16) -> float16x8x4_t; - } - _vld1q_f16_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"] @@ -16156,10 +16108,10 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16170,15 +16122,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0")] - fn _vld1_f32_x2(a: *const f32) -> float32x2x2_t; - } - _vld1_f32_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"] @@ -16187,10 +16131,10 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16201,15 +16145,7 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0")] - fn _vld1_f32_x3(a: *const f32) -> float32x2x3_t; - } - _vld1_f32_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"] @@ -16218,10 +16154,10 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16232,15 +16168,7 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0")] - fn _vld1_f32_x4(a: *const f32) -> float32x2x4_t; - } - _vld1_f32_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"] @@ -16249,10 +16177,10 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16263,15 +16191,7 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0")] - fn _vld1q_f32_x2(a: *const f32) -> float32x4x2_t; - } - _vld1q_f32_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"] @@ -16280,10 +16200,10 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16294,15 +16214,7 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0")] - fn _vld1q_f32_x3(a: *const f32) -> float32x4x3_t; - } - _vld1q_f32_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"] @@ -16311,10 +16223,10 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -16325,15 +16237,7 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0")] - fn _vld1q_f32_x4(a: *const f32) -> float32x4x4_t; - } - _vld1q_f32_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load one single-element structure to one lane of one register"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"] @@ -17000,10 +16904,10 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { #[inline(always)] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17014,7 +16918,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { - transmute(vld1_s64_x2(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"] @@ -17026,7 +16930,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17037,7 +16941,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { - transmute(vld1_s64_x3(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"] @@ -17049,7 +16953,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17060,44 +16964,19 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { - transmute(vld1_s64_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { - transmute(vld1q_s64_x2(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17108,47 +16987,19 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { - let mut ret_val: poly64x2x2_t = transmute(vld1q_s64_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { - transmute(vld1q_s64_x3(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17159,48 +17010,19 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { - let mut ret_val: poly64x2x3_t = transmute(vld1q_s64_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { - transmute(vld1q_s64_x4(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17211,12 +17033,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { - let mut ret_val: poly64x2x4_t = transmute(vld1q_s64_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"] @@ -17329,10 +17146,10 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17343,15 +17160,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0")] - fn _vld1_s8_x2(a: *const i8) -> int8x8x2_t; - } - _vld1_s8_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"] @@ -17360,10 +17169,10 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17374,15 +17183,7 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0")] - fn _vld1_s8_x3(a: *const i8) -> int8x8x3_t; - } - _vld1_s8_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"] @@ -17391,10 +17192,10 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17405,15 +17206,7 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0")] - fn _vld1_s8_x4(a: *const i8) -> int8x8x4_t; - } - _vld1_s8_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"] @@ -17422,10 +17215,10 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17436,15 +17229,7 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0")] - fn _vld1q_s8_x2(a: *const i8) -> int8x16x2_t; - } - _vld1q_s8_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"] @@ -17453,10 +17238,10 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17467,15 +17252,7 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0")] - fn _vld1q_s8_x3(a: *const i8) -> int8x16x3_t; - } - _vld1q_s8_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"] @@ -17484,10 +17261,10 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17498,15 +17275,7 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0")] - fn _vld1q_s8_x4(a: *const i8) -> int8x16x4_t; - } - _vld1q_s8_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"] @@ -17515,10 +17284,10 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17529,15 +17298,7 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0")] - fn _vld1_s16_x2(a: *const i16) -> int16x4x2_t; - } - _vld1_s16_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"] @@ -17546,10 +17307,10 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17560,15 +17321,7 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0")] - fn _vld1_s16_x3(a: *const i16) -> int16x4x3_t; - } - _vld1_s16_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"] @@ -17577,10 +17330,10 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17591,15 +17344,7 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0")] - fn _vld1_s16_x4(a: *const i16) -> int16x4x4_t; - } - _vld1_s16_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"] @@ -17608,10 +17353,10 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17622,15 +17367,7 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0")] - fn _vld1q_s16_x2(a: *const i16) -> int16x8x2_t; - } - _vld1q_s16_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"] @@ -17639,10 +17376,10 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17653,15 +17390,7 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0")] - fn _vld1q_s16_x3(a: *const i16) -> int16x8x3_t; - } - _vld1q_s16_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"] @@ -17670,10 +17399,10 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17684,15 +17413,7 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0")] - fn _vld1q_s16_x4(a: *const i16) -> int16x8x4_t; - } - _vld1q_s16_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"] @@ -17701,10 +17422,10 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17715,15 +17436,7 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0")] - fn _vld1_s32_x2(a: *const i32) -> int32x2x2_t; - } - _vld1_s32_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"] @@ -17732,10 +17445,10 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17746,15 +17459,7 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0")] - fn _vld1_s32_x3(a: *const i32) -> int32x2x3_t; - } - _vld1_s32_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"] @@ -17763,10 +17468,10 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17777,15 +17482,7 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0")] - fn _vld1_s32_x4(a: *const i32) -> int32x2x4_t; - } - _vld1_s32_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"] @@ -17794,10 +17491,10 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17808,15 +17505,7 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0")] - fn _vld1q_s32_x2(a: *const i32) -> int32x4x2_t; - } - _vld1q_s32_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"] @@ -17825,10 +17514,10 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17839,15 +17528,7 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0")] - fn _vld1q_s32_x3(a: *const i32) -> int32x4x3_t; - } - _vld1q_s32_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"] @@ -17856,10 +17537,10 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17870,15 +17551,7 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0")] - fn _vld1q_s32_x4(a: *const i32) -> int32x4x4_t; - } - _vld1q_s32_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"] @@ -17887,10 +17560,10 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17901,15 +17574,7 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0")] - fn _vld1_s64_x2(a: *const i64) -> int64x1x2_t; - } - _vld1_s64_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"] @@ -17918,10 +17583,10 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17932,15 +17597,7 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0")] - fn _vld1_s64_x3(a: *const i64) -> int64x1x3_t; - } - _vld1_s64_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"] @@ -17949,10 +17606,10 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17963,15 +17620,7 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0")] - fn _vld1_s64_x4(a: *const i64) -> int64x1x4_t; - } - _vld1_s64_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"] @@ -17980,10 +17629,10 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -17994,15 +17643,7 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0")] - fn _vld1q_s64_x2(a: *const i64) -> int64x2x2_t; - } - _vld1q_s64_x2(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"] @@ -18011,10 +17652,10 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18025,15 +17666,7 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0")] - fn _vld1q_s64_x3(a: *const i64) -> int64x2x3_t; - } - _vld1q_s64_x3(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"] @@ -18042,10 +17675,10 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { #[inline(always)] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18056,28 +17689,19 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0")] - fn _vld1q_s64_x4(a: *const i64) -> int64x2x4_t; - } - _vld1q_s64_x4(a) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18088,20 +17712,19 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { - transmute(vld1_s8_x2(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18111,24 +17734,20 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { - let mut ret_val: uint8x8x2_t = transmute(vld1_s8_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18138,21 +17757,20 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { - transmute(vld1_s8_x3(transmute(a))) +pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18162,25 +17780,20 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { - let mut ret_val: uint8x8x3_t = transmute(vld1_s8_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18190,21 +17803,20 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { - transmute(vld1_s8_x4(transmute(a))) +pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18214,26 +17826,20 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { - let mut ret_val: uint8x8x4_t = transmute(vld1_s8_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18243,21 +17849,20 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { - transmute(vld1q_s8_x2(transmute(a))) +pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18267,36 +17872,20 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { - let mut ret_val: uint8x16x2_t = transmute(vld1q_s8_x2(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18306,21 +17895,20 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { - transmute(vld1q_s8_x3(transmute(a))) +pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18330,43 +17918,20 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { - let mut ret_val: uint8x16x3_t = transmute(vld1q_s8_x3(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18376,21 +17941,20 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { - transmute(vld1q_s8_x4(transmute(a))) +pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18400,50 +17964,20 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { - let mut ret_val: uint8x16x4_t = transmute(vld1q_s8_x4(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val +pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18453,21 +17987,20 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { - transmute(vld1_s16_x2(transmute(a))) +pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18477,24 +18010,20 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { - let mut ret_val: uint16x4x2_t = transmute(vld1_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18504,21 +18033,20 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { - transmute(vld1_s16_x3(transmute(a))) +pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18528,25 +18056,20 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { - let mut ret_val: uint16x4x3_t = transmute(vld1_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18556,21 +18079,20 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { - transmute(vld1_s16_x4(transmute(a))) +pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18580,26 +18102,20 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { - let mut ret_val: uint16x4x4_t = transmute(vld1_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18609,21 +18125,20 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { - transmute(vld1q_s16_x2(transmute(a))) +pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18633,24 +18148,20 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { - let mut ret_val: uint16x8x2_t = transmute(vld1q_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val +pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -18660,483 +18171,20 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] -pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { - transmute(vld1q_s16_x3(transmute(a))) +pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { - let mut ret_val: uint16x8x3_t = transmute(vld1q_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { - transmute(vld1q_s16_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { - let mut ret_val: uint16x8x4_t = transmute(vld1q_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { - transmute(vld1_s32_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { - let mut ret_val: uint32x2x2_t = transmute(vld1_s32_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { - transmute(vld1_s32_x3(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { - let mut ret_val: uint32x2x3_t = transmute(vld1_s32_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { - transmute(vld1_s32_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { - let mut ret_val: uint32x2x4_t = transmute(vld1_s32_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { - transmute(vld1q_s32_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { - let mut ret_val: uint32x4x2_t = transmute(vld1q_s32_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { - transmute(vld1q_s32_x3(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { - let mut ret_val: uint32x4x3_t = transmute(vld1q_s32_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { - transmute(vld1q_s32_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { - let mut ret_val: uint32x4x4_t = transmute(vld1q_s32_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { - transmute(vld1_s64_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { - transmute(vld1_s64_x3(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { - transmute(vld1_s64_x4(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19147,71 +18195,19 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { - transmute(vld1q_s64_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { - let mut ret_val: uint64x2x2_t = transmute(vld1q_s64_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { - transmute(vld1q_s64_x3(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19222,48 +18218,19 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { - let mut ret_val: uint64x2x3_t = transmute(vld1q_s64_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { - transmute(vld1q_s64_x4(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19274,49 +18241,19 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { - let mut ret_val: uint64x2x4_t = transmute(vld1q_s64_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { - transmute(vld1_s8_x2(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19327,47 +18264,19 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { - let mut ret_val: poly8x8x2_t = transmute(vld1_s8_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { - transmute(vld1_s8_x3(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19378,48 +18287,19 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { - let mut ret_val: poly8x8x3_t = transmute(vld1_s8_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { - transmute(vld1_s8_x4(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19430,49 +18310,19 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { - let mut ret_val: poly8x8x4_t = transmute(vld1_s8_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { - transmute(vld1q_s8_x2(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19483,59 +18333,19 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { - let mut ret_val: poly8x16x2_t = transmute(vld1q_s8_x2(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { - transmute(vld1q_s8_x3(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19546,66 +18356,19 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { - let mut ret_val: poly8x16x3_t = transmute(vld1q_s8_x3(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { - transmute(vld1q_s8_x4(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19616,73 +18379,19 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { - let mut ret_val: poly8x16x4_t = transmute(vld1q_s8_x4(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { - transmute(vld1_s16_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19693,47 +18402,19 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { - let mut ret_val: poly16x4x2_t = transmute(vld1_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { - transmute(vld1_s16_x3(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19744,48 +18425,19 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { - let mut ret_val: poly16x4x3_t = transmute(vld1_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { - transmute(vld1_s16_x4(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19796,49 +18448,19 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { - let mut ret_val: poly16x4x4_t = transmute(vld1_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { - transmute(vld1q_s16_x2(transmute(a))) -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19849,47 +18471,19 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { - let mut ret_val: poly16x8x2_t = transmute(vld1q_s16_x2(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { - transmute(vld1q_s16_x3(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19900,48 +18494,19 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { - let mut ret_val: poly16x8x3_t = transmute(vld1q_s16_x3(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple single-element structures to one, two, three, or four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "little")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { - transmute(vld1q_s16_x4(transmute(a))) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple single-element structures to one, two, three, or four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "big")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld))] #[cfg_attr( all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld1) + assert_instr(ld) )] #[cfg_attr( not(target_arch = "arm"), @@ -19952,12 +18517,7 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { - let mut ret_val: poly16x8x4_t = transmute(vld1q_s16_x4(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val + crate::ptr::read_unaligned(a.cast()) } #[inline(always)] #[rustc_legacy_const_generics(1)] @@ -22195,7 +20755,6 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22215,38 +20774,10 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { transmute(vld2_s8(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { - let mut ret_val: uint8x8x2_t = transmute(vld2_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22266,50 +20797,10 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { transmute(vld2q_s8(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { - let mut ret_val: uint8x16x2_t = transmute(vld2q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22329,38 +20820,10 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { transmute(vld2_s16(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { - let mut ret_val: uint16x4x2_t = transmute(vld2_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22380,38 +20843,10 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { transmute(vld2q_s16(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { - let mut ret_val: uint16x8x2_t = transmute(vld2q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22431,38 +20866,10 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { transmute(vld2_s32(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { - let mut ret_val: uint32x2x2_t = transmute(vld2_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22482,38 +20889,10 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { transmute(vld2q_s32(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { - let mut ret_val: uint32x4x2_t = transmute(vld2q_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22533,38 +20912,10 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { transmute(vld2_s8(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { - let mut ret_val: poly8x8x2_t = transmute(vld2_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22584,50 +20935,10 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { transmute(vld2q_s8(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { - let mut ret_val: poly8x16x2_t = transmute(vld2q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22647,38 +20958,10 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { transmute(vld2_s16(transmute(a))) } #[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { - let mut ret_val: poly16x4x2_t = transmute(vld2_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 2-element structures to two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] @@ -22697,33 +20980,6 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { transmute(vld2q_s16(transmute(a))) } -#[doc = "Load multiple 2-element structures to two registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld2) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { - let mut ret_val: poly16x8x2_t = transmute(vld2q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"] #[doc = "## Safety"] @@ -23780,14 +22036,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4f16.p0" - )] - fn _vld3_f16(ptr: *const f16) -> float16x4x3_t; - } - _vld3_f16(a as _) + crate::core_arch::macros::deinterleaving_load!(f16, 4, 3, a) } #[doc = "Load single 3-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"] @@ -23804,14 +22053,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v8f16.p0" - )] - fn _vld3q_f16(ptr: *const f16) -> float16x8x3_t; - } - _vld3q_f16(a as _) + crate::core_arch::macros::deinterleaving_load!(f16, 8, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] @@ -23823,14 +22065,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2f32.p0" - )] - fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t; - } - _vld3_f32(a as _) + crate::core_arch::macros::deinterleaving_load!(f32, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] @@ -23842,14 +22077,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4f32.p0" - )] - fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t; - } - _vld3q_f32(a as _) + crate::core_arch::macros::deinterleaving_load!(f32, 4, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] @@ -23861,14 +22089,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v8i8.p0" - )] - fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t; - } - _vld3_s8(a as _) + crate::core_arch::macros::deinterleaving_load!(i8, 8, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] @@ -23880,14 +22101,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v16i8.p0" - )] - fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t; - } - _vld3q_s8(a as _) + crate::core_arch::macros::deinterleaving_load!(i8, 16, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] @@ -23899,14 +22113,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4i16.p0" - )] - fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t; - } - _vld3_s16(a as _) + crate::core_arch::macros::deinterleaving_load!(i16, 4, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] @@ -23918,14 +22125,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v8i16.p0" - )] - fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t; - } - _vld3q_s16(a as _) + crate::core_arch::macros::deinterleaving_load!(i16, 8, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] @@ -23937,14 +22137,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v2i32.p0" - )] - fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t; - } - _vld3_s32(a as _) + crate::core_arch::macros::deinterleaving_load!(i32, 2, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] @@ -23956,14 +22149,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ld3))] pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v4i32.p0" - )] - fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t; - } - _vld3q_s32(a as _) + crate::core_arch::macros::deinterleaving_load!(i32, 4, 3, a) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] @@ -24783,14 +22969,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { #[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld3.v1i64.p0" - )] - fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t; - } - _vld3_s64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] @@ -24836,7 +23015,6 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -24856,39 +23034,10 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { transmute(vld3_s8(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { - let mut ret_val: uint8x8x3_t = transmute(vld3_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -24908,57 +23057,10 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { transmute(vld3q_s8(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { - let mut ret_val: uint8x16x3_t = transmute(vld3q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -24978,39 +23080,10 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { transmute(vld3_s16(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { - let mut ret_val: uint16x4x3_t = transmute(vld3_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25030,39 +23103,10 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { transmute(vld3q_s16(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { - let mut ret_val: uint16x8x3_t = transmute(vld3q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25082,39 +23126,10 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { transmute(vld3_s32(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { - let mut ret_val: uint32x2x3_t = transmute(vld3_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25134,39 +23149,10 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { transmute(vld3q_s32(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { - let mut ret_val: uint32x4x3_t = transmute(vld3q_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25186,39 +23172,10 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { transmute(vld3_s8(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { - let mut ret_val: poly8x8x3_t = transmute(vld3_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25238,57 +23195,10 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { transmute(vld3q_s8(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { - let mut ret_val: poly8x16x3_t = transmute(vld3q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25308,39 +23218,10 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { transmute(vld3_s16(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { - let mut ret_val: poly16x4x3_t = transmute(vld3_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] @@ -25360,34 +23241,6 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { transmute(vld3q_s16(transmute(a))) } #[doc = "Load multiple 3-element structures to three registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld3) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { - let mut ret_val: poly16x8x3_t = transmute(vld3q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 3-element structures to three registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] @@ -26483,14 +24336,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4f16.p0" - )] - fn _vld4_f16(ptr: *const f16) -> float16x4x4_t; - } - _vld4_f16(a as _) + crate::core_arch::macros::deinterleaving_load!(f16, 4, 4, a) } #[doc = "Load single 4-element structure and replicate to all lanes of two registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"] @@ -26506,14 +24352,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t { #[unstable(feature = "stdarch_neon_f16", issue = "136306")] #[cfg(not(target_arch = "arm64ec"))] pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v8f16.p0" - )] - fn _vld4q_f16(ptr: *const f16) -> float16x8x4_t; - } - _vld4q_f16(a as _) + crate::core_arch::macros::deinterleaving_load!(f16, 8, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] @@ -26525,14 +24364,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2f32.p0" - )] - fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t; - } - _vld4_f32(a as _) + crate::core_arch::macros::deinterleaving_load!(f32, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] @@ -26544,14 +24376,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4f32.p0" - )] - fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t; - } - _vld4q_f32(a as _) + crate::core_arch::macros::deinterleaving_load!(f32, 4, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] @@ -26563,14 +24388,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v8i8.p0" - )] - fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t; - } - _vld4_s8(a as _) + crate::core_arch::macros::deinterleaving_load!(i8, 8, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] @@ -26582,14 +24400,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v16i8.p0" - )] - fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t; - } - _vld4q_s8(a as _) + crate::core_arch::macros::deinterleaving_load!(i8, 16, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] @@ -26601,14 +24412,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4i16.p0" - )] - fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t; - } - _vld4_s16(a as _) + crate::core_arch::macros::deinterleaving_load!(i16, 4, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] @@ -26620,14 +24424,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v8i16.p0" - )] - fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t; - } - _vld4q_s16(a as _) + crate::core_arch::macros::deinterleaving_load!(i16, 8, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] @@ -26639,14 +24436,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v2i32.p0" - )] - fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t; - } - _vld4_s32(a as _) + crate::core_arch::macros::deinterleaving_load!(i32, 2, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] @@ -26658,14 +24448,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(ld4))] pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v4i32.p0" - )] - fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t; - } - _vld4q_s32(a as _) + crate::core_arch::macros::deinterleaving_load!(i32, 4, 4, a) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] @@ -27526,14 +25309,7 @@ pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { #[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(nop))] pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.ld4.v1i64.p0" - )] - fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t; - } - _vld4_s64(a as _) + crate::ptr::read_unaligned(a.cast()) } #[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] @@ -27579,7 +25355,6 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27599,40 +25374,10 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { transmute(vld4_s8(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { - let mut ret_val: uint8x8x4_t = transmute(vld4_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27652,64 +25397,10 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { transmute(vld4q_s8(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { - let mut ret_val: uint8x16x4_t = transmute(vld4q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27729,40 +25420,10 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { transmute(vld4_s16(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { - let mut ret_val: uint16x4x4_t = transmute(vld4_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27782,40 +25443,10 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { transmute(vld4q_s16(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { - let mut ret_val: uint16x8x4_t = transmute(vld4q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27835,40 +25466,10 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { transmute(vld4_s32(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { - let mut ret_val: uint32x2x4_t = transmute(vld4_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27888,40 +25489,10 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { transmute(vld4q_s32(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { - let mut ret_val: uint32x4x4_t = transmute(vld4q_s32(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27941,40 +25512,10 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { transmute(vld4_s8(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { - let mut ret_val: poly8x8x4_t = transmute(vld4_s8(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -27994,64 +25535,10 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { transmute(vld4q_s8(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { - let mut ret_val: poly8x16x4_t = transmute(vld4q_s8(transmute(a))); - ret_val.0 = unsafe { - simd_shuffle!( - ret_val.0, - ret_val.0, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.1 = unsafe { - simd_shuffle!( - ret_val.1, - ret_val.1, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.2 = unsafe { - simd_shuffle!( - ret_val.2, - ret_val.2, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val.3 = unsafe { - simd_shuffle!( - ret_val.3, - ret_val.3, - [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0] - ) - }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -28071,40 +25558,10 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { transmute(vld4_s16(transmute(a))) } #[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { - let mut ret_val: poly16x4x4_t = transmute(vld4_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [3, 2, 1, 0]) }; - ret_val -} -#[doc = "Load multiple 4-element structures to four registers"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] #[doc = "## Safety"] #[doc = " * Neon intrinsic unsafe"] #[inline(always)] -#[cfg(target_endian = "little")] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] @@ -28123,35 +25580,6 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { transmute(vld4q_s16(transmute(a))) } -#[doc = "Load multiple 4-element structures to four registers"] -#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] -#[doc = "## Safety"] -#[doc = " * Neon intrinsic unsafe"] -#[inline(always)] -#[cfg(target_endian = "big")] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr( - all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), - assert_instr(ld4) -)] -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { - let mut ret_val: poly16x8x4_t = transmute(vld4q_s16(transmute(a))); - ret_val.0 = unsafe { simd_shuffle!(ret_val.0, ret_val.0, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.1 = unsafe { simd_shuffle!(ret_val.1, ret_val.1, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.2 = unsafe { simd_shuffle!(ret_val.2, ret_val.2, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) }; - ret_val -} #[doc = "Store SIMD&FP register (immediate offset)"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"] #[doc = "## Safety"] @@ -28187,7 +25615,7 @@ pub unsafe fn vldrq_p128(a: *const p128) -> p128 { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -28217,7 +25645,7 @@ pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -28593,7 +26021,7 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -28615,7 +26043,7 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -28679,7 +26107,7 @@ pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -28709,7 +26137,7 @@ pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -29085,7 +26513,7 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -29107,7 +26535,7 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33043,7 +30471,7 @@ pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33065,7 +30493,7 @@ pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33130,7 +30558,7 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -33159,7 +30587,7 @@ pub fn vmul_lane_f16(a: float16x4_t, v: float16x4_t) -> float16 #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -34656,15 +32084,7 @@ pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smull.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i32")] - fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t; - } - unsafe { _vmull_s16(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"] @@ -34685,15 +32105,7 @@ pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smull.v2i64" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i64")] - fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t; - } - unsafe { _vmull_s32(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Signed multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"] @@ -34714,15 +32126,7 @@ pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.smull.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i16")] - fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t; - } - unsafe { _vmull_s8(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"] @@ -34743,15 +32147,7 @@ pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umull.v8i16" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i16")] - fn _vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t; - } - unsafe { _vmull_u8(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"] @@ -34772,15 +32168,7 @@ pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umull.v4i32" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i32")] - fn _vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t; - } - unsafe { _vmull_u16(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Unsigned multiply long"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"] @@ -34801,15 +32189,7 @@ pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") )] pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - unsafe extern "unadjusted" { - #[cfg_attr( - any(target_arch = "aarch64", target_arch = "arm64ec"), - link_name = "llvm.aarch64.neon.umull.v2i64" - )] - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i64")] - fn _vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t; - } - unsafe { _vmull_u32(a, b) } + unsafe { simd_mul(simd_cast(a), simd_cast(b)) } } #[doc = "Vector bitwise not."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"] @@ -35131,7 +32511,7 @@ pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -35153,7 +32533,7 @@ pub fn vneg_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -36391,7 +33771,7 @@ pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42473,7 +39853,7 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42503,7 +39883,7 @@ pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42649,7 +40029,7 @@ pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42679,7 +40059,7 @@ pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42768,7 +40148,7 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42791,7 +40171,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42818,7 +40198,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42841,7 +40221,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42868,7 +40248,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42891,7 +40271,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42918,7 +40298,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42941,7 +40321,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42968,7 +40348,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -42991,7 +40371,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43015,7 +40395,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43038,7 +40418,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43065,7 +40445,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43088,7 +40468,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43115,7 +40495,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43138,7 +40518,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43165,7 +40545,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43188,7 +40568,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43212,7 +40592,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43235,7 +40615,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43262,7 +40642,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43285,7 +40665,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43312,7 +40692,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43335,7 +40715,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43362,7 +40742,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43385,7 +40765,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43416,7 +40796,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43439,7 +40819,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43466,7 +40846,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43489,7 +40869,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43516,7 +40896,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43539,7 +40919,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43566,7 +40946,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43589,7 +40969,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43620,7 +41000,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43643,7 +41023,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43670,7 +41050,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43693,7 +41073,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43720,7 +41100,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43743,7 +41123,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43770,7 +41150,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43793,7 +41173,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43824,7 +41204,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43847,7 +41227,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43874,7 +41254,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43897,7 +41277,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43924,7 +41304,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43947,7 +41327,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43974,7 +41354,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -43997,7 +41377,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44024,7 +41404,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44047,7 +41427,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44075,7 +41455,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44098,7 +41478,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44125,7 +41505,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44148,7 +41528,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44175,7 +41555,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44198,7 +41578,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44225,7 +41605,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44248,7 +41628,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44275,7 +41655,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44298,7 +41678,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44324,7 +41704,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44347,7 +41727,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44374,7 +41754,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44397,7 +41777,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44424,7 +41804,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44447,7 +41827,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44475,7 +41855,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44498,7 +41878,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44525,7 +41905,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44548,7 +41928,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44575,7 +41955,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44598,7 +41978,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44625,7 +42005,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44648,7 +42028,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44675,7 +42055,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44698,7 +42078,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44724,7 +42104,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44747,7 +42127,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44774,7 +42154,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44797,7 +42177,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44824,7 +42204,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44847,7 +42227,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44875,7 +42255,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44898,7 +42278,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44925,7 +42305,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44948,7 +42328,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44975,7 +42355,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -44998,7 +42378,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45024,7 +42404,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45047,7 +42427,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45071,7 +42451,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45094,7 +42474,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45118,7 +42498,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45141,7 +42521,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45168,7 +42548,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45191,7 +42571,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45217,7 +42597,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -45240,7 +42620,7 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -59244,7 +56624,7 @@ pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -59266,7 +56646,7 @@ pub fn vrev64_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -59636,7 +57016,7 @@ pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -59665,7 +57045,7 @@ pub fn vrndn_f16(a: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -60756,7 +58136,7 @@ pub fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -60786,7 +58166,7 @@ pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -60932,7 +58312,7 @@ pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -60962,7 +58342,7 @@ pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { )] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -72516,7 +69896,7 @@ pub unsafe fn vstrq_p128(a: *mut p128, b: p128) { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -72538,7 +69918,7 @@ pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -74519,7 +71899,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -74549,7 +71929,7 @@ pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -75832,7 +73212,7 @@ pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -75862,7 +73242,7 @@ pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -76438,7 +73818,7 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -76468,7 +73848,7 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t { #[target_feature(enable = "neon,fp16")] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", diff --git a/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs b/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs index 1ca8ce2b13954..8a4a6e9228221 100644 --- a/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs @@ -104,7 +104,7 @@ types! { } types! { - #![cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION"))] + #![cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0"))] #![cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] /// Arm-specific 64-bit wide vector of four packed `f16`. @@ -750,7 +750,7 @@ pub struct uint32x4x4_t( #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -763,7 +763,7 @@ pub struct float16x4x2_t(pub float16x4_t, pub float16x4_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -776,7 +776,7 @@ pub struct float16x4x3_t(pub float16x4_t, pub float16x4_t, pub float16x4_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -794,7 +794,7 @@ pub struct float16x4x4_t( #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -807,7 +807,7 @@ pub struct float16x8x2_t(pub float16x8_t, pub float16x8_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", @@ -820,7 +820,7 @@ pub struct float16x8x3_t(pub float16x8_t, pub float16x8_t, pub float16x8_t); #[derive(Copy, Clone, Debug)] #[cfg_attr( not(target_arch = "arm"), - stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION") + stable(feature = "stdarch_neon_fp16", since = "1.94.0") )] #[cfg_attr( target_arch = "arm", diff --git a/stdarch/crates/core_arch/src/core_arch_docs.md b/stdarch/crates/core_arch/src/core_arch_docs.md index 7075945754975..9b52fb2af1598 100644 --- a/stdarch/crates/core_arch/src/core_arch_docs.md +++ b/stdarch/crates/core_arch/src/core_arch_docs.md @@ -186,6 +186,7 @@ others at: * [`arm`] * [`aarch64`] * [`amdgpu`] +* [`hexagon`] * [`riscv32`] * [`riscv64`] * [`mips`] @@ -203,6 +204,7 @@ others at: [`arm`]: ../../core/arch/arm/index.html [`aarch64`]: ../../core/arch/aarch64/index.html [`amdgpu`]: ../../core/arch/amdgpu/index.html +[`hexagon`]: ../../core/arch/hexagon/index.html [`riscv32`]: ../../core/arch/riscv32/index.html [`riscv64`]: ../../core/arch/riscv64/index.html [`mips`]: ../../core/arch/mips/index.html diff --git a/stdarch/crates/core_arch/src/hexagon/mod.rs b/stdarch/crates/core_arch/src/hexagon/mod.rs new file mode 100644 index 0000000000000..c370f3da15dfb --- /dev/null +++ b/stdarch/crates/core_arch/src/hexagon/mod.rs @@ -0,0 +1,29 @@ +//! Hexagon architecture intrinsics +//! +//! This module contains intrinsics for the Qualcomm Hexagon DSP architecture, +//! including the Hexagon Vector Extensions (HVX). +//! +//! HVX is a wide SIMD architecture designed for high-performance signal processing, +//! machine learning, and image processing workloads. +//! +//! ## Vector Length Modes +//! +//! HVX supports two vector length modes: +//! - 64-byte mode (512-bit vectors): Use the [`v64`] module +//! - 128-byte mode (1024-bit vectors): Use the [`v128`] module +//! +//! Both modules are available unconditionally, but require the appropriate +//! target features to actually use the intrinsics: +//! - For 64-byte mode: `-C target-feature=+hvx-length64b` +//! - For 128-byte mode: `-C target-feature=+hvx-length128b` +//! +//! Note that HVX v66 and later default to 128-byte mode, while earlier versions +//! (v60-v65) default to 64-byte mode. + +/// HVX intrinsics for 64-byte vector mode (512-bit vectors) +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub mod v64; + +/// HVX intrinsics for 128-byte vector mode (1024-bit vectors) +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub mod v128; diff --git a/stdarch/crates/core_arch/src/hexagon/v128.rs b/stdarch/crates/core_arch/src/hexagon/v128.rs new file mode 100644 index 0000000000000..ef7ff4205c71d --- /dev/null +++ b/stdarch/crates/core_arch/src/hexagon/v128.rs @@ -0,0 +1,7489 @@ +//! Hexagon HVX 128-byte vector mode intrinsics +//! +//! This module provides intrinsics for the Hexagon Vector Extensions (HVX) +//! in 128-byte vector mode (1024-bit vectors). +//! +//! HVX is a wide vector extension designed for high-performance signal processing. +//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61) +//! +//! ## Vector Types +//! +//! In 128-byte mode: +//! - `HvxVector` is 1024 bits (128 bytes) containing 32 x 32-bit values +//! - `HvxVectorPair` is 2048 bits (256 bytes) +//! - `HvxVectorPred` is 1024 bits (128 bytes) for predicate operations +//! +//! To use this module, compile with `-C target-feature=+hvx-length128b`. +//! +//! ## Architecture Versions +//! +//! Different intrinsics require different HVX architecture versions. Use the +//! appropriate target feature to enable the required version: +//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations) +//! - HVX v62: `-C target-feature=+hvxv62` +//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support) +//! - HVX v66: `-C target-feature=+hvxv66` +//! - HVX v68: `-C target-feature=+hvxv68` +//! - HVX v69: `-C target-feature=+hvxv69` +//! - HVX v73: `-C target-feature=+hvxv73` +//! - HVX v79: `-C target-feature=+hvxv79` +//! +//! Each version includes all features from previous versions. + +#![allow(non_camel_case_types)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use crate::intrinsics::simd::{simd_add, simd_and, simd_or, simd_sub, simd_xor}; + +// HVX type definitions for 128-byte vector mode +types! { + #![unstable(feature = "stdarch_hexagon", issue = "151523")] + + /// HVX vector type (1024 bits / 128 bytes) + /// + /// This type represents a single HVX vector register containing 32 x 32-bit values. + pub struct HvxVector(32 x i32); + + /// HVX vector pair type (2048 bits / 256 bytes) + /// + /// This type represents a pair of HVX vector registers, often used for + /// operations that produce double-width results. + pub struct HvxVectorPair(64 x i32); + + /// HVX vector predicate type (1024 bits / 128 bytes) + /// + /// This type represents a predicate vector used for conditional operations. + /// Each bit corresponds to a lane in the vector. + pub struct HvxVectorPred(32 x i32); +} + +// LLVM intrinsic declarations for 128-byte vector mode +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.hexagon.V6.extractw.128B"] + fn extractw(_: HvxVector, _: i32) -> i32; + #[link_name = "llvm.hexagon.V6.get.qfext.128B"] + fn get_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.hi.128B"] + fn hi(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lo.128B"] + fn lo(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatb.128B"] + fn lvsplatb(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplath.128B"] + fn lvsplath(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatw.128B"] + fn lvsplatw(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and.128B"] + fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and.n.128B"] + fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.not.128B"] + fn pred_not(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or.128B"] + fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or.n.128B"] + fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2.128B"] + fn pred_scalar2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2v2.128B"] + fn pred_scalar2v2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.xor.128B"] + fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.set.qfext.128B"] + fn set_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqh.128B"] + fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqw.128B"] + fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10.128B"] + fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx.128B"] + fn v6mpyhubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10.128B"] + fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx.128B"] + fn v6mpyvubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai.128B"] + fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai.128B"] + fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai.128B"] + fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai.128B"] + fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vabs.f8.128B"] + fn vabs_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.hf.128B"] + fn vabs_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.sf.128B"] + fn vabs_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb.128B"] + fn vabsb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb.sat.128B"] + fn vabsb_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffh.128B"] + fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffub.128B"] + fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffuh.128B"] + fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffw.128B"] + fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh.128B"] + fn vabsh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh.sat.128B"] + fn vabsh_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw.128B"] + fn vabsw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw.sat.128B"] + fn vabsw_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf.128B"] + fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf.hf.128B"] + fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16.128B"] + fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16.mix.128B"] + fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32.128B"] + fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32.mix.128B"] + fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf.128B"] + fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf.hf.128B"] + fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadd.sf.sf.128B"] + fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb.128B"] + fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb.dv.128B"] + fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddbnq.128B"] + fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbq.128B"] + fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat.128B"] + fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat.dv.128B"] + fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddcarrysat.128B"] + fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbh.128B"] + fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbw.128B"] + fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh.128B"] + fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh.dv.128B"] + fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhnq.128B"] + fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhq.128B"] + fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat.128B"] + fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat.dv.128B"] + fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw.128B"] + fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw.acc.128B"] + fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh.128B"] + fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh.acc.128B"] + fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubsat.128B"] + fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddubsat.dv.128B"] + fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddububb.sat.128B"] + fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat.128B"] + fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat.dv.128B"] + fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw.128B"] + fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw.acc.128B"] + fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduwsat.128B"] + fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduwsat.dv.128B"] + fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddw.128B"] + fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddw.dv.128B"] + fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddwnq.128B"] + fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwq.128B"] + fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat.128B"] + fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat.dv.128B"] + fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.valignb.128B"] + fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.valignbi.128B"] + fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vand.128B"] + fn vand(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt.128B"] + fn vandnqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt.acc.128B"] + fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt.128B"] + fn vandqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt.acc.128B"] + fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvnqv.128B"] + fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvqv.128B"] + fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt.128B"] + fn vandvrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt.acc.128B"] + fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh.128B"] + fn vaslh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh.acc.128B"] + fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslhv.128B"] + fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw.128B"] + fn vaslw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw.acc.128B"] + fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslwv.128B"] + fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasr.into.128B"] + fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vasrh.128B"] + fn vasrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrh.acc.128B"] + fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbrndsat.128B"] + fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbsat.128B"] + fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubrndsat.128B"] + fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubsat.128B"] + fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhv.128B"] + fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubrndsat.128B"] + fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubsat.128B"] + fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhrndsat.128B"] + fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhsat.128B"] + fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat.128B"] + fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubsat.128B"] + fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat.128B"] + fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhsat.128B"] + fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw.128B"] + fn vasrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw.acc.128B"] + fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwh.128B"] + fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhrndsat.128B"] + fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhsat.128B"] + fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhrndsat.128B"] + fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhsat.128B"] + fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwv.128B"] + fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign.128B"] + fn vassign(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign.fp.128B"] + fn vassign_fp(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassignp.128B"] + fn vassignp(_: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vavgb.128B"] + fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgbrnd.128B"] + fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgh.128B"] + fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavghrnd.128B"] + fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgub.128B"] + fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgubrnd.128B"] + fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguh.128B"] + fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguhrnd.128B"] + fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguw.128B"] + fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguwrnd.128B"] + fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgw.128B"] + fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgwrnd.128B"] + fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0h.128B"] + fn vcl0h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0w.128B"] + fn vcl0w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcombine.128B"] + fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vconv.h.hf.128B"] + fn vconv_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.h.128B"] + fn vconv_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf16.128B"] + fn vconv_hf_qf16(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf32.128B"] + fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.qf32.128B"] + fn vconv_sf_qf32(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.w.128B"] + fn vconv_sf_w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.w.sf.128B"] + fn vconv_w_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.b.128B"] + fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub.128B"] + fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.b.hf.128B"] + fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.h.hf.128B"] + fn vcvt_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.b.128B"] + fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.f8.128B"] + fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.h.128B"] + fn vcvt_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.sf.128B"] + fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.ub.128B"] + fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.uh.128B"] + fn vcvt_hf_uh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.sf.hf.128B"] + fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.ub.hf.128B"] + fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.uh.hf.128B"] + fn vcvt_uh_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vd0.128B"] + fn vd0() -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdd0.128B"] + fn vdd0() -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdealb.128B"] + fn vdealb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealb4w.128B"] + fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealh.128B"] + fn vdealh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealvdd.128B"] + fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdelta.128B"] + fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.128B"] + fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc.128B"] + fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.128B"] + fn vdmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.acc.128B"] + fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv.128B"] + fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc.128B"] + fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb.128B"] + fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.acc.128B"] + fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.128B"] + fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc.128B"] + fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhisat.128B"] + fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc.128B"] + fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat.128B"] + fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc.128B"] + fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.128B"] + fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc.128B"] + fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat.128B"] + fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc.128B"] + fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat.128B"] + fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc.128B"] + fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdsaduh.128B"] + fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdsaduh.acc.128B"] + fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.veqb.128B"] + fn veqb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.and.128B"] + fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.or.128B"] + fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.xor.128B"] + fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.128B"] + fn veqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.and.128B"] + fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.or.128B"] + fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.xor.128B"] + fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.128B"] + fn veqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.and.128B"] + fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.or.128B"] + fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.xor.128B"] + fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.f8.128B"] + fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.hf.128B"] + fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.sf.128B"] + fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.f8.128B"] + fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.hf.128B"] + fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.sf.128B"] + fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.f8.128B"] + fn vfneg_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.hf.128B"] + fn vfneg_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.sf.128B"] + fn vfneg_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgathermh.128B"] + fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhq.128B"] + fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhw.128B"] + fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhwq.128B"] + fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermw.128B"] + fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermwq.128B"] + fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgtb.128B"] + fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.and.128B"] + fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.or.128B"] + fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.xor.128B"] + fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.128B"] + fn vgth(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.and.128B"] + fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.or.128B"] + fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.xor.128B"] + fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.128B"] + fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.and.128B"] + fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.or.128B"] + fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.xor.128B"] + fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.128B"] + fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.and.128B"] + fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.or.128B"] + fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.xor.128B"] + fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.128B"] + fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.and.128B"] + fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.or.128B"] + fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.xor.128B"] + fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.128B"] + fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.and.128B"] + fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.or.128B"] + fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.xor.128B"] + fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.128B"] + fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.and.128B"] + fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.or.128B"] + fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.xor.128B"] + fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.128B"] + fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.and.128B"] + fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.or.128B"] + fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.xor.128B"] + fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vinsertwr.128B"] + fn vinsertwr(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignb.128B"] + fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignbi.128B"] + fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrb.128B"] + fn vlsrb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrh.128B"] + fn vlsrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrhv.128B"] + fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrw.128B"] + fn vlsrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrwv.128B"] + fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.128B"] + fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.nm.128B"] + fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracc.128B"] + fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracci.128B"] + fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvbi.128B"] + fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvwh.128B"] + fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.nm.128B"] + fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracc.128B"] + fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracci.128B"] + fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwhi.128B"] + fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmax.hf.128B"] + fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmax.sf.128B"] + fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxb.128B"] + fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxh.128B"] + fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxub.128B"] + fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxuh.128B"] + fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxw.128B"] + fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.hf.128B"] + fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.sf.128B"] + fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminb.128B"] + fn vminb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminh.128B"] + fn vminh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminub.128B"] + fn vminub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminuh.128B"] + fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminw.128B"] + fn vminw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpabus.128B"] + fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabus.acc.128B"] + fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabusv.128B"] + fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu.128B"] + fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu.acc.128B"] + fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuuv.128B"] + fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb.128B"] + fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb.acc.128B"] + fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb.128B"] + fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb.acc.128B"] + fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.128B"] + fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc.128B"] + fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.128B"] + fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf.128B"] + fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf.128B"] + fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.128B"] + fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf.128B"] + fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf.128B"] + fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16.128B"] + fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf.128B"] + fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.128B"] + fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc.128B"] + fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.sf.128B"] + fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpybus.128B"] + fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybus.acc.128B"] + fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv.128B"] + fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv.acc.128B"] + fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv.128B"] + fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv.acc.128B"] + fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyewuh.128B"] + fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyewuh.64.128B"] + fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh.128B"] + fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh.acc.128B"] + fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsat.acc.128B"] + fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsrs.128B"] + fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhss.128B"] + fn vmpyhss(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhus.128B"] + fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhus.acc.128B"] + fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv.128B"] + fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv.acc.128B"] + fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhvsrs.128B"] + fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyieoh.128B"] + fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewh.acc.128B"] + fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh.128B"] + fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc.128B"] + fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih.128B"] + fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih.acc.128B"] + fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb.128B"] + fn vmpyihb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb.acc.128B"] + fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiowh.128B"] + fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb.128B"] + fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb.acc.128B"] + fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh.128B"] + fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh.acc.128B"] + fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub.128B"] + fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub.acc.128B"] + fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.128B"] + fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc.128B"] + fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.128B"] + fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc.128B"] + fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.sacc.128B"] + fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyub.128B"] + fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyub.acc.128B"] + fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv.128B"] + fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv.acc.128B"] + fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh.128B"] + fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh.acc.128B"] + fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhe.128B"] + fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhe.acc.128B"] + fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhv.128B"] + fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhv.acc.128B"] + fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhvs.128B"] + fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmux.128B"] + fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgb.128B"] + fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgh.128B"] + fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgub.128B"] + fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgw.128B"] + fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamth.128B"] + fn vnormamth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamtw.128B"] + fn vnormamtw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnot.128B"] + fn vnot(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vor.128B"] + fn vor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeb.128B"] + fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeh.128B"] + fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhb.sat.128B"] + fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhub.sat.128B"] + fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackob.128B"] + fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackoh.128B"] + fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwh.sat.128B"] + fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwuh.sat.128B"] + fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpopcounth.128B"] + fn vpopcounth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqb.128B"] + fn vprefixqb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqh.128B"] + fn vprefixqh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqw.128B"] + fn vprefixqw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrdelta.128B"] + fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus.128B"] + fn vrmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus.acc.128B"] + fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusi.128B"] + fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusi.acc.128B"] + fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusv.128B"] + fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusv.acc.128B"] + fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv.128B"] + fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv.acc.128B"] + fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub.128B"] + fn vrmpyub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub.acc.128B"] + fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubi.128B"] + fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubi.acc.128B"] + fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubv.128B"] + fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubv.acc.128B"] + fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vror.128B"] + fn vror(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrotr.128B"] + fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhb.128B"] + fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhub.128B"] + fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduhub.128B"] + fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduwuh.128B"] + fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwh.128B"] + fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwuh.128B"] + fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrsadubi.128B"] + fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrsadubi.acc.128B"] + fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsatdw.128B"] + fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsathub.128B"] + fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatuwuh.128B"] + fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatwh.128B"] + fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsb.128B"] + fn vsb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vscattermh.128B"] + fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermh.add.128B"] + fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhq.128B"] + fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw.128B"] + fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw.add.128B"] + fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhwq.128B"] + fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw.128B"] + fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw.add.128B"] + fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermwq.128B"] + fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vsh.128B"] + fn vsh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufeh.128B"] + fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffb.128B"] + fn vshuffb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffeb.128B"] + fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffh.128B"] + fn vshuffh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffob.128B"] + fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffvdd.128B"] + fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeb.128B"] + fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeh.128B"] + fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoh.128B"] + fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf.128B"] + fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf.hf.128B"] + fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16.128B"] + fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16.mix.128B"] + fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32.128B"] + fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32.mix.128B"] + fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf.128B"] + fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf.hf.128B"] + fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsub.sf.sf.128B"] + fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb.128B"] + fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb.dv.128B"] + fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubbnq.128B"] + fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbq.128B"] + fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat.128B"] + fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat.dv.128B"] + fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubh.128B"] + fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubh.dv.128B"] + fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhnq.128B"] + fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhq.128B"] + fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat.128B"] + fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat.dv.128B"] + fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhw.128B"] + fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububh.128B"] + fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububsat.128B"] + fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsububsat.dv.128B"] + fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubububb.sat.128B"] + fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat.128B"] + fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat.dv.128B"] + fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuhw.128B"] + fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuwsat.128B"] + fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuwsat.dv.128B"] + fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubw.128B"] + fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubw.dv.128B"] + fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubwnq.128B"] + fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwq.128B"] + fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat.128B"] + fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat.dv.128B"] + fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vswap.128B"] + fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb.128B"] + fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb.acc.128B"] + fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus.128B"] + fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus.acc.128B"] + fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb.128B"] + fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb.acc.128B"] + fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackb.128B"] + fn vunpackb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackh.128B"] + fn vunpackh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackob.128B"] + fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackoh.128B"] + fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackub.128B"] + fn vunpackub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackuh.128B"] + fn vunpackuh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vxor.128B"] + fn vxor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vzb.128B"] + fn vzb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vzh.128B"] + fn vzh(_: HvxVector) -> HvxVectorPair; +} + +/// `Rd32=vextract(Vu32,Rs32)` +/// +/// Instruction Type: LD +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(extractw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { + extractw(vu, rs) +} + +/// `Vd32=hi(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(hi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { + hi(vss) +} + +/// `Vd32=lo(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lo))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { + lo(vss) +} + +/// `Vd32=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lvsplatw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { + lvsplatw(rt) +} + +/// `Vd32.uh=vabsdiff(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffh(vu, vv) +} + +/// `Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffub(vu, vv) +} + +/// `Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffuh(vu, vv) +} + +/// `Vd32.uw=vabsdiff(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffw(vu, vv) +} + +/// `Vd32.h=vabs(Vu32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { + vabsh(vu) +} + +/// `Vd32.h=vabs(Vu32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { + vabsh_sat(vu) +} + +/// `Vd32.w=vabs(Vu32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { + vabsw(vu) +} + +/// `Vd32.w=vabs(Vu32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { + vabsw_sat(vu) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddb(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddb_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddh(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddh_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddhsat(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddhw(vu, vv) +} + +/// `Vdd32.h=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddubh(vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddubsat(vu, vv) +} + +/// `Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddubsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduhsat(vu, vv) +} + +/// `Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadduhw(vu, vv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_add(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddw_dv(vuu, vvv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddwsat(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddwsat_dv(vuu, vvv) +} + +/// `Vd32=valign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + valignb(vu, vv, rt) +} + +/// `Vd32=valign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + valignbi(vu, vv, iu3) +} + +/// `Vd32=vand(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vand))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_and(vu, vv) +} + +/// `Vd32.h=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { + vaslh(vu, rt) +} + +/// `Vd32.h=vasl(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslhv(vu, vv) +} + +/// `Vd32.w=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { + vaslw(vu, rt) +} + +/// `Vx32.w+=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslw_acc(vx, vu, rt) +} + +/// `Vd32.w=vasl(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslwv(vu, vv) +} + +/// `Vd32.h=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { + vasrh(vu, rt) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhbrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrhv(vu, vv) +} + +/// `Vd32.w=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { + vasrw(vu, rt) +} + +/// `Vx32.w+=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrw_acc(vx, vu, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwh(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhrndsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhsat(vu, vv, rt) +} + +/// `Vd32.w=vasr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrwv(vu, vv) +} + +/// `Vd32=Vu32` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassign))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { + vassign(vu) +} + +/// `Vdd32=Vuu32` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassignp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { + vassignp(vuu) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgh(vu, vv) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavghrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavghrnd(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgub(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgubrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgubrnd(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguh(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguhrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguhrnd(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgw(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgwrnd(vu, vv) +} + +/// `Vd32.uh=vcl0(Vu32.uh)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { + vcl0h(vu) +} + +/// `Vd32.uw=vcl0(Vu32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { + vcl0w(vu) +} + +/// `Vdd32=vcombine(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcombine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vcombine(vu, vv) +} + +/// `Vd32=#0` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vzero() -> HvxVector { + vd0() +} + +/// `Vd32.b=vdeal(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { + vdealb(vu) +} + +/// `Vd32.b=vdeale(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb4w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdealb4w(vu, vv) +} + +/// `Vd32.h=vdeal(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { + vdealh(vu) +} + +/// `Vdd32=vdeal(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vdealvdd(vu, vv, rt) +} + +/// `Vd32=vdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdelta(vu, vv) +} + +/// `Vd32.h=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus(vu, rt) +} + +/// `Vx32.h+=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpybus_dv(vuu, rt) +} + +/// `Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vdmpyacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpybus_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb_acc(vx, vu, rt) +} + +/// `Vdd32.w=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpyhb_dv(vuu, rt) +} + +/// `Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vdmpyacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpyhb_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat(vu, vv) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat_acc(vx, vu, vv) +} + +/// `Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdsaduh(vuu, rt) +} + +/// `Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdsaduh_acc(vxx, vuu, rt) +} + +/// `Vx32.w=vinsert(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vinsertwr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { + vinsertwr(vx, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlalignb(vu, vv, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlalignbi(vu, vv, iu3) +} + +/// `Vd32.uh=vlsr(Vu32.uh,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrh(vu, rt) +} + +/// `Vd32.h=vlsr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrhv(vu, vv) +} + +/// `Vd32.uw=vlsr(Vu32.uw,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrw(vu, rt) +} + +/// `Vd32.w=vlsr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrwv(vu, vv) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32or_vbvbvbr( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVector { + vlutvvb_oracc(vx, vu, vv, rt) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16or_whvbvhr( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVectorPair { + vlutvwh_oracc(vxx, vu, vv, rt) +} + +/// `Vd32.h=vmax(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxh(vu, vv) +} + +/// `Vd32.ub=vmax(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxub(vu, vv) +} + +/// `Vd32.uh=vmax(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxuh(vu, vv) +} + +/// `Vd32.w=vmax(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxw(vu, vv) +} + +/// `Vd32.h=vmin(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminh(vu, vv) +} + +/// `Vd32.ub=vmin(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminub(vu, vv) +} + +/// `Vd32.uh=vmin(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminuh(vu, vv) +} + +/// `Vd32.w=vmin(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminw(vu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabus(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpaacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabus_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabusv(vuu, vvv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabuuv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabuuv(vuu, vvv) +} + +/// `Vdd32.w=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpahb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpaacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpahb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus(vu, rt) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus_acc(vxx, vu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybusv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvubvb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybusv_acc(vxx, vu, vv) +} + +/// `Vdd32.h=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvbvb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybv_acc(vxx, vu, vv) +} + +/// `Vd32.w=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyewuh(vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh(vu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyhsat_acc(vxx, vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhsrs(vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhss))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhss(vu, rt) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhus(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhus_acc(vxx, vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhv(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhvsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyhvsrs(vu, vv) +} + +/// `Vd32.w=vmpyieo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyieoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyieoh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewh_acc(vx, vu, vv) +} + +/// `Vd32.w=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih(vu, vv) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb(vu, rt) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyio(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiowh(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh(vu, vv) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh_rnd(vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_rnd_sacc(vx, vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_sacc(vx, vu, vv) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyub(vu, rt) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyub_acc(vxx, vu, rt) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyubv(vu, vv) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyubv_acc(vxx, vu, vv) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyuh(vu, rt) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyuh_acc(vxx, vu, rt) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyuhv(vu, vv) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyuhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vnavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgh(vu, vv) +} + +/// `Vd32.b=vnavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgub(vu, vv) +} + +/// `Vd32.w=vnavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgw(vu, vv) +} + +/// `Vd32.h=vnormamt(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { + vnormamth(vu) +} + +/// `Vd32.w=vnormamt(Vu32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamtw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { + vnormamtw(vu) +} + +/// `Vd32=vnot(Vu32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnot))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { + vnot(vu) +} + +/// `Vd32=vor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_or(vu, vv) +} + +/// `Vd32.b=vpacke(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeb(vu, vv) +} + +/// `Vd32.h=vpacke(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeh(vu, vv) +} + +/// `Vd32.b=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhb_sat(vu, vv) +} + +/// `Vd32.ub=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhub_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhub_sat(vu, vv) +} + +/// `Vd32.b=vpacko(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackob(vu, vv) +} + +/// `Vd32.h=vpacko(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackoh(vu, vv) +} + +/// `Vd32.h=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwh_sat(vu, vv) +} + +/// `Vd32.uh=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwuh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwuh_sat(vu, vv) +} + +/// `Vd32.h=vpopcount(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpopcounth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { + vpopcounth(vu) +} + +/// `Vd32=vrdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrdelta(vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus(vu, rt) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpybusi(vuu, rt, iu1) +} + +/// `Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpybusi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv_acc(vx, vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv_acc(vx, vu, vv) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub(vu, rt) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub_acc(vx, vu, rt) +} + +/// `Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpyubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpyubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv(vu, vv) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv_acc(vx, vu, vv) +} + +/// `Vd32=vror(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vror))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { + vror(vu, rt) +} + +/// `Vd32.b=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhb(vu, vv) +} + +/// `Vd32.ub=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhub(vu, vv) +} + +/// `Vd32.h=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwh(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwuh(vu, vv) +} + +/// `Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrsadubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrsadubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.ub=vsat(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsathub(vu, vv) +} + +/// `Vd32.h=vsat(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsatwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatwh(vu, vv) +} + +/// `Vdd32.h=vsxt(Vu32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { + vsb(vu) +} + +/// `Vdd32.w=vsxt(Vu32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { + vsh(vu) +} + +/// `Vd32.h=vshuffe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufeh(vu, vv) +} + +/// `Vd32.b=vshuff(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { + vshuffb(vu) +} + +/// `Vd32.b=vshuffe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffeb(vu, vv) +} + +/// `Vd32.h=vshuff(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { + vshuffh(vu) +} + +/// `Vd32.b=vshuffo(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffob(vu, vv) +} + +/// `Vdd32=vshuff(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vshuffvdd(vu, vv, rt) +} + +/// `Vdd32.b=vshuffoe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeb(vu, vv) +} + +/// `Vdd32.h=vshuffoe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeh(vu, vv) +} + +/// `Vd32.h=vshuffo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufoh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubb(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubb_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubh(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubh_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubhsat(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubhw(vu, vv) +} + +/// `Vdd32.h=vsub(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsububh(vu, vv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsububsat(vu, vv) +} + +/// `Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsububsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuhsat(vu, vv) +} + +/// `Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubuhw(vu, vv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_sub(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubw_dv(vuu, vvv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubwsat(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubwsat_dv(vuu, vvv) +} + +/// `Vdd32.h=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyb(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpyacc_whwbrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpybus(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpyacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpybus_acc(vxx, vuu, rt) +} + +/// `Vdd32.w=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyhb(vuu, rt) +} + +/// `Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vtmpyacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyhb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vunpack(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { + vunpackb(vu) +} + +/// `Vdd32.w=vunpack(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { + vunpackh(vu) +} + +/// `Vxx32.h|=vunpacko(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackob(vxx, vu) +} + +/// `Vxx32.w|=vunpacko(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackoh(vxx, vu) +} + +/// `Vdd32.uh=vunpack(Vu32.ub)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { + vunpackub(vu) +} + +/// `Vdd32.uw=vunpack(Vu32.uh)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { + vunpackuh(vu) +} + +/// `Vd32=vxor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vxor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_xor(vu, vv) +} + +/// `Vdd32.uh=vzxt(Vu32.ub)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { + vzb(vu) +} + +/// `Vdd32.uw=vzxt(Vu32.uh)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { + vzh(vu) +} + +/// `Vd32.b=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplatb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { + lvsplatb(rt) +} + +/// `Vd32.h=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplath))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { + lvsplath(rt) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddbsat(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddbsat_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(vclb(Vu32.h),Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbh(vu, vv) +} + +/// `Vd32.w=vadd(vclb(Vu32.w),Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbw(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vaddacc_wwvhvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddhw_acc(vxx, vu, vv) +} + +/// `Vxx32.h+=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddubh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vaddacc_whvubvub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddubh_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddububb_sat(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vaddacc_wwvuhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vadduhw_acc(vxx, vu, vv) +} + +/// `Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduwsat(vu, vv) +} + +/// `Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrhbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasruwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhrndsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vlsr(Vu32.ub,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlsrb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrb(vu, rt) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb_nm(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32or_vbvbvbi( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVector { + vlutvvb_oracci(vx, vu, vv, iu3) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlutvvbi(vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh_nm(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16or_whvbvhi( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVectorPair { + vlutvwh_oracci(vxx, vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwhi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { + vlutvwhi(vu, vv, iu3) +} + +/// `Vd32.b=vmax(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmaxb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxb(vu, vv) +} + +/// `Vd32.b=vmin(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vminb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminb(vu, vv) +} + +/// `Vdd32.w=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpauhb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpaacc_wwwuhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpauhb_acc(vxx, vuu, rt) +} + +/// `Vdd32=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyewuh_64))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyewuh_64(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub_acc(vx, vu, rt) +} + +/// `Vxx32+=vmpyo(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyowh_64_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vmpyoacc_wvwvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyowh_64_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vround(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduhub(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduwuh(vu, vv) +} + +/// `Vd32.uh=vsat(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsatuwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatuwuh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubbsat(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubbsat_dv(vuu, vvv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubububb_sat(vu, vv) +} + +/// `Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuwsat(vu, vv) +} + +/// `Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vabs(Vu32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { + vabsb(vu) +} + +/// `Vd32.b=vabs(Vu32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { + vabsb_sat(vu) +} + +/// `Vx32.h+=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vaslh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslh_acc(vx, vu, rt) +} + +/// `Vx32.h+=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasrh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrh_acc(vx, vu, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhsat(vu, vv, rt) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgb(vu, vv) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgbrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgbrnd(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguw(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguwrnd(vu, vv) +} + +/// `Vdd32=#0` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vdd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vzero() -> HvxVectorPair { + vdd0() +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermh(rs, rt, mu, vv) +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { + vgathermhw(rs, rt, mu, vvv) +} + +/// `vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermw(rs, rt, mu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabuu(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpaacc_whwubrub( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabuu_acc(vxx, vuu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh_acc(vxx, vu, rt) +} + +/// `Vd32.uw=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe(vu, rt) +} + +/// `Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe_acc(vx, vu, rt) +} + +/// `Vd32.b=vnavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vnavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgb(vu, vv) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh_add(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw_add(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw_add(rt, mu, vv, vw) +} + +/// `Vxx32.w=vasrinto(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vasr_into))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vasrinto_wwvwvw( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vasr_into(vxx, vu, vv) +} + +/// `Vd32.uw=vrotr(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vrotr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrotr(vu, vv) +} + +/// `Vd32.w=vsatdw(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vsatdw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatdw(vu, vv) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpy_wubwbi_h( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpy_wubwbi_v( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vd32.hf=vabs(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { + vabs_hf(vu) +} + +/// `Vd32.sf=vabs(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { + vabs_sf(vu) +} + +/// `Vd32.qf16=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf(vu, vv) +} + +/// `Vd32.hf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf(vu, vv) +} + +/// `Vdd32.sf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadd_sf_hf(vu, vv) +} + +/// `Vd32.sf=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf_sf(vu, vv) +} + +/// `Vd32.w=vfmv(Vu32.w)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vassign_fp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { + vassign_fp(vu) +} + +/// `Vd32.hf=Vu32.qf16` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { + vconv_hf_qf16(vu) +} + +/// `Vd32.hf=Vuu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { + vconv_hf_qf32(vuu) +} + +/// `Vd32.sf=Vu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_sf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { + vconv_sf_qf32(vu) +} + +/// `Vd32.b=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_b_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_b_hf(vu, vv) +} + +/// `Vd32.h=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { + vcvt_h_hf(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_b(vu) +} + +/// `Vd32.hf=vcvt(Vu32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { + vcvt_hf_h(vu) +} + +/// `Vd32.hf=vcvt(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_hf_sf(vu, vv) +} + +/// `Vdd32.hf=vcvt(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_ub(vu) +} + +/// `Vd32.hf=vcvt(Vu32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_uh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { + vcvt_hf_uh(vu) +} + +/// `Vdd32.sf=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { + vcvt_sf_hf(vu) +} + +/// `Vd32.ub=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_ub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_ub_hf(vu, vv) +} + +/// `Vd32.uh=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_uh_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { + vcvt_uh_hf(vu) +} + +/// `Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf(vu, vv) +} + +/// `Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf_acc(vx, vu, vv) +} + +/// `Vd32.hf=vfmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_hf(vu, vv) +} + +/// `Vd32.sf=vfmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_sf(vu, vv) +} + +/// `Vd32.hf=vfmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_hf(vu, vv) +} + +/// `Vd32.sf=vfmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_sf(vu, vv) +} + +/// `Vd32.hf=vfneg(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { + vfneg_hf(vu) +} + +/// `Vd32.sf=vfneg(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { + vfneg_sf(vu) +} + +/// `Vd32.hf=vmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_hf(vu, vv) +} + +/// `Vd32.sf=vmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_sf(vu, vv) +} + +/// `Vd32.hf=vmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_hf(vu, vv) +} + +/// `Vd32.sf=vmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_sf(vu, vv) +} + +/// `Vd32.hf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf(vu, vv) +} + +/// `Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf_acc(vx, vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_hf(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_mix_hf(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_mix_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_qf16(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32_sf(vu, vv) +} + +/// `Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_sf_hf(vu, vv) +} + +/// `Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpy_sf_hf_acc(vxx, vu, vv) +} + +/// `Vd32.sf=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_sf_sf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf(vu, vv) +} + +/// `Vd32.hf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf(vu, vv) +} + +/// `Vdd32.sf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsub_sf_hf(vu, vv) +} + +/// `Vd32.sf=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf_sf(vu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubrndsat(vuu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhrndsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhsat(vuu, vv) +} + +/// `Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vmpyuhvs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyuhvs(vu, vv) +} + +/// `Vd32.h=Vu32.hf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { + vconv_h_hf(vu) +} + +/// `Vd32.hf=Vu32.h` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { + vconv_hf_h(vu) +} + +/// `Vd32.sf=Vu32.w` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_sf_w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { + vconv_sf_w(vu) +} + +/// `Vd32.w=Vu32.sf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_w_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { + vconv_w_sf(vu) +} + +/// `Vd32=vgetqfext(Vu32.x,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(get_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { + get_qfext(vu, rt) +} + +/// `Vd32.x=vsetqfext(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(set_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { + set_qfext(vu, rt) +} + +/// `Vd32.f8=vabs(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vabs_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { + vabs_f8(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_b(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_ub(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt_hf_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_f8(vu) +} + +/// `Vd32.f8=vfmax(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmax_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_f8(vu, vv) +} + +/// `Vd32.f8=vfmin(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmin_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_f8(vu, vv) +} + +/// `Vd32.f8=vfneg(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfneg_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { + vfneg_f8(vu) +} + +/// `Qd4=and(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=and(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=not(Qs4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_not(vandvrt( + core::mem::transmute::(qs), + -1, + )), + -1, + )) +} + +/// `Qd4=or(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=or(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=vsetq(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2(rt), -1)) +} + +/// `Qd4=xor(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_xor( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `if (!Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vd32=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt(core::mem::transmute::(qu), rt) +} + +/// `Vx32|=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt_acc(vx, core::mem::transmute::(qu), rt) +} + +/// `Qd4=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vu, rt)) +} + +/// `Qx4|=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt_acc( + core::mem::transmute::(qx), + vu, + rt, + )) +} + +/// `Qd4=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgth(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtub(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Vd32=vmux(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmux( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `if (!Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vdd32=vswap(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vswap( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `Qd4=vsetq2(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2v2(rt), -1)) +} + +/// `Qd4.b=vshuffe(Qs4.h,Qt4.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqh( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4.h=vshuffe(Qs4.w,Qt4.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqw( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Vd32=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt( + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vx32|=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt_acc( + vx, + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vd32=vand(!Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvnqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `Vd32=vand(Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmvh( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermhq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmww( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, +) { + vgathermhwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + ) +} + +/// `if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmvw( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `Vd32.b=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqb(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.h=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqh(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.w=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqw(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmvhv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermhq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmwwv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, + vw: HvxVector, +) { + vscattermhwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmvwv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( + vu: HvxVector, + vv: HvxVector, + qs: HvxVectorPred, +) -> HvxVector { + vaddcarrysat( + vu, + vv, + vandvrt(core::mem::transmute::(qs), -1), + ) +} + +/// `Qd4=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgthf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtsf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} diff --git a/stdarch/crates/core_arch/src/hexagon/v64.rs b/stdarch/crates/core_arch/src/hexagon/v64.rs new file mode 100644 index 0000000000000..023a8711d21f3 --- /dev/null +++ b/stdarch/crates/core_arch/src/hexagon/v64.rs @@ -0,0 +1,7489 @@ +//! Hexagon HVX 64-byte vector mode intrinsics +//! +//! This module provides intrinsics for the Hexagon Vector Extensions (HVX) +//! in 64-byte vector mode (512-bit vectors). +//! +//! HVX is a wide vector extension designed for high-performance signal processing. +//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61) +//! +//! ## Vector Types +//! +//! In 64-byte mode: +//! - `HvxVector` is 512 bits (64 bytes) containing 16 x 32-bit values +//! - `HvxVectorPair` is 1024 bits (128 bytes) +//! - `HvxVectorPred` is 512 bits (64 bytes) for predicate operations +//! +//! To use this module, compile with `-C target-feature=+hvx-length64b`. +//! +//! ## Architecture Versions +//! +//! Different intrinsics require different HVX architecture versions. Use the +//! appropriate target feature to enable the required version: +//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations) +//! - HVX v62: `-C target-feature=+hvxv62` +//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support) +//! - HVX v66: `-C target-feature=+hvxv66` +//! - HVX v68: `-C target-feature=+hvxv68` +//! - HVX v69: `-C target-feature=+hvxv69` +//! - HVX v73: `-C target-feature=+hvxv73` +//! - HVX v79: `-C target-feature=+hvxv79` +//! +//! Each version includes all features from previous versions. + +#![allow(non_camel_case_types)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use crate::intrinsics::simd::{simd_add, simd_and, simd_or, simd_sub, simd_xor}; + +// HVX type definitions for 64-byte vector mode +types! { + #![unstable(feature = "stdarch_hexagon", issue = "151523")] + + /// HVX vector type (512 bits / 64 bytes) + /// + /// This type represents a single HVX vector register containing 16 x 32-bit values. + pub struct HvxVector(16 x i32); + + /// HVX vector pair type (1024 bits / 128 bytes) + /// + /// This type represents a pair of HVX vector registers, often used for + /// operations that produce double-width results. + pub struct HvxVectorPair(32 x i32); + + /// HVX vector predicate type (512 bits / 64 bytes) + /// + /// This type represents a predicate vector used for conditional operations. + /// Each bit corresponds to a lane in the vector. + pub struct HvxVectorPred(16 x i32); +} + +// LLVM intrinsic declarations for 64-byte vector mode +#[allow(improper_ctypes)] +unsafe extern "unadjusted" { + #[link_name = "llvm.hexagon.V6.extractw"] + fn extractw(_: HvxVector, _: i32) -> i32; + #[link_name = "llvm.hexagon.V6.get.qfext"] + fn get_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.hi"] + fn hi(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lo"] + fn lo(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatb"] + fn lvsplatb(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplath"] + fn lvsplath(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.lvsplatw"] + fn lvsplatw(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and"] + fn pred_and(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.and.n"] + fn pred_and_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.not"] + fn pred_not(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or"] + fn pred_or(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.or.n"] + fn pred_or_n(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2"] + fn pred_scalar2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.scalar2v2"] + fn pred_scalar2v2(_: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.pred.xor"] + fn pred_xor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.set.qfext"] + fn set_qfext(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqh"] + fn shuffeqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.shuffeqw"] + fn shuffeqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10"] + fn v6mpyhubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyhubs10.vxx"] + fn v6mpyhubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10"] + fn v6mpyvubs10(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.v6mpyvubs10.vxx"] + fn v6mpyvubs10_vxx( + _: HvxVectorPair, + _: HvxVectorPair, + _: HvxVectorPair, + _: i32, + ) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vS32b.nqpred.ai"] + fn vS32b_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.nqpred.ai"] + fn vS32b_nt_nqpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.nt.qpred.ai"] + fn vS32b_nt_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vS32b.qpred.ai"] + fn vS32b_qpred_ai(_: HvxVector, _: *mut HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vabs.f8"] + fn vabs_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.hf"] + fn vabs_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabs.sf"] + fn vabs_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb"] + fn vabsb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsb.sat"] + fn vabsb_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffh"] + fn vabsdiffh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffub"] + fn vabsdiffub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffuh"] + fn vabsdiffuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsdiffw"] + fn vabsdiffw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh"] + fn vabsh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsh.sat"] + fn vabsh_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw"] + fn vabsw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vabsw.sat"] + fn vabsw_sat(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf"] + fn vadd_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.hf.hf"] + fn vadd_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16"] + fn vadd_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf16.mix"] + fn vadd_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32"] + fn vadd_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.qf32.mix"] + fn vadd_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf"] + fn vadd_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadd.sf.hf"] + fn vadd_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadd.sf.sf"] + fn vadd_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb"] + fn vaddb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddb.dv"] + fn vaddb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddbnq"] + fn vaddbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbq"] + fn vaddbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat"] + fn vaddbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddbsat.dv"] + fn vaddbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddcarrysat"] + fn vaddcarrysat(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbh"] + fn vaddclbh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddclbw"] + fn vaddclbw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh"] + fn vaddh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddh.dv"] + fn vaddh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhnq"] + fn vaddhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhq"] + fn vaddhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat"] + fn vaddhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddhsat.dv"] + fn vaddhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw"] + fn vaddhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddhw.acc"] + fn vaddhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh"] + fn vaddubh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubh.acc"] + fn vaddubh_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddubsat"] + fn vaddubsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddubsat.dv"] + fn vaddubsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddububb.sat"] + fn vaddububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat"] + fn vadduhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduhsat.dv"] + fn vadduhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw"] + fn vadduhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduhw.acc"] + fn vadduhw_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vadduwsat"] + fn vadduwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vadduwsat.dv"] + fn vadduwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddw"] + fn vaddw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddw.dv"] + fn vaddw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vaddwnq"] + fn vaddwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwq"] + fn vaddwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat"] + fn vaddwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaddwsat.dv"] + fn vaddwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.valignb"] + fn valignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.valignbi"] + fn valignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vand"] + fn vand(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt"] + fn vandnqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandnqrt.acc"] + fn vandnqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt"] + fn vandqrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandqrt.acc"] + fn vandqrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvnqv"] + fn vandvnqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvqv"] + fn vandvqv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt"] + fn vandvrt(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vandvrt.acc"] + fn vandvrt_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh"] + fn vaslh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslh.acc"] + fn vaslh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslhv"] + fn vaslhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw"] + fn vaslw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslw.acc"] + fn vaslw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vaslwv"] + fn vaslwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasr.into"] + fn vasr_into(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vasrh"] + fn vasrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrh.acc"] + fn vasrh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbrndsat"] + fn vasrhbrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhbsat"] + fn vasrhbsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubrndsat"] + fn vasrhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhubsat"] + fn vasrhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrhv"] + fn vasrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubrndsat"] + fn vasruhubrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruhubsat"] + fn vasruhubsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhrndsat"] + fn vasruwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasruwuhsat"] + fn vasruwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubrndsat"] + fn vasrvuhubrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvuhubsat"] + fn vasrvuhubsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhrndsat"] + fn vasrvwuhrndsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrvwuhsat"] + fn vasrvwuhsat(_: HvxVectorPair, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw"] + fn vasrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrw.acc"] + fn vasrw_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwh"] + fn vasrwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhrndsat"] + fn vasrwhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwhsat"] + fn vasrwhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhrndsat"] + fn vasrwuhrndsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwuhsat"] + fn vasrwuhsat(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vasrwv"] + fn vasrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign"] + fn vassign(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassign.fp"] + fn vassign_fp(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vassignp"] + fn vassignp(_: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vavgb"] + fn vavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgbrnd"] + fn vavgbrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgh"] + fn vavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavghrnd"] + fn vavghrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgub"] + fn vavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgubrnd"] + fn vavgubrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguh"] + fn vavguh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguhrnd"] + fn vavguhrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguw"] + fn vavguw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavguwrnd"] + fn vavguwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgw"] + fn vavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vavgwrnd"] + fn vavgwrnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0h"] + fn vcl0h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcl0w"] + fn vcl0w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcombine"] + fn vcombine(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vconv.h.hf"] + fn vconv_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.h"] + fn vconv_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf16"] + fn vconv_hf_qf16(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.hf.qf32"] + fn vconv_hf_qf32(_: HvxVectorPair) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.qf32"] + fn vconv_sf_qf32(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.sf.w"] + fn vconv_sf_w(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vconv.w.sf"] + fn vconv_w_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.b"] + fn vcvt2_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt2.hf.ub"] + fn vcvt2_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.b.hf"] + fn vcvt_b_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.h.hf"] + fn vcvt_h_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.b"] + fn vcvt_hf_b(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.f8"] + fn vcvt_hf_f8(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.h"] + fn vcvt_hf_h(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.sf"] + fn vcvt_hf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.hf.ub"] + fn vcvt_hf_ub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.hf.uh"] + fn vcvt_hf_uh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.sf.hf"] + fn vcvt_sf_hf(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vcvt.ub.hf"] + fn vcvt_ub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vcvt.uh.hf"] + fn vcvt_uh_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vd0"] + fn vd0() -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdd0"] + fn vdd0() -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdealb"] + fn vdealb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealb4w"] + fn vdealb4w(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealh"] + fn vdealh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdealvdd"] + fn vdealvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdelta"] + fn vdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf"] + fn vdmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpy.sf.hf.acc"] + fn vdmpy_sf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus"] + fn vdmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.acc"] + fn vdmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv"] + fn vdmpybus_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpybus.dv.acc"] + fn vdmpybus_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb"] + fn vdmpyhb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.acc"] + fn vdmpyhb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv"] + fn vdmpyhb_dv(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhb.dv.acc"] + fn vdmpyhb_dv_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdmpyhisat"] + fn vdmpyhisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhisat.acc"] + fn vdmpyhisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat"] + fn vdmpyhsat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsat.acc"] + fn vdmpyhsat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat"] + fn vdmpyhsuisat(_: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsuisat.acc"] + fn vdmpyhsuisat_acc(_: HvxVector, _: HvxVectorPair, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat"] + fn vdmpyhsusat(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhsusat.acc"] + fn vdmpyhsusat_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat"] + fn vdmpyhvsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdmpyhvsat.acc"] + fn vdmpyhvsat_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vdsaduh"] + fn vdsaduh(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vdsaduh.acc"] + fn vdsaduh_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.veqb"] + fn veqb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.and"] + fn veqb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.or"] + fn veqb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqb.xor"] + fn veqb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh"] + fn veqh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.and"] + fn veqh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.or"] + fn veqh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqh.xor"] + fn veqh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw"] + fn veqw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.and"] + fn veqw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.or"] + fn veqw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.veqw.xor"] + fn veqw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.f8"] + fn vfmax_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.hf"] + fn vfmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmax.sf"] + fn vfmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.f8"] + fn vfmin_f8(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.hf"] + fn vfmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfmin.sf"] + fn vfmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.f8"] + fn vfneg_f8(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.hf"] + fn vfneg_hf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vfneg.sf"] + fn vfneg_sf(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgathermh"] + fn vgathermh(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhq"] + fn vgathermhq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhw"] + fn vgathermhw(_: *mut HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermhwq"] + fn vgathermhwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVectorPair) -> (); + #[link_name = "llvm.hexagon.V6.vgathermw"] + fn vgathermw(_: *mut HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgathermwq"] + fn vgathermwq(_: *mut HvxVector, _: HvxVector, _: i32, _: i32, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vgtb"] + fn vgtb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.and"] + fn vgtb_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.or"] + fn vgtb_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtb.xor"] + fn vgtb_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth"] + fn vgth(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.and"] + fn vgth_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.or"] + fn vgth_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgth.xor"] + fn vgth_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf"] + fn vgthf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.and"] + fn vgthf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.or"] + fn vgthf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgthf.xor"] + fn vgthf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf"] + fn vgtsf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.and"] + fn vgtsf_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.or"] + fn vgtsf_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtsf.xor"] + fn vgtsf_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub"] + fn vgtub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.and"] + fn vgtub_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.or"] + fn vgtub_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtub.xor"] + fn vgtub_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh"] + fn vgtuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.and"] + fn vgtuh_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.or"] + fn vgtuh_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuh.xor"] + fn vgtuh_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw"] + fn vgtuw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.and"] + fn vgtuw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.or"] + fn vgtuw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtuw.xor"] + fn vgtuw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw"] + fn vgtw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.and"] + fn vgtw_and(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.or"] + fn vgtw_or(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vgtw.xor"] + fn vgtw_xor(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vinsertwr"] + fn vinsertwr(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignb"] + fn vlalignb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlalignbi"] + fn vlalignbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrb"] + fn vlsrb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrh"] + fn vlsrh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrhv"] + fn vlsrhv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrw"] + fn vlsrw(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlsrwv"] + fn vlsrwv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb"] + fn vlutvvb(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.nm"] + fn vlutvvb_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracc"] + fn vlutvvb_oracc(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvb.oracci"] + fn vlutvvb_oracci(_: HvxVector, _: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvvbi"] + fn vlutvvbi(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vlutvwh"] + fn vlutvwh(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.nm"] + fn vlutvwh_nm(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracc"] + fn vlutvwh_oracc(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwh.oracci"] + fn vlutvwh_oracci(_: HvxVectorPair, _: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vlutvwhi"] + fn vlutvwhi(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmax.hf"] + fn vmax_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmax.sf"] + fn vmax_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxb"] + fn vmaxb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxh"] + fn vmaxh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxub"] + fn vmaxub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxuh"] + fn vmaxuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmaxw"] + fn vmaxw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.hf"] + fn vmin_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmin.sf"] + fn vmin_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminb"] + fn vminb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminh"] + fn vminh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminub"] + fn vminub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminuh"] + fn vminuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vminw"] + fn vminw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpabus"] + fn vmpabus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabus.acc"] + fn vmpabus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabusv"] + fn vmpabusv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu"] + fn vmpabuu(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuu.acc"] + fn vmpabuu_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpabuuv"] + fn vmpabuuv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb"] + fn vmpahb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpahb.acc"] + fn vmpahb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb"] + fn vmpauhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpauhb.acc"] + fn vmpauhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf"] + fn vmpy_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.hf.hf.acc"] + fn vmpy_hf_hf_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16"] + fn vmpy_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.hf"] + fn vmpy_qf16_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf16.mix.hf"] + fn vmpy_qf16_mix_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32"] + fn vmpy_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.hf"] + fn vmpy_qf32_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.mix.hf"] + fn vmpy_qf32_mix_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.qf16"] + fn vmpy_qf32_qf16(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.qf32.sf"] + fn vmpy_qf32_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf"] + fn vmpy_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.hf.acc"] + fn vmpy_sf_hf_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpy.sf.sf"] + fn vmpy_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpybus"] + fn vmpybus(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybus.acc"] + fn vmpybus_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv"] + fn vmpybusv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybusv.acc"] + fn vmpybusv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv"] + fn vmpybv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpybv.acc"] + fn vmpybv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyewuh"] + fn vmpyewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyewuh.64"] + fn vmpyewuh_64(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh"] + fn vmpyh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyh.acc"] + fn vmpyh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsat.acc"] + fn vmpyhsat_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhsrs"] + fn vmpyhsrs(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhss"] + fn vmpyhss(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyhus"] + fn vmpyhus(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhus.acc"] + fn vmpyhus_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv"] + fn vmpyhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhv.acc"] + fn vmpyhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyhvsrs"] + fn vmpyhvsrs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyieoh"] + fn vmpyieoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewh.acc"] + fn vmpyiewh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh"] + fn vmpyiewuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiewuh.acc"] + fn vmpyiewuh_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih"] + fn vmpyih(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyih.acc"] + fn vmpyih_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb"] + fn vmpyihb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyihb.acc"] + fn vmpyihb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiowh"] + fn vmpyiowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb"] + fn vmpyiwb(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwb.acc"] + fn vmpyiwb_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh"] + fn vmpyiwh(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwh.acc"] + fn vmpyiwh_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub"] + fn vmpyiwub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyiwub.acc"] + fn vmpyiwub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh"] + fn vmpyowh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.64.acc"] + fn vmpyowh_64_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd"] + fn vmpyowh_rnd(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.rnd.sacc"] + fn vmpyowh_rnd_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyowh.sacc"] + fn vmpyowh_sacc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyub"] + fn vmpyub(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyub.acc"] + fn vmpyub_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv"] + fn vmpyubv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyubv.acc"] + fn vmpyubv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh"] + fn vmpyuh(_: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuh.acc"] + fn vmpyuh_acc(_: HvxVectorPair, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhe"] + fn vmpyuhe(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhe.acc"] + fn vmpyuhe_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmpyuhv"] + fn vmpyuhv(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhv.acc"] + fn vmpyuhv_acc(_: HvxVectorPair, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vmpyuhvs"] + fn vmpyuhvs(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vmux"] + fn vmux(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgb"] + fn vnavgb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgh"] + fn vnavgh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgub"] + fn vnavgub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnavgw"] + fn vnavgw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamth"] + fn vnormamth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnormamtw"] + fn vnormamtw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vnot"] + fn vnot(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vor"] + fn vor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeb"] + fn vpackeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackeh"] + fn vpackeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhb.sat"] + fn vpackhb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackhub.sat"] + fn vpackhub_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackob"] + fn vpackob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackoh"] + fn vpackoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwh.sat"] + fn vpackwh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpackwuh.sat"] + fn vpackwuh_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vpopcounth"] + fn vpopcounth(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqb"] + fn vprefixqb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqh"] + fn vprefixqh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vprefixqw"] + fn vprefixqw(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrdelta"] + fn vrdelta(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus"] + fn vrmpybus(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybus.acc"] + fn vrmpybus_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusi"] + fn vrmpybusi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusi.acc"] + fn vrmpybusi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpybusv"] + fn vrmpybusv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybusv.acc"] + fn vrmpybusv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv"] + fn vrmpybv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpybv.acc"] + fn vrmpybv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub"] + fn vrmpyub(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyub.acc"] + fn vrmpyub_acc(_: HvxVector, _: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubi"] + fn vrmpyubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubi.acc"] + fn vrmpyubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrmpyubv"] + fn vrmpyubv(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrmpyubv.acc"] + fn vrmpyubv_acc(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vror"] + fn vror(_: HvxVector, _: i32) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrotr"] + fn vrotr(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhb"] + fn vroundhb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundhub"] + fn vroundhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduhub"] + fn vrounduhub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrounduwuh"] + fn vrounduwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwh"] + fn vroundwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vroundwuh"] + fn vroundwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vrsadubi"] + fn vrsadubi(_: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vrsadubi.acc"] + fn vrsadubi_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsatdw"] + fn vsatdw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsathub"] + fn vsathub(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatuwuh"] + fn vsatuwuh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsatwh"] + fn vsatwh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsb"] + fn vsb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vscattermh"] + fn vscattermh(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermh.add"] + fn vscattermh_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhq"] + fn vscattermhq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw"] + fn vscattermhw(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhw.add"] + fn vscattermhw_add(_: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermhwq"] + fn vscattermhwq(_: HvxVector, _: i32, _: i32, _: HvxVectorPair, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw"] + fn vscattermw(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermw.add"] + fn vscattermw_add(_: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vscattermwq"] + fn vscattermwq(_: HvxVector, _: i32, _: i32, _: HvxVector, _: HvxVector) -> (); + #[link_name = "llvm.hexagon.V6.vsh"] + fn vsh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufeh"] + fn vshufeh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffb"] + fn vshuffb(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffeb"] + fn vshuffeb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffh"] + fn vshuffh(_: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffob"] + fn vshuffob(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vshuffvdd"] + fn vshuffvdd(_: HvxVector, _: HvxVector, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeb"] + fn vshufoeb(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoeh"] + fn vshufoeh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vshufoh"] + fn vshufoh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf"] + fn vsub_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.hf.hf"] + fn vsub_hf_hf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16"] + fn vsub_qf16(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf16.mix"] + fn vsub_qf16_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32"] + fn vsub_qf32(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.qf32.mix"] + fn vsub_qf32_mix(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf"] + fn vsub_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsub.sf.hf"] + fn vsub_sf_hf(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsub.sf.sf"] + fn vsub_sf_sf(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb"] + fn vsubb(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubb.dv"] + fn vsubb_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubbnq"] + fn vsubbnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbq"] + fn vsubbq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat"] + fn vsubbsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubbsat.dv"] + fn vsubbsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubh"] + fn vsubh(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubh.dv"] + fn vsubh_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhnq"] + fn vsubhnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhq"] + fn vsubhq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat"] + fn vsubhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubhsat.dv"] + fn vsubhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubhw"] + fn vsubhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububh"] + fn vsububh(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsububsat"] + fn vsububsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsububsat.dv"] + fn vsububsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubububb.sat"] + fn vsubububb_sat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat"] + fn vsubuhsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuhsat.dv"] + fn vsubuhsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuhw"] + fn vsubuhw(_: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubuwsat"] + fn vsubuwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubuwsat.dv"] + fn vsubuwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubw"] + fn vsubw(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubw.dv"] + fn vsubw_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vsubwnq"] + fn vsubwnq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwq"] + fn vsubwq(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat"] + fn vsubwsat(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vsubwsat.dv"] + fn vsubwsat_dv(_: HvxVectorPair, _: HvxVectorPair) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vswap"] + fn vswap(_: HvxVector, _: HvxVector, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb"] + fn vtmpyb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyb.acc"] + fn vtmpyb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus"] + fn vtmpybus(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpybus.acc"] + fn vtmpybus_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb"] + fn vtmpyhb(_: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vtmpyhb.acc"] + fn vtmpyhb_acc(_: HvxVectorPair, _: HvxVectorPair, _: i32) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackb"] + fn vunpackb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackh"] + fn vunpackh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackob"] + fn vunpackob(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackoh"] + fn vunpackoh(_: HvxVectorPair, _: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackub"] + fn vunpackub(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vunpackuh"] + fn vunpackuh(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vxor"] + fn vxor(_: HvxVector, _: HvxVector) -> HvxVector; + #[link_name = "llvm.hexagon.V6.vzb"] + fn vzb(_: HvxVector) -> HvxVectorPair; + #[link_name = "llvm.hexagon.V6.vzh"] + fn vzh(_: HvxVector) -> HvxVectorPair; +} + +/// `Rd32=vextract(Vu32,Rs32)` +/// +/// Instruction Type: LD +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(extractw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_r_vextract_vr(vu: HvxVector, rs: i32) -> i32 { + extractw(vu, rs) +} + +/// `Vd32=hi(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(hi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_hi_w(vss: HvxVectorPair) -> HvxVector { + hi(vss) +} + +/// `Vd32=lo(Vss32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lo))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_lo_w(vss: HvxVectorPair) -> HvxVector { + lo(vss) +} + +/// `Vd32=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(lvsplatw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vsplat_r(rt: i32) -> HvxVector { + lvsplatw(rt) +} + +/// `Vd32.uh=vabsdiff(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vabsdiff_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffh(vu, vv) +} + +/// `Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vabsdiff_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffub(vu, vv) +} + +/// `Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vabsdiff_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffuh(vu, vv) +} + +/// `Vd32.uw=vabsdiff(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsdiffw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vabsdiff_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vabsdiffw(vu, vv) +} + +/// `Vd32.h=vabs(Vu32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vabs_vh(vu: HvxVector) -> HvxVector { + vabsh(vu) +} + +/// `Vd32.h=vabs(Vu32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vabs_vh_sat(vu: HvxVector) -> HvxVector { + vabsh_sat(vu) +} + +/// `Vd32.w=vabs(Vu32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vabs_vw(vu: HvxVector) -> HvxVector { + vabsw(vu) +} + +/// `Vd32.w=vabs(Vu32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vabsw_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vabs_vw_sat(vu: HvxVector) -> HvxVector { + vabsw_sat(vu) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vadd_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddb(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vadd_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddb_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddh(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddh_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddhsat(vu, vv) +} + +/// `Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddhw(vu, vv) +} + +/// `Vdd32.h=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vadd_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vaddubh(vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vadd_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddubsat(vu, vv) +} + +/// `Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddubsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wub_vadd_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddubsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vadd_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduhsat(vu, vv) +} + +/// `Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vadd_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vadduhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadduhw(vu, vv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_add(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddw_dv(vuu, vvv) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddwsat(vu, vv) +} + +/// `Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaddwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vadd_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddwsat_dv(vuu, vvv) +} + +/// `Vd32=valign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_valign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + valignb(vu, vv, rt) +} + +/// `Vd32=valign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(valignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_valign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + valignbi(vu, vv, iu3) +} + +/// `Vd32=vand(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vand))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_and(vu, vv) +} + +/// `Vd32.h=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasl_vhr(vu: HvxVector, rt: i32) -> HvxVector { + vaslh(vu, rt) +} + +/// `Vd32.h=vasl(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasl_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslhv(vu, vv) +} + +/// `Vd32.w=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasl_vwr(vu: HvxVector, rt: i32) -> HvxVector { + vaslw(vu, rt) +} + +/// `Vx32.w+=vasl(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vaslacc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslw_acc(vx, vu, rt) +} + +/// `Vd32.w=vasl(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vaslwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasl_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaslwv(vu, vv) +} + +/// `Vd32.h=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vhr(vu: HvxVector, rt: i32) -> HvxVector { + vasrh(vu, rt) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhbrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vhvhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhubsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrhv(vu, vv) +} + +/// `Vd32.w=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasr_vwr(vu: HvxVector, rt: i32) -> HvxVector { + vasrw(vu, rt) +} + +/// `Vx32.w+=vasr(Vu32.w,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasracc_vwvwr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrw_acc(vx, vu, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwh(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhrndsat(vu, vv, rt) +} + +/// `Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwhsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vwvwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhsat(vu, vv, rt) +} + +/// `Vd32.w=vasr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vasrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vasr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vasrwv(vu, vv) +} + +/// `Vd32=Vu32` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassign))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_equals_v(vu: HvxVector) -> HvxVector { + vassign(vu) +} + +/// `Vdd32=Vuu32` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vassignp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_equals_w(vuu: HvxVectorPair) -> HvxVectorPair { + vassignp(vuu) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgh(vu, vv) +} + +/// `Vd32.h=vavg(Vu32.h,Vv32.h):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavghrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vavg_vhvh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavghrnd(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgub(vu, vv) +} + +/// `Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgubrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vavg_vubvub_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgubrnd(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vavg_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguh(vu, vv) +} + +/// `Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavguhrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vavg_vuhvuh_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguhrnd(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgw(vu, vv) +} + +/// `Vd32.w=vavg(Vu32.w,Vv32.w):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vavgwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vavg_vwvw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgwrnd(vu, vv) +} + +/// `Vd32.uh=vcl0(Vu32.uh)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vcl0_vuh(vu: HvxVector) -> HvxVector { + vcl0h(vu) +} + +/// `Vd32.uw=vcl0(Vu32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcl0w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vcl0_vuw(vu: HvxVector) -> HvxVector { + vcl0w(vu) +} + +/// `Vdd32=vcombine(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vcombine))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vcombine_vv(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vcombine(vu, vv) +} + +/// `Vd32=#0` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vzero() -> HvxVector { + vd0() +} + +/// `Vd32.b=vdeal(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vdeal_vb(vu: HvxVector) -> HvxVector { + vdealb(vu) +} + +/// `Vd32.b=vdeale(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealb4w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vdeale_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdealb4w(vu, vv) +} + +/// `Vd32.h=vdeal(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdeal_vh(vu: HvxVector) -> HvxVector { + vdealh(vu) +} + +/// `Vdd32=vdeal(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdealvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vdeal_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vdealvdd(vu, vv, rt) +} + +/// `Vd32=vdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdelta(vu, vv) +} + +/// `Vd32.h=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus(vu, rt) +} + +/// `Vx32.h+=vdmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vdmpyacc_vhvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vdmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpybus_dv(vuu, rt) +} + +/// `Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpybus_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vdmpyacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpybus_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhrb(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhb_acc(vx, vu, rt) +} + +/// `Vdd32.w=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vdmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdmpyhb_dv(vuu, rt) +} + +/// `Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhb_dv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vdmpyacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdmpyhb_dv_acc(vxx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_whrh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwwhrh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhrh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhrh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_whruh_sat(vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat(vuu, rt) +} + +/// `Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsuisat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwwhruh_sat(vx: HvxVector, vuu: HvxVectorPair, rt: i32) -> HvxVector { + vdmpyhsuisat_acc(vx, vuu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhruh_sat(vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat(vu, rt) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhsusat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhruh_sat(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vdmpyhsusat_acc(vx, vu, rt) +} + +/// `Vd32.w=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpy_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat(vu, vv) +} + +/// `Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdmpyhvsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vdmpyacc_vwvhvh_sat(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpyhvsat_acc(vx, vu, vv) +} + +/// `Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vdsad_wuhruh(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vdsaduh(vuu, rt) +} + +/// `Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vdsaduh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vdsadacc_wuwwuhruh( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vdsaduh_acc(vxx, vuu, rt) +} + +/// `Vx32.w=vinsert(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vinsertwr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vinsert_vwr(vx: HvxVector, rt: i32) -> HvxVector { + vinsertwr(vx, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vlalign_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlalignb(vu, vv, rt) +} + +/// `Vd32=vlalign(Vu32,Vv32,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlalignbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vlalign_vvi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlalignbi(vu, vv, iu3) +} + +/// `Vd32.uh=vlsr(Vu32.uh,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vlsr_vuhr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrh(vu, rt) +} + +/// `Vd32.h=vlsr(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vlsr_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrhv(vu, vv) +} + +/// `Vd32.uw=vlsr(Vu32.uw,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vlsr_vuwr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrw(vu, rt) +} + +/// `Vd32.w=vlsr(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlsrwv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vlsr_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vlsrwv(vu, vv) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32or_vbvbvbr( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVector { + vlutvvb_oracc(vx, vu, vv, rt) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16or_whvbvhr( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + rt: i32, +) -> HvxVectorPair { + vlutvwh_oracc(vxx, vu, vv, rt) +} + +/// `Vd32.h=vmax(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmax_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxh(vu, vv) +} + +/// `Vd32.ub=vmax(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vmax_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxub(vu, vv) +} + +/// `Vd32.uh=vmax(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmax_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxuh(vu, vv) +} + +/// `Vd32.w=vmax(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmaxw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmax_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxw(vu, vv) +} + +/// `Vd32.h=vmin(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmin_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminh(vu, vv) +} + +/// `Vd32.ub=vmin(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vmin_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminub(vu, vv) +} + +/// `Vd32.uh=vmin(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmin_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminuh(vu, vv) +} + +/// `Vd32.w=vmin(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vminw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmin_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminw(vu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabus(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpaacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabus_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabusv(vuu, vvv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpabuuv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubwub(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vmpabuuv(vuu, vvv) +} + +/// `Vdd32.w=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpa_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpahb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpahb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpaacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpahb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus(vu, rt) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvubrb(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpybus_acc(vxx, vu, rt) +} + +/// `Vdd32.h=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybusv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvubvb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybusv_acc(vxx, vu, vv) +} + +/// `Vdd32.h=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpybv(vu, vv) +} + +/// `Vxx32.h+=vmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpyacc_whvbvb( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpybv_acc(vxx, vu, vv) +} + +/// `Vd32.w=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyewuh(vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhrh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh(vu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsat_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhrh_sat( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyhsat_acc(vxx, vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhrh_s1_rnd_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhsrs(vu, rt) +} + +/// `Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhss))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhrh_s1_sat(vu: HvxVector, rt: i32) -> HvxVector { + vmpyhss(vu, rt) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhus(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhus_acc(vxx, vu, vv) +} + +/// `Vdd32.w=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpy_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyhv(vu, vv) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyhvsrs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpy_vhvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyhvsrs(vu, vv) +} + +/// `Vd32.w=vmpyieo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyieoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyieoh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieacc_vwvwvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewh_acc(vx, vu, vv) +} + +/// `Vd32.w=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyie_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh(vu, vv) +} + +/// `Vx32.w+=vmpyie(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiewuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyieacc_vwvwvuh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiewuh_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyi_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih(vu, vv) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyih_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyiacc_vhvhvh(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyih_acc(vx, vu, vv) +} + +/// `Vd32.h=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyi_vhrb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb(vu, rt) +} + +/// `Vx32.h+=vmpyi(Vu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyihb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vmpyiacc_vhvhrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyihb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyio(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyio_vwvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyiowh(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrb(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwb_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyiwh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwh_acc(vx, vu, rt) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyo_vwvh_s1_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh(vu, vv) +} + +/// `Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyo_vwvh_s1_rnd_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyowh_rnd(vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_rnd_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_rnd_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_rnd_sacc(vx, vu, vv) +} + +/// `Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyowh_sacc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyoacc_vwvwvh_s1_sat_shift( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, +) -> HvxVector { + vmpyowh_sacc(vx, vu, vv) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyub(vu, rt) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpyacc_wuhvubrub( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyub_acc(vxx, vu, rt) +} + +/// `Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyubv(vu, vv) +} + +/// `Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vmpyacc_wuhvubvub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyubv_acc(vxx, vu, vv) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpy_vuhruh(vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyuh(vu, rt) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpyacc_wuwvuhruh( + vxx: HvxVectorPair, + vu: HvxVector, + rt: i32, +) -> HvxVectorPair { + vmpyuh_acc(vxx, vu, rt) +} + +/// `Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpy_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyuhv(vu, vv) +} + +/// `Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vmpyuhv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vmpyacc_wuwvuhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyuhv_acc(vxx, vu, vv) +} + +/// `Vd32.h=vnavg(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vnavg_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgh(vu, vv) +} + +/// `Vd32.b=vnavg(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vnavg_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgub(vu, vv) +} + +/// `Vd32.w=vnavg(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnavgw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vnavg_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgw(vu, vv) +} + +/// `Vd32.h=vnormamt(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vnormamt_vh(vu: HvxVector) -> HvxVector { + vnormamth(vu) +} + +/// `Vd32.w=vnormamt(Vu32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnormamtw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vnormamt_vw(vu: HvxVector) -> HvxVector { + vnormamtw(vu) +} + +/// `Vd32=vnot(Vu32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vnot))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vnot_v(vu: HvxVector) -> HvxVector { + vnot(vu) +} + +/// `Vd32=vor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_or(vu, vv) +} + +/// `Vd32.b=vpacke(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpacke_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeb(vu, vv) +} + +/// `Vd32.h=vpacke(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpacke_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackeh(vu, vv) +} + +/// `Vd32.b=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhb_sat(vu, vv) +} + +/// `Vd32.ub=vpack(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackhub_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vpack_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackhub_sat(vu, vv) +} + +/// `Vd32.b=vpacko(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vpacko_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackob(vu, vv) +} + +/// `Vd32.h=vpacko(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpacko_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackoh(vu, vv) +} + +/// `Vd32.h=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwh_sat(vu, vv) +} + +/// `Vd32.uh=vpack(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpackwuh_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vpack_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vpackwuh_sat(vu, vv) +} + +/// `Vd32.h=vpopcount(Vu32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vpopcounth))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vpopcount_vh(vu: HvxVector) -> HvxVector { + vpopcounth(vu) +} + +/// `Vd32=vrdelta(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrdelta))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vrdelta_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrdelta(vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vubrb(vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus(vu, rt) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvubrb(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpybus_acc(vx, vu, rt) +} + +/// `Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vrmpy_wubrbi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpybusi(vuu, rt, iu1) +} + +/// `Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vrmpyacc_wwwubrbi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpybusi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.w=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vubvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.ub,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybusv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvubvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybusv_acc(vx, vu, vv) +} + +/// `Vd32.w=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpy_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv(vu, vv) +} + +/// `Vx32.w+=vrmpy(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpybv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vrmpyacc_vwvbvb(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpybv_acc(vx, vu, vv) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpy_vubrub(vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub(vu, rt) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpyacc_vuwvubrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vrmpyub_acc(vx, vu, rt) +} + +/// `Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrmpy_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrmpyubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrmpyacc_wuwwubrubi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrmpyubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpy_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv(vu, vv) +} + +/// `Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrmpyubv_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrmpyacc_vuwvubvub(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vrmpyubv_acc(vx, vu, vv) +} + +/// `Vd32=vror(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vror))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vror_vr(vu: HvxVector, rt: i32) -> HvxVector { + vror(vu, rt) +} + +/// `Vd32.b=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhb(vu, vv) +} + +/// `Vd32.ub=vround(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vround_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundhub(vu, vv) +} + +/// `Vd32.h=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwh(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vroundwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vround_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vroundwuh(vu, vv) +} + +/// `Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrsad_wubrubi(vuu: HvxVectorPair, rt: i32, iu1: i32) -> HvxVectorPair { + vrsadubi(vuu, rt, iu1) +} + +/// `Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vrsadubi_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vrsadacc_wuwwubrubi( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, + iu1: i32, +) -> HvxVectorPair { + vrsadubi_acc(vxx, vuu, rt, iu1) +} + +/// `Vd32.ub=vsat(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsathub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsat_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsathub(vu, vv) +} + +/// `Vd32.h=vsat(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsatwh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsat_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatwh(vu, vv) +} + +/// `Vdd32.h=vsxt(Vu32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsxt_vb(vu: HvxVector) -> HvxVectorPair { + vsb(vu) +} + +/// `Vdd32.w=vsxt(Vu32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsxt_vh(vu: HvxVector) -> HvxVectorPair { + vsh(vu) +} + +/// `Vd32.h=vshuffe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuffe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufeh(vu, vv) +} + +/// `Vd32.b=vshuff(Vu32.b)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuff_vb(vu: HvxVector) -> HvxVector { + vshuffb(vu) +} + +/// `Vd32.b=vshuffe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuffe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffeb(vu, vv) +} + +/// `Vd32.h=vshuff(Vu32.h)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuff_vh(vu: HvxVector) -> HvxVector { + vshuffh(vu) +} + +/// `Vd32.b=vshuffo(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vshuffo_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshuffob(vu, vv) +} + +/// `Vdd32=vshuff(Vu32,Vv32,Rt8)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshuffvdd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vshuff_vvr(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vshuffvdd(vu, vv, rt) +} + +/// `Vdd32.b=vshuffoe(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vshuffoe_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeb(vu, vv) +} + +/// `Vdd32.h=vshuffoe(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoeh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vshuffoe_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vshufoeh(vu, vv) +} + +/// `Vd32.h=vshuffo(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vshufoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vshuffo_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vshufoh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsub_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubb(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubb_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vsub_wbwb(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubb_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubh(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubh_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_whwh(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubh_dv(vuu, vvv) +} + +/// `Vd32.h=vsub(Vu32.h,Vv32.h):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsub_vhvh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubhsat(vu, vv) +} + +/// `Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_whwh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubhw(vu, vv) +} + +/// `Vdd32.h=vsub(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vsub_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsububh(vu, vv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsub_vubvub_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsububsat(vu, vv) +} + +/// `Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsububsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wub_vsub_wubwub_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsububsat_dv(vuu, vvv) +} + +/// `Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vsub_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuhsat(vu, vv) +} + +/// `Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vsub_wuhwuh_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuhsat_dv(vuu, vvv) +} + +/// `Vdd32.w=vsub(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubuhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsubuhw(vu, vv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsub_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_sub(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubw_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_wwww(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubw_dv(vuu, vvv) +} + +/// `Vd32.w=vsub(Vu32.w,Vv32.w):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsub_vwvw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubwsat(vu, vv) +} + +/// `Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vsubwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vsub_wwww_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubwsat_dv(vuu, vvv) +} + +/// `Vdd32.h=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpy_wbrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyb(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpyacc_whwbrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpy_wubrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpybus(vuu, rt) +} + +/// `Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpybus_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vtmpyacc_whwubrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpybus_acc(vxx, vuu, rt) +} + +/// `Vdd32.w=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vtmpy_whrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vtmpyhb(vuu, rt) +} + +/// `Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vtmpyhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vtmpyacc_wwwhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vtmpyhb_acc(vxx, vuu, rt) +} + +/// `Vdd32.h=vunpack(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vunpack_vb(vu: HvxVector) -> HvxVectorPair { + vunpackb(vu) +} + +/// `Vdd32.w=vunpack(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vunpack_vh(vu: HvxVector) -> HvxVectorPair { + vunpackh(vu) +} + +/// `Vxx32.h|=vunpacko(Vu32.b)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackob))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vunpackoor_whvb(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackob(vxx, vu) +} + +/// `Vxx32.w|=vunpacko(Vu32.h)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackoh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vunpackoor_wwvh(vxx: HvxVectorPair, vu: HvxVector) -> HvxVectorPair { + vunpackoh(vxx, vu) +} + +/// `Vdd32.uh=vunpack(Vu32.ub)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vunpack_vub(vu: HvxVector) -> HvxVectorPair { + vunpackub(vu) +} + +/// `Vdd32.uw=vunpack(Vu32.uh)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vunpackuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vunpack_vuh(vu: HvxVector) -> HvxVectorPair { + vunpackuh(vu) +} + +/// `Vd32=vxor(Vu32,Vv32)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vxor))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vxor_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + simd_xor(vu, vv) +} + +/// `Vdd32.uh=vzxt(Vu32.ub)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuh_vzxt_vub(vu: HvxVector) -> HvxVectorPair { + vzb(vu) +} + +/// `Vdd32.uw=vzxt(Vu32.uh)` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[cfg_attr(test, assert_instr(vzh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vzxt_vuh(vu: HvxVector) -> HvxVectorPair { + vzh(vu) +} + +/// `Vd32.b=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplatb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsplat_r(rt: i32) -> HvxVector { + lvsplatb(rt) +} + +/// `Vd32.h=vsplat(Rt32)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(lvsplath))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vsplat_r(rt: i32) -> HvxVector { + lvsplath(rt) +} + +/// `Vd32.b=vadd(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vadd_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddbsat(vu, vv) +} + +/// `Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vadd_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vaddbsat_dv(vuu, vvv) +} + +/// `Vd32.h=vadd(vclb(Vu32.h),Vv32.h)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vadd_vclb_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbh(vu, vv) +} + +/// `Vd32.w=vadd(vclb(Vu32.w),Vv32.w)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddclbw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vclb_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddclbw(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.h,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vaddacc_wwvhvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddhw_acc(vxx, vu, vv) +} + +/// `Vxx32.h+=vadd(Vu32.ub,Vv32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddubh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vaddacc_whvubvub( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vaddubh_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vadd(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vaddububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vadd_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vaddububb_sat(vu, vv) +} + +/// `Vxx32.w+=vadd(Vu32.uh,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduhw_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vaddacc_wwvuhvuh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vadduhw_acc(vxx, vu, vv) +} + +/// `Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vadd_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadduwsat(vu, vv) +} + +/// `Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vadduwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vadd_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vadduwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrhbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vasr_vhvhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrhbsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasruwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vuwvuwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhrndsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vasrwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vwvwr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasrwuhrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vlsr(Vu32.ub,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlsrb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vlsr_vubr(vu: HvxVector, rt: i32) -> HvxVector { + vlsrb(vu, rt) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vlutvvb_nm(vu, vv, rt) +} + +/// `Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvb_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32or_vbvbvbi( + vx: HvxVector, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVector { + vlutvvb_oracci(vx, vu, vv, iu3) +} + +/// `Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)` +/// +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvvbi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vlut32_vbvbi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVector { + vlutvvbi(vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_nm))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhr_nomatch(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVectorPair { + vlutvwh_nm(vu, vv, rt) +} + +/// `Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwh_oracci))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16or_whvbvhi( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, + iu3: i32, +) -> HvxVectorPair { + vlutvwh_oracci(vxx, vu, vv, iu3) +} + +/// `Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vlutvwhi))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vlut16_vbvhi(vu: HvxVector, vv: HvxVector, iu3: i32) -> HvxVectorPair { + vlutvwhi(vu, vv, iu3) +} + +/// `Vd32.b=vmax(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmaxb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vmax_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmaxb(vu, vv) +} + +/// `Vd32.b=vmin(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vminb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vmin_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vminb(vu, vv) +} + +/// `Vdd32.w=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpa_wuhrb(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpauhb(vuu, rt) +} + +/// `Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpauhb_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpaacc_wwwuhrb( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpauhb_acc(vxx, vuu, rt) +} + +/// `Vdd32=vmpye(Vu32.w,Vv32.uh)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyewuh_64))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vmpye_vwvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpyewuh_64(vu, vv) +} + +/// `Vd32.w=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyi_vwrub(vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub(vu, rt) +} + +/// `Vx32.w+=vmpyi(Vu32.w,Rt32.ub)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyiwub_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vmpyiacc_vwvwrub(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyiwub_acc(vx, vu, rt) +} + +/// `Vxx32+=vmpyo(Vu32.w,Vv32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vmpyowh_64_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vmpyoacc_wvwvh( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpyowh_64_acc(vxx, vu, vv) +} + +/// `Vd32.ub=vround(Vu32.uh,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduhub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vround_vuhvuh_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduhub(vu, vv) +} + +/// `Vd32.uh=vround(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vrounduwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vround_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrounduwuh(vu, vv) +} + +/// `Vd32.uh=vsat(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsatuwuh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vsat_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatuwuh(vu, vv) +} + +/// `Vd32.b=vsub(Vu32.b,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vsub_vbvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubbsat(vu, vv) +} + +/// `Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubbsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wb_vsub_wbwb_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubbsat_dv(vuu, vvv) +} + +/// `Vd32.ub=vsub(Vu32.ub,Vv32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubububb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vsub_vubvb_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubububb_sat(vu, vv) +} + +/// `Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vsub_vuwvuw_sat(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsubuwsat(vu, vv) +} + +/// `Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat` +/// +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[cfg_attr(test, assert_instr(vsubuwsat_dv))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wuw_vsub_wuwwuw_sat(vuu: HvxVectorPair, vvv: HvxVectorPair) -> HvxVectorPair { + vsubuwsat_dv(vuu, vvv) +} + +/// `Vd32.b=vabs(Vu32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vabs_vb(vu: HvxVector) -> HvxVector { + vabsb(vu) +} + +/// `Vd32.b=vabs(Vu32.b):sat` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vabsb_sat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vabs_vb_sat(vu: HvxVector) -> HvxVector { + vabsb_sat(vu) +} + +/// `Vx32.h+=vasl(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vaslh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vaslacc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vaslh_acc(vx, vu, rt) +} + +/// `Vx32.h+=vasr(Vu32.h,Rt32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasrh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vasracc_vhvhr(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vasrh_acc(vx, vu, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vuhvuhr_rnd_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubrndsat(vu, vv, rt) +} + +/// `Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_vuhvuhr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruhubsat(vu, vv, rt) +} + +/// `Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vasruwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_vuwvuwr_sat(vu: HvxVector, vv: HvxVector, rt: i32) -> HvxVector { + vasruwuhsat(vu, vv, rt) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgb(vu, vv) +} + +/// `Vd32.b=vavg(Vu32.b,Vv32.b):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavgbrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vavg_vbvb_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavgbrnd(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vavg_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguw(vu, vv) +} + +/// `Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vavguwrnd))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vavg_vuwvuw_rnd(vu: HvxVector, vv: HvxVector) -> HvxVector { + vavguwrnd(vu, vv) +} + +/// `Vdd32=#0` +/// +/// Instruction Type: MAPPING +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vdd0))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vzero() -> HvxVectorPair { + vdd0() +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armvh(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermh(rs, rt, mu, vv) +} + +/// `vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armww(rs: *mut HvxVector, rt: i32, mu: i32, vvv: HvxVectorPair) { + vgathermhw(rs, rt, mu, vvv) +} + +/// `vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vgathermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_armvw(rs: *mut HvxVector, rt: i32, mu: i32, vv: HvxVector) { + vgathermw(rs, rt, mu, vv) +} + +/// `Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpa_wubrub(vuu: HvxVectorPair, rt: i32) -> HvxVectorPair { + vmpabuu(vuu, rt) +} + +/// `Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpabuu_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wh_vmpaacc_whwubrub( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + rt: i32, +) -> HvxVectorPair { + vmpabuu_acc(vxx, vuu, rt) +} + +/// `Vxx32.w+=vmpy(Vu32.h,Rt32.h)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyh_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vmpyacc_wwvhrh(vxx: HvxVectorPair, vu: HvxVector, rt: i32) -> HvxVectorPair { + vmpyh_acc(vxx, vu, rt) +} + +/// `Vd32.uw=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vmpye_vuhruh(vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe(vu, rt) +} + +/// `Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vmpyuhe_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vmpyeacc_vuwvuhruh(vx: HvxVector, vu: HvxVector, rt: i32) -> HvxVector { + vmpyuhe_acc(vx, vu, rt) +} + +/// `Vd32.b=vnavg(Vu32.b,Vv32.b)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vnavgb))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vnavg_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVector { + vnavgb(vu, vv) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.h).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermh_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmvhv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermh_add(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32` +/// +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermhw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmwwv(rt: i32, mu: i32, vvv: HvxVectorPair, vw: HvxVector) { + vscattermhw_add(rt, mu, vvv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw(rt, mu, vv, vw) +} + +/// `vscatter(Rt32,Mu2,Vv32.w).w+=Vw32` +/// +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[cfg_attr(test, assert_instr(vscattermw_add))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatteracc_rmvwv(rt: i32, mu: i32, vv: HvxVector, vw: HvxVector) { + vscattermw_add(rt, mu, vv, vw) +} + +/// `Vxx32.w=vasrinto(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VP_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vasr_into))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_vasrinto_wwvwvw( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vasr_into(vxx, vu, vv) +} + +/// `Vd32.uw=vrotr(Vu32.uw,Vv32.uw)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vrotr))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuw_vrotr_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vrotr(vu, vv) +} + +/// `Vd32.w=vsatdw(Vu32.w,Vv32.w)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[cfg_attr(test, assert_instr(vsatdw))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vsatdw_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsatdw(vu, vv) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpy_wubwbi_h( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyhubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_h( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyhubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpy_wubwbi_v( + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10(vuu, vvv, iu2) +} + +/// `Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(v6mpyvubs10_vxx))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_ww_v6mpyacc_wwwubwbi_v( + vxx: HvxVectorPair, + vuu: HvxVectorPair, + vvv: HvxVectorPair, + iu2: i32, +) -> HvxVectorPair { + v6mpyvubs10_vxx(vxx, vuu, vvv, iu2) +} + +/// `Vd32.hf=vabs(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vabs_vhf(vu: HvxVector) -> HvxVector { + vabs_hf(vu) +} + +/// `Vd32.sf=vabs(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vabs_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vabs_vsf(vu: HvxVector) -> HvxVector { + vabs_sf(vu) +} + +/// `Vd32.qf16=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf(vu, vv) +} + +/// `Vd32.hf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16(vu, vv) +} + +/// `Vd32.qf16=vadd(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vadd_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf(vu, vv) +} + +/// `Vdd32.sf=vadd(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vadd_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vadd_sf_hf(vu, vv) +} + +/// `Vd32.sf=vadd(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vadd_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vadd_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vadd_sf_sf(vu, vv) +} + +/// `Vd32.w=vfmv(Vu32.w)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vassign_fp))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vfmv_vw(vu: HvxVector) -> HvxVector { + vassign_fp(vu) +} + +/// `Vd32.hf=Vu32.qf16` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_vqf16(vu: HvxVector) -> HvxVector { + vconv_hf_qf16(vu) +} + +/// `Vd32.hf=Vuu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_hf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_wqf32(vuu: HvxVectorPair) -> HvxVector { + vconv_hf_qf32(vuu) +} + +/// `Vd32.sf=Vu32.qf32` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vconv_sf_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_equals_vqf32(vu: HvxVector) -> HvxVector { + vconv_sf_qf32(vu) +} + +/// `Vd32.b=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_b_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_b_hf(vu, vv) +} + +/// `Vd32.h=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_vcvt_vhf(vu: HvxVector) -> HvxVector { + vcvt_h_hf(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_vb(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_b(vu) +} + +/// `Vd32.hf=vcvt(Vu32.h)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vh(vu: HvxVector) -> HvxVector { + vcvt_hf_h(vu) +} + +/// `Vd32.hf=vcvt(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_hf_sf(vu, vv) +} + +/// `Vdd32.hf=vcvt(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_vub(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_ub(vu) +} + +/// `Vd32.hf=vcvt(Vu32.uh)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_hf_uh))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vcvt_vuh(vu: HvxVector) -> HvxVector { + vcvt_hf_uh(vu) +} + +/// `Vdd32.sf=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vcvt_vhf(vu: HvxVector) -> HvxVectorPair { + vcvt_sf_hf(vu) +} + +/// `Vd32.ub=vcvt(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_ub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vcvt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vcvt_ub_hf(vu, vv) +} + +/// `Vd32.uh=vcvt(Vu32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vcvt_uh_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vcvt_vhf(vu: HvxVector) -> HvxVector { + vcvt_uh_hf(vu) +} + +/// `Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vdmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf(vu, vv) +} + +/// `Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vdmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vdmpyacc_vsfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vdmpy_sf_hf_acc(vx, vu, vv) +} + +/// `Vd32.hf=vfmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_hf(vu, vv) +} + +/// `Vd32.sf=vfmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_sf(vu, vv) +} + +/// `Vd32.hf=vfmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_hf(vu, vv) +} + +/// `Vd32.sf=vfmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_sf(vu, vv) +} + +/// `Vd32.hf=vfneg(Vu32.hf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vfneg_vhf(vu: HvxVector) -> HvxVector { + vfneg_hf(vu) +} + +/// `Vd32.sf=vfneg(Vu32.sf)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vfneg_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vfneg_vsf(vu: HvxVector) -> HvxVector { + vfneg_sf(vu) +} + +/// `Vd32.hf=vmax(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmax_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_hf(vu, vv) +} + +/// `Vd32.sf=vmax(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmax_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmax_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmax_sf(vu, vv) +} + +/// `Vd32.hf=vmin(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmin_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_hf(vu, vv) +} + +/// `Vd32.sf=vmin(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmin_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmin_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmin_sf(vu, vv) +} + +/// `Vd32.hf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf(vu, vv) +} + +/// `Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_hf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vmpyacc_vhfvhfvhf(vx: HvxVector, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_hf_hf_acc(vx, vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_hf(vu, vv) +} + +/// `Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf16_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf16_mix_hf(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vmpy_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_mix_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_mix_hf(vu, vv) +} + +/// `Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wqf32_vmpy_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_qf32_qf16(vu, vv) +} + +/// `Vd32.qf32=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_qf32_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_qf32_sf(vu, vv) +} + +/// `Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vmpy_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vmpy_sf_hf(vu, vv) +} + +/// `Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_hf_acc))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vmpyacc_wsfvhfvhf( + vxx: HvxVectorPair, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPair { + vmpy_sf_hf_acc(vxx, vu, vv) +} + +/// `Vd32.sf=vmpy(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vmpy_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vmpy_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpy_sf_sf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf(vu, vv) +} + +/// `Vd32.hf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_hf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_hf_hf(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vqf16vqf16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16(vu, vv) +} + +/// `Vd32.qf16=vsub(Vu32.qf16,Vv32.hf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf16_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf16_vsub_vqf16vhf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf16_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vqf32vqf32(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.qf32,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_qf32_mix))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vqf32vsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_qf32_mix(vu, vv) +} + +/// `Vd32.qf32=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vqf32_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf(vu, vv) +} + +/// `Vdd32.sf=vsub(Vu32.hf,Vv32.hf)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_wsf_vsub_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vsub_sf_hf(vu, vv) +} + +/// `Vd32.sf=vsub(Vu32.sf,Vv32.sf)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[cfg_attr(test, assert_instr(vsub_sf_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_vsub_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVector { + vsub_sf_sf(vu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_wuhvub_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubrndsat(vuu, vv) +} + +/// `Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvuhubsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vub_vasr_wuhvub_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvuhubsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhrndsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_wwvuh_rnd_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhrndsat(vuu, vv) +} + +/// `Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vasrvwuhsat))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vasr_wwvuh_sat(vuu: HvxVectorPair, vv: HvxVector) -> HvxVector { + vasrvwuhsat(vuu, vv) +} + +/// `Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv69"))] +#[cfg_attr(test, assert_instr(vmpyuhvs))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vuh_vmpy_vuhvuh_rs16(vu: HvxVector, vv: HvxVector) -> HvxVector { + vmpyuhvs(vu, vv) +} + +/// `Vd32.h=Vu32.hf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_h_hf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_equals_vhf(vu: HvxVector) -> HvxVector { + vconv_h_hf(vu) +} + +/// `Vd32.hf=Vu32.h` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_hf_h))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vhf_equals_vh(vu: HvxVector) -> HvxVector { + vconv_hf_h(vu) +} + +/// `Vd32.sf=Vu32.w` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_sf_w))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vsf_equals_vw(vu: HvxVector) -> HvxVector { + vconv_sf_w(vu) +} + +/// `Vd32.w=Vu32.sf` +/// +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv73"))] +#[cfg_attr(test, assert_instr(vconv_w_sf))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_equals_vsf(vu: HvxVector) -> HvxVector { + vconv_w_sf(vu) +} + +/// `Vd32=vgetqfext(Vu32.x,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(get_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vgetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { + get_qfext(vu, rt) +} + +/// `Vd32.x=vsetqfext(Vu32,Rt32)` +/// +/// Instruction Type: CVI_VX +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(set_qfext))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vsetqfext_vr(vu: HvxVector, rt: i32) -> HvxVector { + set_qfext(vu, rt) +} + +/// `Vd32.f8=vabs(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vabs_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vabs_v(vu: HvxVector) -> HvxVector { + vabs_f8(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.b)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_b))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt2_vb(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_b(vu) +} + +/// `Vdd32.hf=vcvt2(Vu32.ub)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt2_hf_ub))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt2_vub(vu: HvxVector) -> HvxVectorPair { + vcvt2_hf_ub(vu) +} + +/// `Vdd32.hf=vcvt(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_DV +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vcvt_hf_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_whf_vcvt_v(vu: HvxVector) -> HvxVectorPair { + vcvt_hf_f8(vu) +} + +/// `Vd32.f8=vfmax(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmax_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfmax_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmax_f8(vu, vv) +} + +/// `Vd32.f8=vfmin(Vu32.f8,Vv32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfmin_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfmin_vv(vu: HvxVector, vv: HvxVector) -> HvxVector { + vfmin_f8(vu, vv) +} + +/// `Vd32.f8=vfneg(Vu32.f8)` +/// +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv79"))] +#[cfg_attr(test, assert_instr(vfneg_f8))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vfneg_v(vu: HvxVector) -> HvxVector { + vfneg_f8(vu) +} + +/// `Qd4=and(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_and_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=and(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_and_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_and_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=not(Qs4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_not_q(qs: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_not(vandvrt( + core::mem::transmute::(qs), + -1, + )), + -1, + )) +} + +/// `Qd4=or(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_or_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=or(Qs4,!Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_or_qqn(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_or_n( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4=vsetq(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vsetq_r(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2(rt), -1)) +} + +/// `Qd4=xor(Qs4,Qt4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_xor_qq(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + pred_xor( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `if (!Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qnriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qnriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_nqpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4):nt=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qriv_nt(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_nt_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (Qv4) vmem(Rt32+#s4)=Vs32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VM_ST +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vmem_qriv(qv: HvxVectorPred, rt: *mut HvxVector, vs: HvxVector) { + vS32b_qpred_ai( + vandvrt(core::mem::transmute::(qv), -1), + rt, + vs, + ) +} + +/// `if (!Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condacc_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b+=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condacc_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condacc_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h+=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condacc_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condacc_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w+=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condacc_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vaddwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vd32=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qr(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt(core::mem::transmute::(qu), rt) +} + +/// `Vx32|=vand(Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vandor_vqr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandvrt_acc(vx, core::mem::transmute::(qu), rt) +} + +/// `Qd4=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vand_vr(vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vu, rt)) +} + +/// `Qx4|=vand(Vu32,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vandor_qvr(qx: HvxVectorPred, vu: HvxVector, rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt_acc( + core::mem::transmute::(qx), + vu, + rt, + )) +} + +/// `Qd4=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eq_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(veqw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqand_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqor_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.eq(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_eqxacc_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + veqw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vbvb(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtb(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.b,Vv32.b)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvbvb( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtb_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vhvh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgth(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.h,Vv32.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvhvh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgth_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vubvub(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtub(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvubvub( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtub_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vuhvuh(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuh(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvuhvuh( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuh_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vuwvuw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtuw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvuwvuw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtuw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vwvw(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtw(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.w,Vv32.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvwvw( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtw_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Vd32=vmux(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vmux_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVector { + vmux( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `if (!Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condnac_qnvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.b-=Vu32.b` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_condnac_qvbvb(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubbq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condnac_qnvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.h-=Vu32.h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_condnac_qvhvh(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubhq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (!Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condnac_qnvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwnq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `if (Qv4) Vx32.w-=Vu32.w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_condnac_qvwvw(qv: HvxVectorPred, vx: HvxVector, vu: HvxVector) -> HvxVector { + vsubwq( + vandvrt(core::mem::transmute::(qv), -1), + vx, + vu, + ) +} + +/// `Vdd32=vswap(Qt4,Vu32,Vv32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv60"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_w_vswap_qvv(qt: HvxVectorPred, vu: HvxVector, vv: HvxVector) -> HvxVectorPair { + vswap( + vandvrt(core::mem::transmute::(qt), -1), + vu, + vv, + ) +} + +/// `Qd4=vsetq2(Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VP +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vsetq2_r(rt: i32) -> HvxVectorPred { + core::mem::transmute::(vandqrt(pred_scalar2v2(rt), -1)) +} + +/// `Qd4.b=vshuffe(Qs4.h,Qt4.h)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_qb_vshuffe_qhqh(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqh( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Qd4.h=vshuffe(Qs4.w,Qt4.w)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA_DV +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_qh_vshuffe_qwqw(qs: HvxVectorPred, qt: HvxVectorPred) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + shuffeqw( + vandvrt(core::mem::transmute::(qs), -1), + vandvrt(core::mem::transmute::(qt), -1), + ), + -1, + )) +} + +/// `Vd32=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qnr(qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt( + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vx32|=vand(!Qu4,Rt32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VX_LATE +/// Execution Slots: SLOT23 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vandor_vqnr(vx: HvxVector, qu: HvxVectorPred, rt: i32) -> HvxVector { + vandnqrt_acc( + vx, + vandvrt(core::mem::transmute::(qu), -1), + rt, + ) +} + +/// `Vd32=vand(!Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qnv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvnqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `Vd32=vand(Qv4,Vu32)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv62"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_v_vand_qv(qv: HvxVectorPred, vu: HvxVector) -> HvxVector { + vandvqv( + vandvrt(core::mem::transmute::(qv), -1), + vu, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmvh( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermhq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER_DV +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmww( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, +) { + vgathermhwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + ) +} + +/// `if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_GATHER +/// Execution Slots: SLOT01 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vgather_aqrmvw( + rs: *mut HvxVector, + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, +) { + vgathermwq( + rs, + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + ) +} + +/// `Vd32.b=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vb_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqb(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.h=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vh_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqh(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `Vd32.w=prefixsum(Qv4)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VS +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_prefixsum_q(qv: HvxVectorPred) -> HvxVector { + vprefixqw(vandvrt( + core::mem::transmute::(qv), + -1, + )) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmvhv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermhq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER_DV +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmwwv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vvv: HvxVectorPair, + vw: HvxVector, +) { + vscattermhwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vvv, + vw, + ) +} + +/// `if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_SCATTER +/// Execution Slots: SLOT0 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv65"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vscatter_qrmvwv( + qs: HvxVectorPred, + rt: i32, + mu: i32, + vv: HvxVector, + vw: HvxVector, +) { + vscattermwq( + vandvrt(core::mem::transmute::(qs), -1), + rt, + mu, + vv, + vw, + ) +} + +/// `Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv66"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_vw_vadd_vwvwq_carry_sat( + vu: HvxVector, + vv: HvxVector, + qs: HvxVectorPred, +) -> HvxVector { + vaddcarrysat( + vu, + vv, + vandvrt(core::mem::transmute::(qs), -1), + ) +} + +/// `Qd4=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vhfvhf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgthf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.hf,Vv32.hf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvhfvhf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgthf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qd4=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gt_vsfvsf(vu: HvxVector, vv: HvxVector) -> HvxVectorPred { + core::mem::transmute::(vandqrt(vgtsf(vu, vv), -1)) +} + +/// `Qx4&=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtand_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_and( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4|=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtor_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_or( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} + +/// `Qx4^=vcmp.gt(Vu32.sf,Vv32.sf)` +/// +/// This is a compound operation composed of multiple HVX instructions. +/// Instruction Type: CVI_VA +/// Execution Slots: SLOT0123 +#[inline(always)] +#[cfg_attr(target_arch = "hexagon", target_feature(enable = "hvxv68"))] +#[unstable(feature = "stdarch_hexagon", issue = "151523")] +pub unsafe fn q6_q_vcmp_gtxacc_qvsfvsf( + qx: HvxVectorPred, + vu: HvxVector, + vv: HvxVector, +) -> HvxVectorPred { + core::mem::transmute::(vandqrt( + vgtsf_xor( + vandvrt(core::mem::transmute::(qx), -1), + vu, + vv, + ), + -1, + )) +} diff --git a/stdarch/crates/core_arch/src/lib.rs b/stdarch/crates/core_arch/src/lib.rs index 039a4c4411f2e..8a1bead7c4791 100644 --- a/stdarch/crates/core_arch/src/lib.rs +++ b/stdarch/crates/core_arch/src/lib.rs @@ -23,6 +23,7 @@ mips_target_feature, powerpc_target_feature, loongarch_target_feature, + hexagon_target_feature, wasm_target_feature, abi_unadjusted, rtm_target_feature, diff --git a/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs b/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs index cda0ebec67799..1d9d4e8248e63 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs @@ -7,7 +7,7 @@ // ``` use crate::mem::transmute; -use super::types::*; +use super::super::*; #[allow(improper_ctypes)] unsafe extern "unadjusted" { @@ -980,7 +980,7 @@ unsafe extern "unadjusted" { #[link_name = "llvm.loongarch.lasx.xvssrln.w.d"] fn __lasx_xvssrln_w_d(a: __v4i64, b: __v4i64) -> __v8i32; #[link_name = "llvm.loongarch.lasx.xvorn.v"] - fn __lasx_xvorn_v(a: __v32i8, b: __v32i8) -> __v32i8; + fn __lasx_xvorn_v(a: __v32u8, b: __v32u8) -> __v32u8; #[link_name = "llvm.loongarch.lasx.xvldi"] fn __lasx_xvldi(a: i32) -> __v4i64; #[link_name = "llvm.loongarch.lasx.xvldx"] @@ -1491,6 +1491,42 @@ unsafe extern "unadjusted" { fn __lasx_xvrepli_h(a: i32) -> __v16i16; #[link_name = "llvm.loongarch.lasx.xvrepli.w"] fn __lasx_xvrepli_w(a: i32) -> __v8i32; + #[link_name = "llvm.loongarch.lasx.cast.128.s"] + fn __lasx_cast_128_s(a: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.cast.128.d"] + fn __lasx_cast_128_d(a: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.cast.128"] + fn __lasx_cast_128(a: __v2i64) -> __v4i64; + #[link_name = "llvm.loongarch.lasx.concat.128.s"] + fn __lasx_concat_128_s(a: __v4f32, b: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.concat.128.d"] + fn __lasx_concat_128_d(a: __v2f64, b: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.concat.128"] + fn __lasx_concat_128(a: __v2i64, b: __v2i64) -> __v4i64; + #[link_name = "llvm.loongarch.lasx.extract.128.lo.s"] + fn __lasx_extract_128_lo_s(a: __v8f32) -> __v4f32; + #[link_name = "llvm.loongarch.lasx.extract.128.hi.s"] + fn __lasx_extract_128_hi_s(a: __v8f32) -> __v4f32; + #[link_name = "llvm.loongarch.lasx.extract.128.lo.d"] + fn __lasx_extract_128_lo_d(a: __v4f64) -> __v2f64; + #[link_name = "llvm.loongarch.lasx.extract.128.hi.d"] + fn __lasx_extract_128_hi_d(a: __v4f64) -> __v2f64; + #[link_name = "llvm.loongarch.lasx.extract.128.lo"] + fn __lasx_extract_128_lo(a: __v4i64) -> __v2i64; + #[link_name = "llvm.loongarch.lasx.extract.128.hi"] + fn __lasx_extract_128_hi(a: __v4i64) -> __v2i64; + #[link_name = "llvm.loongarch.lasx.insert.128.lo.s"] + fn __lasx_insert_128_lo_s(a: __v8f32, b: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.insert.128.hi.s"] + fn __lasx_insert_128_hi_s(a: __v8f32, b: __v4f32) -> __v8f32; + #[link_name = "llvm.loongarch.lasx.insert.128.lo.d"] + fn __lasx_insert_128_lo_d(a: __v4f64, b: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.insert.128.hi.d"] + fn __lasx_insert_128_hi_d(a: __v4f64, b: __v2f64) -> __v4f64; + #[link_name = "llvm.loongarch.lasx.insert.128.lo"] + fn __lasx_insert_128_lo(a: __v4i64, b: __v2i64) -> __v4i64; + #[link_name = "llvm.loongarch.lasx.insert.128.hi"] + fn __lasx_insert_128_hi(a: __v4i64, b: __v2i64) -> __v4i64; } #[inline] @@ -7062,3 +7098,129 @@ pub fn lasx_xvrepli_w() -> m256i { static_assert_simm_bits!(IMM_S10, 10); unsafe { transmute(__lasx_xvrepli_w(IMM_S10)) } } + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_cast_128_s(a: m128) -> m256 { + unsafe { transmute(__lasx_cast_128_s(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_cast_128_d(a: m128d) -> m256d { + unsafe { transmute(__lasx_cast_128_d(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_cast_128(a: m128i) -> m256i { + unsafe { transmute(__lasx_cast_128(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_concat_128_s(a: m128, b: m128) -> m256 { + unsafe { transmute(__lasx_concat_128_s(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_concat_128_d(a: m128d, b: m128d) -> m256d { + unsafe { transmute(__lasx_concat_128_d(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_concat_128(a: m128i, b: m128i) -> m256i { + unsafe { transmute(__lasx_concat_128(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_lo_s(a: m256) -> m128 { + unsafe { transmute(__lasx_extract_128_lo_s(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_hi_s(a: m256) -> m128 { + unsafe { transmute(__lasx_extract_128_hi_s(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_lo_d(a: m256d) -> m128d { + unsafe { transmute(__lasx_extract_128_lo_d(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_hi_d(a: m256d) -> m128d { + unsafe { transmute(__lasx_extract_128_hi_d(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_lo(a: m256i) -> m128i { + unsafe { transmute(__lasx_extract_128_lo(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_extract_128_hi(a: m256i) -> m128i { + unsafe { transmute(__lasx_extract_128_hi(transmute(a))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_lo_s(a: m256, b: m128) -> m256 { + unsafe { transmute(__lasx_insert_128_lo_s(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_hi_s(a: m256, b: m128) -> m256 { + unsafe { transmute(__lasx_insert_128_hi_s(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_lo_d(a: m256d, b: m128d) -> m256d { + unsafe { transmute(__lasx_insert_128_lo_d(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_hi_d(a: m256d, b: m128d) -> m256d { + unsafe { transmute(__lasx_insert_128_hi_d(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_lo(a: m256i, b: m128i) -> m256i { + unsafe { transmute(__lasx_insert_128_lo(transmute(a), transmute(b))) } +} + +#[inline] +#[target_feature(enable = "lasx")] +#[unstable(feature = "stdarch_loongarch", issue = "117427")] +pub fn lasx_insert_128_hi(a: m256i, b: m128i) -> m256i { + unsafe { transmute(__lasx_insert_128_hi(transmute(a), transmute(b))) } +} diff --git a/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs b/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs index 54771d7b51109..319ce7cf98195 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lasx/tests.rs @@ -14756,3 +14756,284 @@ unsafe fn test_lasx_xvrepli_w() { assert_eq!(r, transmute(lasx_xvrepli_w::<-388>())); } + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_cast_128_s() { + let a = u32x4::new(1031165056, 1051966120, 1060984374, 1062536919); + let r = i64x4::new(4518160082931176576, 4563561318958585398, 1966080, 1966080); + + assert_eq!( + r.as_array()[0..2], + transmute::<_, i64x4>(lasx_cast_128_s(transmute(a))).as_array()[0..2] + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_cast_128_d() { + let a = u64x2::new(4604694967937271251, 4600904075476555984); + let r = i64x4::new( + 4604694967937271251, + 4600904075476555984, + 2910860781861170785, + 8314045306847701346, + ); + + assert_eq!( + r.as_array()[0..2], + transmute::<_, i64x4>(lasx_cast_128_d(transmute(a))).as_array()[0..2] + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_cast_128() { + let a = i64x2::new(-5333716211868108402, 2442107533729495827); + let r = i64x4::new( + -5333716211868108402, + 2442107533729495827, + -1115824375586394527, + 8314045306157170687, + ); + + assert_eq!( + r.as_array()[0..2], + transmute::<_, i64x4>(lasx_cast_128(transmute(a))).as_array()[0..2] + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_concat_128_s() { + let a = u32x4::new(1032255272, 1059413818, 1058434362, 1041454056); + let b = u32x4::new(1047296252, 1059191602, 1051282752, 1026847376); + let r = i64x4::new( + 4550147702272751400, + 4473011111864986938, + 4549193291835144444, + 4410275898954698048, + ); + + assert_eq!(r, transmute(lasx_concat_128_s(transmute(a), transmute(b)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_concat_128_d() { + let a = u64x2::new(4602341404117999960, 4599751584045405722); + let b = u64x2::new(4595947342927040984, 4600308396523102002); + let r = i64x4::new( + 4602341404117999960, + 4599751584045405722, + 4595947342927040984, + 4600308396523102002, + ); + + assert_eq!(r, transmute(lasx_concat_128_d(transmute(a), transmute(b)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_concat_128() { + let a = i64x2::new(3302609705743394573, 8438855426868306143); + let b = i64x2::new(8632034656150002181, 7751541408133090748); + let r = i64x4::new( + 3302609705743394573, + 8438855426868306143, + 8632034656150002181, + 7751541408133090748, + ); + + assert_eq!(r, transmute(lasx_concat_128(transmute(a), transmute(b)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_lo_s() { + let a = u32x8::new( + 1038279272, 1053426270, 1062315532, 1055361088, 1061380448, 1052007748, 1063816577, + 1061671114, + ); + let r = i64x2::new(4524431379435545192, 4532741359493293580); + + assert_eq!(r, transmute(lasx_extract_128_lo_s(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_hi_s() { + let a = u32x8::new( + 1059517342, 1052723820, 1053176244, 1060336354, 1058221022, 1064684502, 1061072013, + 1059238420, + ); + let r = i64x2::new(4572785117706267614, 4549394373627784333); + + assert_eq!(r, transmute(lasx_extract_128_hi_s(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_lo_d() { + let a = u64x4::new( + 4606487981487128637, + 4592443779247846248, + 4605637448543526041, + 4604126872543611047, + ); + let r = i64x2::new(4606487981487128637, 4592443779247846248); + + assert_eq!(r, transmute(lasx_extract_128_lo_d(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_hi_d() { + let a = u64x4::new( + 4595075050683709816, + 4603388454656549851, + 4603881047625519227, + 4604218419306666352, + ); + let r = i64x2::new(4603881047625519227, 4604218419306666352); + + assert_eq!(r, transmute(lasx_extract_128_hi_d(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_lo() { + let a = i64x4::new( + 1690990426210778543, + -1056924033489771427, + 1791197928200737608, + 2648792885519901423, + ); + let r = i64x2::new(1690990426210778543, -1056924033489771427); + + assert_eq!(r, transmute(lasx_extract_128_lo(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_extract_128_hi() { + let a = i64x4::new( + 1400282616691463341, + 6677577875527300174, + -1903780563362068813, + -7449796170151383489, + ); + let r = i64x2::new(-1903780563362068813, -7449796170151383489); + + assert_eq!(r, transmute(lasx_extract_128_hi(transmute(a)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_lo_s() { + let a = u32x8::new( + 1063338913, 1017815328, 1065051130, 1040694156, 1059596680, 1048796526, 1058020845, + 1057822131, + ); + let b = u32x4::new(1052930766, 1021556992, 1050709482, 1059704809); + let r = i64x4::new( + 4387553872693064398, + 4551397499119635946, + 4504546780388010376, + 4543311458688048621, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_lo_s(transmute(a), transmute(b))) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_hi_s() { + let a = u32x8::new( + 1018863744, 1064221149, 1048659080, 1057450774, 1049935896, 1034170664, 1059759433, + 1057849762, + ); + let b = u32x4::new(1060332648, 1063149600, 1051087106, 1060582348); + let r = i64x4::new( + 4570795031685406848, + 4541716492508546184, + 4566192763815814248, + 4555166500425978114, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_hi_s(transmute(a), transmute(b))) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_lo_d() { + let a = u64x4::new( + 4601319519422109044, + 4601506273633970188, + 4605118087882201940, + 4605125059076454256, + ); + let b = u64x2::new(4587489919640425888, 4591909120489567808); + let r = i64x4::new( + 4587489919640425888, + 4591909120489567808, + 4605118087882201940, + 4605125059076454256, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_lo_d(transmute(a), transmute(b))) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_hi_d() { + let a = u64x4::new( + 4604690660177752777, + 4593824994203592700, + 4599958775071728504, + 4604125324674373728, + ); + let b = u64x2::new(4601718173474385938, 4591758028383494760); + let r = i64x4::new( + 4604690660177752777, + 4593824994203592700, + 4601718173474385938, + 4591758028383494760, + ); + + assert_eq!( + r, + transmute(lasx_insert_128_hi_d(transmute(a), transmute(b))) + ); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_lo() { + let a = i64x4::new( + 8159968186698006293, + 5648210958959948409, + 603295919044368378, + -4396186135186039276, + ); + let b = i64x2::new(-6258666140812668387, 5822982556977506382); + let r = i64x4::new( + -6258666140812668387, + 5822982556977506382, + 603295919044368378, + -4396186135186039276, + ); + + assert_eq!(r, transmute(lasx_insert_128_lo(transmute(a), transmute(b)))); +} + +#[simd_test(enable = "lasx")] +unsafe fn test_lasx_insert_128_hi() { + let a = i64x4::new( + 2981835982487038158, + 5258378092714202875, + 5115371338527125146, + -6993491475145500537, + ); + let b = i64x2::new(1176776599938765863, -7502655081590988207); + let r = i64x4::new( + 2981835982487038158, + 5258378092714202875, + 1176776599938765863, + -7502655081590988207, + ); + + assert_eq!(r, transmute(lasx_insert_128_hi(transmute(a), transmute(b)))); +} diff --git a/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs b/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs index 764e69ca05444..25efaadb42880 100644 --- a/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs +++ b/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs @@ -7,7 +7,7 @@ // ``` use crate::mem::transmute; -use super::types::*; +use super::super::*; #[allow(improper_ctypes)] unsafe extern "unadjusted" { @@ -1324,7 +1324,7 @@ unsafe extern "unadjusted" { #[link_name = "llvm.loongarch.lsx.vssrln.w.d"] fn __lsx_vssrln_w_d(a: __v2i64, b: __v2i64) -> __v4i32; #[link_name = "llvm.loongarch.lsx.vorn.v"] - fn __lsx_vorn_v(a: __v16i8, b: __v16i8) -> __v16i8; + fn __lsx_vorn_v(a: __v16u8, b: __v16u8) -> __v16u8; #[link_name = "llvm.loongarch.lsx.vldi"] fn __lsx_vldi(a: i32) -> __v2i64; #[link_name = "llvm.loongarch.lsx.vshuf.b"] diff --git a/stdarch/crates/core_arch/src/macros.rs b/stdarch/crates/core_arch/src/macros.rs index 353829633f018..9f6922efeeb7d 100644 --- a/stdarch/crates/core_arch/src/macros.rs +++ b/stdarch/crates/core_arch/src/macros.rs @@ -186,3 +186,94 @@ macro_rules! simd_masked_store { $crate::intrinsics::simd::simd_masked_store::<_, _, _, { $align }>($mask, $ptr, $default) }; } + +/// The first N even indices `[0, 2, 4, ...]`. +pub(crate) const fn even() -> [u32; N] { + let mut out = [0u32; N]; + let mut i = 0usize; + while i < N { + out[i] = (2 * i) as u32; + i += 1; + } + out +} + +/// The first N odd indices `[1, 3, 5, ...]`. +pub(crate) const fn odd() -> [u32; N] { + let mut out = [0u32; N]; + let mut i = 0usize; + while i < N { + out[i] = (2 * i + 1) as u32; + i += 1; + } + out +} + +/// Multiples of N offset by K `[K, K+N, K+2N, ...]`. +pub(crate) const fn deinterleave_mask() +-> [u32; LANES] { + let mut out = [0u32; LANES]; + let mut i = 0usize; + while i < LANES { + out[i] = (i * N + K) as u32; + i += 1; + } + out +} + +#[allow(unused)] +macro_rules! deinterleaving_load { + ($elem:ty, $lanes:literal, 2, $ptr:expr) => {{ + use $crate::core_arch::macros::deinterleave_mask; + use $crate::core_arch::simd::Simd; + use $crate::{mem::transmute, ptr}; + + type V = Simd<$elem, $lanes>; + type W = Simd<$elem, { $lanes * 2 }>; + + let w: W = ptr::read_unaligned($ptr as *const W); + + let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 2, 0>()); + let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 2, 1>()); + + transmute((v0, v1)) + }}; + + ($elem:ty, $lanes:literal, 3, $ptr:expr) => {{ + use $crate::core_arch::macros::deinterleave_mask; + use $crate::core_arch::simd::Simd; + use $crate::{mem::transmute, ptr}; + + type V = Simd<$elem, $lanes>; + type W = Simd<$elem, { $lanes * 3 }>; + + let w: W = ptr::read_unaligned($ptr as *const W); + + let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 0>()); + let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 1>()); + let v2: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 3, 2>()); + + transmute((v0, v1, v2)) + }}; + + ($elem:ty, $lanes:literal, 4, $ptr:expr) => {{ + use $crate::core_arch::macros::deinterleave_mask; + use $crate::core_arch::simd::Simd; + use $crate::{mem::transmute, ptr}; + + type V = Simd<$elem, $lanes>; + type W = Simd<$elem, { $lanes * 4 }>; + + let w: W = ptr::read_unaligned($ptr as *const W); + + let v0: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 0>()); + let v1: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 1>()); + let v2: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 2>()); + let v3: V = simd_shuffle!(w, w, deinterleave_mask::<$lanes, 4, 3>()); + + transmute((v0, v1, v2, v3)) + }}; +} + +#[allow(unused)] +pub(crate) use deinterleaving_load; diff --git a/stdarch/crates/core_arch/src/mod.rs b/stdarch/crates/core_arch/src/mod.rs index 3577175ae31c7..2483d07b230f9 100644 --- a/stdarch/crates/core_arch/src/mod.rs +++ b/stdarch/crates/core_arch/src/mod.rs @@ -320,6 +320,19 @@ pub mod arch { pub mod s390x { pub use crate::core_arch::s390x::*; } + + /// Platform-specific intrinsics for the `hexagon` platform. + /// + /// This module provides intrinsics for the Qualcomm Hexagon DSP architecture, + /// including the Hexagon Vector Extensions (HVX). + /// + /// See the [module documentation](../index.html) for more details. + #[cfg(any(target_arch = "hexagon", doc))] + #[doc(cfg(target_arch = "hexagon"))] + #[unstable(feature = "stdarch_hexagon", issue = "151523")] + pub mod hexagon { + pub use crate::core_arch::hexagon::*; + } } #[cfg(any(target_arch = "x86", target_arch = "x86_64", doc))] @@ -379,3 +392,7 @@ mod loongarch64; #[cfg(any(target_arch = "s390x", doc))] #[doc(cfg(target_arch = "s390x"))] mod s390x; + +#[cfg(any(target_arch = "hexagon", doc))] +#[doc(cfg(target_arch = "hexagon"))] +mod hexagon; diff --git a/stdarch/crates/core_arch/src/powerpc/altivec.rs b/stdarch/crates/core_arch/src/powerpc/altivec.rs index fb1a9d8ed9e2c..f68121ad31716 100644 --- a/stdarch/crates/core_arch/src/powerpc/altivec.rs +++ b/stdarch/crates/core_arch/src/powerpc/altivec.rs @@ -47,6 +47,54 @@ types! { pub struct vector_float(4 x f32); } +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_char { + #[inline] + fn from(value: m8x16) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m8x16 { + #[inline] + fn from(value: vector_bool_char) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_short { + #[inline] + fn from(value: m16x8) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m16x8 { + #[inline] + fn from(value: vector_bool_short) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_int { + #[inline] + fn from(value: m32x4) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m32x4 { + #[inline] + fn from(value: vector_bool_int) -> Self { + unsafe { transmute(value) } + } +} + #[allow(improper_ctypes)] unsafe extern "C" { #[link_name = "llvm.ppc.altivec.lvx"] @@ -129,8 +177,6 @@ unsafe extern "C" { b: vector_signed_short, c: vector_signed_int, ) -> vector_signed_int; - #[link_name = "llvm.ppc.altivec.vnmsubfp"] - fn vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float; #[link_name = "llvm.ppc.altivec.vsum2sws"] fn vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int; #[link_name = "llvm.ppc.altivec.vsum4ubs"] @@ -1881,9 +1927,9 @@ mod sealed { #[inline] #[target_feature(enable = "altivec")] - #[cfg_attr(test, assert_instr(vnmsubfp))] - unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float { - vnmsubfp(a, b, c) + #[cfg_attr(test, assert_instr(xvnmsubasp))] + pub unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float { + simd_neg(simd_fma(a, b, simd_neg(c))) } #[inline] @@ -3249,7 +3295,7 @@ mod sealed { unsafe fn vec_round(self) -> Self; } - test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, xvrspic] } + test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, vrfin] } #[unstable(feature = "stdarch_powerpc", issue = "111145")] impl VectorRound for vector_float { @@ -4281,7 +4327,7 @@ pub unsafe fn vec_madd(a: vector_float, b: vector_float, c: vector_float) -> vec #[target_feature(enable = "altivec")] #[unstable(feature = "stdarch_powerpc", issue = "111145")] pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> vector_float { - vnmsubfp(a, b, c) + sealed::vec_vnmsubfp(a, b, c) } /// Vector Select @@ -4653,22 +4699,22 @@ mod tests { }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); + let b: s_t_l!($ty) = $ty::new($($b),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a, b)); + let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!(d, r); } }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); + let b: s_t_l!($ty) = $ty::new($($b),+).into(); - let r : $ty_out = transmute($fn(a, b)); + let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!($d, r); } } @@ -4677,11 +4723,11 @@ mod tests { macro_rules! test_vec_1 { { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: vector_float = transmute(f32x4::new($($a),+)); + fn $name() { + let a = vector_float::from(f32x4::new($($a),+)); - let d: vector_float = transmute(f32x4::new($($d),+)); - let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON))); + let d = vector_float::from(f32x4::new($($d),+)); + let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)) }); let e = m32x4::new(true, true, true, true); assert_eq!(e, r); } @@ -4691,18 +4737,18 @@ mod tests { }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a)); + let r = $ty_out::from(unsafe { $fn(a) }); assert_eq!(d, r); } } } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ld() { + fn test_vec_ld() { let pat = [ u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), u8x16::new( @@ -4711,14 +4757,14 @@ mod tests { ]; for off in 0..16 { - let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) ); } for off in 16..32 { - let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new( @@ -4729,7 +4775,7 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_xl() { + fn test_vec_xl() { let pat = [ u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), u8x16::new( @@ -4738,7 +4784,7 @@ mod tests { ]; for off in 0..16 { - let val: u8x16 = transmute(vec_xl(0, (pat.as_ptr() as *const u8).offset(off))); + let val = u8x16::from(unsafe { vec_xl(0, (pat.as_ptr() as *const u8).offset(off)) }); for i in 0..16 { let v = val.extract_dyn(i); assert_eq!(off as usize + i, v as usize); @@ -4747,14 +4793,16 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_xst() { - let v: vector_unsigned_char = transmute(u8x16::new( + fn test_vec_xst() { + let v = vector_unsigned_char::from(u8x16::new( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, )); for off in 0..16 { let mut buf = [0u8; 32]; - vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off)); + unsafe { + vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off)); + } for i in 0..16 { assert_eq!(i as u8, buf[off as usize..][i]); } @@ -4762,7 +4810,7 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ldl() { + fn test_vec_ldl() { let pat = [ u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), u8x16::new( @@ -4771,14 +4819,14 @@ mod tests { ]; for off in 0..16 { - let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) ); } for off in 16..32 { - let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off))); + let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) }); assert_eq!( v, u8x16::new( @@ -4789,30 +4837,30 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_lde_u8() { + fn test_vec_lde_u8() { let pat = [u8x16::new( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, )]; for off in 0..16 { - let v: u8x16 = transmute(vec_lde(off, pat.as_ptr() as *const u8)); + let v = u8x16::from(unsafe { vec_lde(off, pat.as_ptr() as *const u8) }); assert_eq!(off as u8, v.extract_dyn(off as _)); } } #[simd_test(enable = "altivec")] - unsafe fn test_vec_lde_u16() { + fn test_vec_lde_u16() { let pat = [u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)]; for off in 0..8 { - let v: u16x8 = transmute(vec_lde(off * 2, pat.as_ptr() as *const u16)); + let v = u16x8::from(unsafe { vec_lde(off * 2, pat.as_ptr() as *const u16) }); assert_eq!(off as u16, v.extract_dyn(off as _)); } } #[simd_test(enable = "altivec")] - unsafe fn test_vec_lde_u32() { + fn test_vec_lde_u32() { let pat = [u32x4::new(0, 1, 2, 3)]; for off in 0..4 { - let v: u32x4 = transmute(vec_lde(off * 4, pat.as_ptr() as *const u32)); + let v = u32x4::from(unsafe { vec_lde(off * 4, pat.as_ptr() as *const u32) }); assert_eq!(off as u32, v.extract_dyn(off as _)); } } @@ -5818,9 +5866,9 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_cmpb() { - let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9)); - let b: vector_float = transmute(f32x4::new(-0.1, 0.5, -0.6, 0.9)); + fn test_vec_cmpb() { + let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9)); + let b = vector_float::from(f32x4::new(-0.1, 0.5, -0.6, 0.9)); let d = i32x4::new( -0b10000000000000000000000000000000, 0, @@ -5828,15 +5876,15 @@ mod tests { 0, ); - assert_eq!(d, transmute(vec_cmpb(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_cmpb(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ceil() { - let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9)); + fn test_vec_ceil() { + let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9)); let d = f32x4::new(1.0, 1.0, 1.0, 1.0); - assert_eq!(d, transmute(vec_ceil(a))); + assert_eq!(d, f32x4::from(unsafe { vec_ceil(a) })); } test_vec_2! { test_vec_andc, vec_andc, i32x4, @@ -5926,11 +5974,11 @@ mod tests { macro_rules! test_vec_abs { { $name: ident, $ty: ident, $a: expr, $d: expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a = vec_splats($a); - let a: s_t_l!($ty) = vec_abs(a); + fn $name() { + let a = unsafe { vec_splats($a) }; + let a: s_t_l!($ty) = unsafe { vec_abs(a) }; let d = $ty::splat($d); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -5943,11 +5991,11 @@ mod tests { macro_rules! test_vec_abss { { $name: ident, $ty: ident, $a: expr, $d: expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a = vec_splats($a); - let a: s_t_l!($ty) = vec_abss(a); + fn $name() { + let a = unsafe { vec_splats($a) }; + let a: s_t_l!($ty) = unsafe { vec_abss(a) }; let d = $ty::splat($d); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -5959,10 +6007,10 @@ mod tests { macro_rules! test_vec_splats { { $name: ident, $ty: ident, $a: expr } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = vec_splats($a); + fn $name() { + let a: s_t_l!($ty) = unsafe { vec_splats($a) }; let d = $ty::splat($a); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -5978,10 +6026,10 @@ mod tests { macro_rules! test_vec_splat { { $name: ident, $fun: ident, $ty: ident, $a: expr, $b: expr} => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a = $fun::<$a>(); + fn $name() { + let a = unsafe { $fun::<$a>() }; let d = $ty::splat($b); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -6073,12 +6121,12 @@ mod tests { macro_rules! test_vec_min { { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); + let b: s_t_l!($ty) = $ty::new($($b),+).into(); let d = $ty::new($($d),+); - let r : $ty = transmute(vec_min(a, b)); + let r = $ty::from(unsafe { vec_min(a, b) }); assert_eq!(d, r); } } @@ -6117,12 +6165,12 @@ mod tests { macro_rules! test_vec_max { { $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); + let b: s_t_l!($ty) = $ty::new($($b),+).into(); let d = $ty::new($($d),+); - let r : $ty = transmute(vec_max(a, b)); + let r = $ty::from(unsafe { vec_max(a, b) }); assert_eq!(d, r); } } @@ -6163,13 +6211,13 @@ mod tests { $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: $longtype = transmute($shorttype::new($($a),+)); - let b: $longtype = transmute($shorttype::new($($b),+)); - let c: vector_unsigned_char = transmute(u8x16::new($($c),+)); + fn $name() { + let a = $longtype::from($shorttype::new($($a),+)); + let b = $longtype::from($shorttype::new($($b),+)); + let c = vector_unsigned_char::from(u8x16::new($($c),+)); let d = $shorttype::new($($d),+); - let r: $shorttype = transmute(vec_perm(a, b, c)); + let r = $shorttype::from(unsafe { vec_perm(a, b, c) }); assert_eq!(d, r); } } @@ -6249,8 +6297,8 @@ mod tests { [0.0, 1.0, 1.0, 1.1]} #[simd_test(enable = "altivec")] - unsafe fn test_vec_madds() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_madds() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6260,19 +6308,19 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, 21); - assert_eq!(d, transmute(vec_madds(a, b, c))); + assert_eq!(d, i16x8::from(unsafe { vec_madds(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_madd_float() { - let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); + fn test_vec_madd_float() { + let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); let d = f32x4::new( 0.1 * 0.1 + 0.1, 0.2 * 0.2 + 0.2, @@ -6280,26 +6328,26 @@ mod tests { 0.4 * 0.4 + 0.4, ); - assert_eq!(d, transmute(vec_madd(a, b, c))); + assert_eq!(d, f32x4::from(unsafe { vec_madd(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_nmsub_float() { - let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); - let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4)); + fn test_vec_nmsub_float() { + let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); + let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4)); let d = f32x4::new( -(0.1 * 0.1 - 0.1), -(0.2 * 0.2 - 0.2), -(0.3 * 0.3 - 0.3), -(0.4 * 0.4 - 0.4), ); - assert_eq!(d, transmute(vec_nmsub(a, b, c))); + assert_eq!(d, f32x4::from(unsafe { vec_nmsub(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mradds() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_mradds() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6309,25 +6357,25 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1)); let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, i16::MAX); - assert_eq!(d, transmute(vec_mradds(a, b, c))); + assert_eq!(d, i16x8::from(unsafe { vec_mradds(a, b, c) })); } macro_rules! test_vec_mladd { {$name:ident, $sa:ident, $la:ident, $sbc:ident, $lbc:ident, $sd:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "altivec")] - unsafe fn $name() { - let a: $la = transmute($sa::new($($a),+)); - let b: $lbc = transmute($sbc::new($($b),+)); - let c = transmute($sbc::new($($c),+)); + fn $name() { + let a = $la::from($sa::new($($a),+)); + let b = $lbc::from($sbc::new($($b),+)); + let c = $sbc::new($($c),+).into(); let d = $sd::new($($d),+); - assert_eq!(d, transmute(vec_mladd(a, b, c))); + assert_eq!(d, $sd::from(unsafe { vec_mladd(a, b, c) })); } } } @@ -6335,24 +6383,24 @@ mod tests { test_vec_mladd! { test_vec_mladd_u16x8_u16x8, u16x8, vector_unsigned_short, u16x8, vector_unsigned_short, u16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } - test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_unsigned_short, i16x8, + test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_signed_short, i16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } test_vec_mladd! { test_vec_mladd_i16x8_u16x8, i16x8, vector_signed_short, u16x8, vector_unsigned_short, i16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } - test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_unsigned_short, i16x8, + test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_signed_short, i16x8, [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56] } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_unsigned_char = transmute(u8x16::new( + fn test_vec_msum_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_unsigned_char::from(u8x16::new( 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, )); - let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( (0 + 1 + 2 + 3) * 255 + 0, (4 + 5 + 6 + 7) * 255 + 1, @@ -6360,17 +6408,17 @@ mod tests { (4 + 5 + 6 + 7) * 255 + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_signed_char() { - let a: vector_signed_char = transmute(i8x16::new( + fn test_vec_msum_signed_char() { + let a = vector_signed_char::from(i8x16::new( 0, -1, 2, -3, 1, -1, 1, -1, 0, 1, 2, 3, 4, -5, -6, -7, )); - let b: vector_unsigned_char = - transmute(i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)); - let c: vector_signed_int = transmute(u32x4::new(0, 1, 2, 3)); + let b = + vector_unsigned_char::from(u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)); + let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( (0 - 1 + 2 - 3) + 0, (0) + 1, @@ -6378,11 +6426,12 @@ mod tests { (4 - 5 - 6 - 7) + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) })); } + #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_unsigned_short() { - let a: vector_unsigned_short = transmute(u16x8::new( + fn test_vec_msum_unsigned_short() { + let a = vector_unsigned_short::from(u16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6392,9 +6441,8 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_unsigned_short = - transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( (0 + 1) * 256 * 256 + 0, (2 + 3) * 256 * 256 + 1, @@ -6402,12 +6450,12 @@ mod tests { (6 + 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msum_signed_short() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_msum_signed_short() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, -1 * 256, 2 * 256, @@ -6417,8 +6465,8 @@ mod tests { 6 * 256, -7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( (0 - 1) * 256 * 256 + 0, (2 - 3) * 256 * 256 + 1, @@ -6426,12 +6474,12 @@ mod tests { (6 - 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msum(a, b, c))); + assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msums_unsigned() { - let a: vector_unsigned_short = transmute(u16x8::new( + fn test_vec_msums_unsigned() { + let a = vector_unsigned_short::from(u16x8::new( 0 * 256, 1 * 256, 2 * 256, @@ -6441,9 +6489,8 @@ mod tests { 6 * 256, 7 * 256, )); - let b: vector_unsigned_short = - transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( (0 + 1) * 256 * 256 + 0, (2 + 3) * 256 * 256 + 1, @@ -6451,12 +6498,12 @@ mod tests { (6 + 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msums(a, b, c))); + assert_eq!(d, u32x4::from(unsafe { vec_msums(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_msums_signed() { - let a: vector_signed_short = transmute(i16x8::new( + fn test_vec_msums_signed() { + let a = vector_signed_short::from(i16x8::new( 0 * 256, -1 * 256, 2 * 256, @@ -6466,8 +6513,8 @@ mod tests { 6 * 256, -7 * 256, )); - let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); - let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256)); + let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( (0 - 1) * 256 * 256 + 0, (2 - 3) * 256 * 256 + 1, @@ -6475,23 +6522,23 @@ mod tests { (6 - 7) * 256 * 256 + 3, ); - assert_eq!(d, transmute(vec_msums(a, b, c))); + assert_eq!(d, i32x4::from(unsafe { vec_msums(a, b, c) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum2s() { - let a: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); - let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + fn test_vec_sum2s() { + let a = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); + let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new(0, 0 + 1 + 1, 0, 2 + 3 + 3); - assert_eq!(d, transmute(vec_sum2s(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_sum2s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum4s_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3)); + fn test_vec_sum4s_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3)); let d = u32x4::new( 0 + 1 + 2 + 3 + 0, 4 + 5 + 6 + 7 + 1, @@ -6499,13 +6546,13 @@ mod tests { 4 + 5 + 6 + 7 + 3, ); - assert_eq!(d, transmute(vec_sum4s(a, b))); + assert_eq!(d, u32x4::from(unsafe { vec_sum4s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum4s_signed_char() { - let a: vector_signed_char = - transmute(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + fn test_vec_sum4s_signed_char() { + let a = + vector_signed_char::from(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new( 0 + 1 + 2 + 3 + 0, 4 + 5 + 6 + 7 + 1, @@ -6513,109 +6560,110 @@ mod tests { 4 + 5 + 6 + 7 + 3, ); - assert_eq!(d, transmute(vec_sum4s(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_sum4s_signed_short() { - let a: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); - let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3)); + fn test_vec_sum4s_signed_short() { + let a = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3)); let d = i32x4::new(0 + 1 + 0, 2 + 3 + 1, 4 + 5 + 2, 6 + 7 + 3); - assert_eq!(d, transmute(vec_sum4s(a, b))); + assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mule_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); let d = u16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, u16x8::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_signed_char() { - let a: vector_signed_char = transmute(i8x16::new( + fn test_vec_mule_signed_char() { + let a = vector_signed_char::from(i8x16::new( 0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7, )); let d = i16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, i16x8::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_unsigned_short() { - let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mule_unsigned_short() { + let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); let d = u32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, u32x4::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mule_signed_short() { - let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); + fn test_vec_mule_signed_short() { + let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); let d = i32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6); - assert_eq!(d, transmute(vec_mule(a, a))); + assert_eq!(d, i32x4::from(unsafe { vec_mule(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_unsigned_char() { - let a: vector_unsigned_char = - transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mulo_unsigned_char() { + let a = + vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7)); let d = u16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, u16x8::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_signed_char() { - let a: vector_signed_char = transmute(i8x16::new( + fn test_vec_mulo_signed_char() { + let a = vector_signed_char::from(i8x16::new( 0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7, )); let d = i16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, i16x8::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_unsigned_short() { - let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); + fn test_vec_mulo_unsigned_short() { + let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)); let d = u32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, u32x4::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn test_vec_mulo_signed_short() { - let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); + fn test_vec_mulo_signed_short() { + let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7)); let d = i32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7); - assert_eq!(d, transmute(vec_mulo(a, a))); + assert_eq!(d, i32x4::from(unsafe { vec_mulo(a, a) })); } #[simd_test(enable = "altivec")] - unsafe fn vec_add_i32x4_i32x4() { + fn vec_add_i32x4_i32x4() { let x = i32x4::new(1, 2, 3, 4); let y = i32x4::new(4, 3, 2, 1); - let x: vector_signed_int = transmute(x); - let y: vector_signed_int = transmute(y); - let z = vec_add(x, y); - assert_eq!(i32x4::splat(5), transmute(z)); + let x = vector_signed_int::from(x); + let y = vector_signed_int::from(y); + let z = unsafe { vec_add(x, y) }; + assert_eq!(i32x4::splat(5), i32x4::from(z)); } #[simd_test(enable = "altivec")] - unsafe fn vec_ctf_u32() { - let v: vector_unsigned_int = transmute(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42)); - let v2 = vec_ctf::<1, _>(v); - let r2: vector_float = transmute(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0)); - let v4 = vec_ctf::<2, _>(v); - let r4: vector_float = transmute(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5)); - let v8 = vec_ctf::<3, _>(v); - let r8: vector_float = transmute(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25)); + fn vec_ctf_u32() { + let v = vector_unsigned_int::from(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42)); + let v2 = unsafe { vec_ctf::<1, _>(v) }; + let r2 = vector_float::from(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0)); + let v4 = unsafe { vec_ctf::<2, _>(v) }; + let r4 = vector_float::from(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5)); + let v8 = unsafe { vec_ctf::<3, _>(v) }; + let r8 = vector_float::from(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25)); let check = |a, b| { - let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON))); + let r = + m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) }); let e = m32x4::new(true, true, true, true); assert_eq!(e, r); }; @@ -6626,26 +6674,32 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_ctu() { + fn test_vec_ctu() { let v = u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42); - let v2: u32x4 = transmute(vec_ctu::<1>(transmute(f32x4::new( - 0.0, - 2147483600.0, - 2147483600.0, - 21.0, - )))); - let v4: u32x4 = transmute(vec_ctu::<2>(transmute(f32x4::new( - 0.0, - 1073741800.0, - 1073741800.0, - 10.5, - )))); - let v8: u32x4 = transmute(vec_ctu::<3>(transmute(f32x4::new( - 0.0, - 536870900.0, - 536870900.0, - 5.25, - )))); + let v2 = u32x4::from(unsafe { + vec_ctu::<1>(vector_float::from(f32x4::new( + 0.0, + 2147483600.0, + 2147483600.0, + 21.0, + ))) + }); + let v4 = u32x4::from(unsafe { + vec_ctu::<2>(vector_float::from(f32x4::new( + 0.0, + 1073741800.0, + 1073741800.0, + 10.5, + ))) + }); + let v8 = u32x4::from(unsafe { + vec_ctu::<3>(vector_float::from(f32x4::new( + 0.0, + 536870900.0, + 536870900.0, + 5.25, + ))) + }); assert_eq!(v2, v); assert_eq!(v4, v); @@ -6653,18 +6707,18 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn vec_ctf_i32() { - let v: vector_signed_int = transmute(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42)); - let v2 = vec_ctf::<1, _>(v); - let r2: vector_float = - transmute(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0)); - let v4 = vec_ctf::<2, _>(v); - let r4: vector_float = transmute(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5)); - let v8 = vec_ctf::<3, _>(v); - let r8: vector_float = transmute(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25)); + fn vec_ctf_i32() { + let v = vector_signed_int::from(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42)); + let v2 = unsafe { vec_ctf::<1, _>(v) }; + let r2 = vector_float::from(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0)); + let v4 = unsafe { vec_ctf::<2, _>(v) }; + let r4 = vector_float::from(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5)); + let v8 = unsafe { vec_ctf::<3, _>(v) }; + let r8 = vector_float::from(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25)); let check = |a, b| { - let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON))); + let r = + m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) }); println!("{:?} {:?}", a, b); let e = m32x4::new(true, true, true, true); assert_eq!(e, r); @@ -6676,26 +6730,32 @@ mod tests { } #[simd_test(enable = "altivec")] - unsafe fn test_vec_cts() { + fn test_vec_cts() { let v = i32x4::new(i32::MIN, i32::MAX, i32::MAX, 42); - let v2: i32x4 = transmute(vec_cts::<1>(transmute(f32x4::new( - -1073741800.0, - 1073741800.0, - 1073741800.0, - 21.0, - )))); - let v4: i32x4 = transmute(vec_cts::<2>(transmute(f32x4::new( - -536870900.0, - 536870900.0, - 536870900.0, - 10.5, - )))); - let v8: i32x4 = transmute(vec_cts::<3>(transmute(f32x4::new( - -268435460.0, - 268435460.0, - 268435460.0, - 5.25, - )))); + let v2 = i32x4::from(unsafe { + vec_cts::<1>(transmute(f32x4::new( + -1073741800.0, + 1073741800.0, + 1073741800.0, + 21.0, + ))) + }); + let v4 = i32x4::from(unsafe { + vec_cts::<2>(transmute(f32x4::new( + -536870900.0, + 536870900.0, + 536870900.0, + 10.5, + ))) + }); + let v8 = i32x4::from(unsafe { + vec_cts::<3>(transmute(f32x4::new( + -268435460.0, + 268435460.0, + 268435460.0, + 5.25, + ))) + }); assert_eq!(v2, v); assert_eq!(v4, v); diff --git a/stdarch/crates/core_arch/src/powerpc/vsx.rs b/stdarch/crates/core_arch/src/powerpc/vsx.rs index ca9fcaabe8b22..0aac236173401 100644 --- a/stdarch/crates/core_arch/src/powerpc/vsx.rs +++ b/stdarch/crates/core_arch/src/powerpc/vsx.rs @@ -9,6 +9,7 @@ #![allow(non_camel_case_types)] use crate::core_arch::powerpc::*; +use crate::core_arch::simd::*; #[cfg(test)] use stdarch_test::assert_instr; @@ -34,6 +35,22 @@ types! { // pub struct vector_unsigned___int128 = i128x1; } +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for vector_bool_long { + #[inline] + fn from(value: m64x2) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_powerpc", issue = "111145")] +impl From for m64x2 { + #[inline] + fn from(value: vector_bool_long) -> Self { + unsafe { transmute(value) } + } +} + #[allow(improper_ctypes)] unsafe extern "C" { #[link_name = "llvm.ppc.altivec.vperm"] @@ -46,7 +63,6 @@ unsafe extern "C" { mod sealed { use super::*; - use crate::core_arch::simd::*; #[unstable(feature = "stdarch_powerpc", issue = "111145")] pub trait VectorPermDI { @@ -221,14 +237,16 @@ mod tests { macro_rules! test_vec_xxpermdi { {$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "vsx")] - unsafe fn $name() { - let a: $longtype = transmute($shorttype::new($($a),+, $($b),+)); - let b = transmute($shorttype::new($($c),+, $($d),+)); - - assert_eq!($shorttype::new($($a),+, $($c),+), transmute(vec_xxpermdi::<_, 0>(a, b))); - assert_eq!($shorttype::new($($b),+, $($c),+), transmute(vec_xxpermdi::<_, 1>(a, b))); - assert_eq!($shorttype::new($($a),+, $($d),+), transmute(vec_xxpermdi::<_, 2>(a, b))); - assert_eq!($shorttype::new($($b),+, $($d),+), transmute(vec_xxpermdi::<_, 3>(a, b))); + fn $name() { + let a = $longtype::from($shorttype::new($($a),+, $($b),+)); + let b = $longtype::from($shorttype::new($($c),+, $($d),+)); + + unsafe { + assert_eq!($shorttype::new($($a),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 0>(a, b))); + assert_eq!($shorttype::new($($b),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 1>(a, b))); + assert_eq!($shorttype::new($($a),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 2>(a, b))); + assert_eq!($shorttype::new($($b),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 3>(a, b))); + } } } } diff --git a/stdarch/crates/core_arch/src/s390x/mod.rs b/stdarch/crates/core_arch/src/s390x/mod.rs index 7d3b3f2d99aae..5b85020072d87 100644 --- a/stdarch/crates/core_arch/src/s390x/mod.rs +++ b/stdarch/crates/core_arch/src/s390x/mod.rs @@ -2,6 +2,11 @@ pub(crate) mod macros; +/// the float and vector registers overlap therefore we cannot use any vector +/// extensions if softfloat is enabled. + +#[cfg(not(target_abi = "softfloat"))] mod vector; +#[cfg(not(target_abi = "softfloat"))] #[unstable(feature = "stdarch_s390x", issue = "130869")] pub use self::vector::*; diff --git a/stdarch/crates/core_arch/src/s390x/vector.rs b/stdarch/crates/core_arch/src/s390x/vector.rs index e1f841030c000..346cd674df665 100644 --- a/stdarch/crates/core_arch/src/s390x/vector.rs +++ b/stdarch/crates/core_arch/src/s390x/vector.rs @@ -51,6 +51,54 @@ types! { pub struct vector_double(2 x f64); } +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for vector_bool_char { + #[inline] + fn from(value: m8x16) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for m8x16 { + #[inline] + fn from(value: vector_bool_char) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for vector_bool_short { + #[inline] + fn from(value: m16x8) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for m16x8 { + #[inline] + fn from(value: vector_bool_short) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for vector_bool_int { + #[inline] + fn from(value: m32x4) -> Self { + unsafe { transmute(value) } + } +} + +#[unstable(feature = "stdarch_s390x", issue = "135681")] +impl From for m32x4 { + #[inline] + fn from(value: vector_bool_int) -> Self { + unsafe { transmute(value) } + } +} + #[repr(C, packed)] struct PackedTuple { x: T, @@ -6051,27 +6099,16 @@ mod tests { } macro_rules! test_vec_1 { - { $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => { - #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: vector_float = transmute(f32x4::new($($a),+)); - - let d: vector_float = transmute(f32x4::new($($d),+)); - let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON))); - let e = m32x4::new(true, true, true, true); - assert_eq!(e, r); - } - }; { $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($d:expr),+] } => { test_vec_1! { $name, $fn, $ty -> $ty, [$($a),+], [$($d),+] } }; { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); + fn $name() { + let a: s_t_l!($ty) = $ty::new($($a),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a)); + let r = $ty_out::from(unsafe { $fn(a) }); assert_eq!(d, r); } } @@ -6086,35 +6123,23 @@ mod tests { }; { $name: ident, $fn:ident, $ty1: ident, $ty2: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty1) = transmute($ty1::new($($a),+)); - let b: s_t_l!($ty2) = transmute($ty2::new($($b),+)); + fn $name() { + let a: s_t_l!($ty1) = $ty1::new($($a),+).into(); + let b: s_t_l!($ty2) = $ty2::new($($b),+).into(); let d = $ty_out::new($($d),+); - let r : $ty_out = transmute($fn(a, b)); + let r = $ty_out::from(unsafe { $fn(a, b) }); assert_eq!(d, r); } }; - { $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => { - #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty) = transmute($ty::new($($a),+)); - let b: s_t_l!($ty) = transmute($ty::new($($b),+)); - - let r : $ty_out = transmute($fn(a, b)); - assert_eq!($d, r); - } - } } #[simd_test(enable = "vector")] - unsafe fn vec_add_i32x4_i32x4() { - let x = i32x4::new(1, 2, 3, 4); - let y = i32x4::new(4, 3, 2, 1); - let x: vector_signed_int = transmute(x); - let y: vector_signed_int = transmute(y); - let z = vec_add(x, y); - assert_eq!(i32x4::splat(5), transmute(z)); + fn vec_add_i32x4_i32x4() { + let x = vector_signed_int::from(i32x4::new(1, 2, 3, 4)); + let y = vector_signed_int::from(i32x4::new(4, 3, 2, 1)); + let z = unsafe { vec_add(x, y) }; + assert_eq!(i32x4::splat(5), i32x4::from(z)); } macro_rules! test_vec_sub { @@ -6232,11 +6257,11 @@ mod tests { macro_rules! test_vec_abs { { $name: ident, $ty: ident, $a: expr, $d: expr } => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: s_t_l!($ty) = vec_splats($a); - let a: s_t_l!($ty) = vec_abs(a); + fn $name() { + let a: s_t_l!($ty) = unsafe { vec_splats($a) }; + let a: s_t_l!($ty) = unsafe { vec_abs(a) }; let d = $ty::splat($d); - assert_eq!(d, transmute(a)); + assert_eq!(d, $ty::from(a)); } } } @@ -6386,7 +6411,7 @@ mod tests { [0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 16], [4, 2, 1, 8] } - test_vec_2! { test_vec_sral_pos, vec_sral, u32x4, u8x16 -> i32x4, + test_vec_2! { test_vec_sral_pos, vec_sral, u32x4, u8x16 -> u32x4, [0b1000, 0b1000, 0b1000, 0b1000], [0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 16], [4, 2, 1, 8] } @@ -6423,13 +6448,13 @@ mod tests { $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => { #[simd_test(enable = "vector")] - unsafe fn $name() { - let a: $longtype = transmute($shorttype::new($($a),+)); - let b: $longtype = transmute($shorttype::new($($b),+)); - let c: vector_unsigned_char = transmute(u8x16::new($($c),+)); + fn $name() { + let a = $longtype::from($shorttype::new($($a),+)); + let b = $longtype::from($shorttype::new($($b),+)); + let c = vector_unsigned_char::from(u8x16::new($($c),+)); let d = $shorttype::new($($d),+); - let r: $shorttype = transmute(vec_perm(a, b, c)); + let r = $shorttype::from(unsafe { vec_perm(a, b, c) }); assert_eq!(d, r); } } @@ -6512,46 +6537,46 @@ mod tests { [core::f32::consts::PI, 1.0, 25.0, 2.0], [core::f32::consts::PI.sqrt(), 1.0, 5.0, core::f32::consts::SQRT_2] } - test_vec_2! { test_vec_find_any_eq, vec_find_any_eq, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq, vec_find_any_eq, i32x4, i32x4 -> i32x4, [1, -2, 3, -4], [-5, 3, -7, 8], - [0, 0, 0xFFFFFFFF, 0] + [0, 0, !0, 0] } - test_vec_2! { test_vec_find_any_ne, vec_find_any_ne, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne, vec_find_any_ne, i32x4, i32x4 -> i32x4, [1, -2, 3, -4], [-5, 3, -7, 8], - [0xFFFFFFFF, 0xFFFFFFFF, 0, 0xFFFFFFFF] + [!0, !0, 0, !0] } - test_vec_2! { test_vec_find_any_eq_idx_1, vec_find_any_eq_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq_idx_1, vec_find_any_eq_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [5, 3, 7, 8], [0, 8, 0, 0] } - test_vec_2! { test_vec_find_any_eq_idx_2, vec_find_any_eq_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq_idx_2, vec_find_any_eq_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [5, 6, 7, 8], [0, 16, 0, 0] } - test_vec_2! { test_vec_find_any_ne_idx_1, vec_find_any_ne_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne_idx_1, vec_find_any_ne_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [1, 5, 3, 4], [0, 4, 0, 0] } - test_vec_2! { test_vec_find_any_ne_idx_2, vec_find_any_ne_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne_idx_2, vec_find_any_ne_idx, i32x4, i32x4 -> i32x4, [1, 2, 3, 4], [1, 2, 3, 4], [0, 16, 0, 0] } - test_vec_2! { test_vec_find_any_eq_or_0_idx_1, vec_find_any_eq_or_0_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_eq_or_0_idx_1, vec_find_any_eq_or_0_idx, i32x4, i32x4 -> i32x4, [1, 2, 0, 4], [5, 6, 7, 8], [0, 8, 0, 0] } - test_vec_2! { test_vec_find_any_ne_or_0_idx_1, vec_find_any_ne_or_0_idx, i32x4, i32x4 -> u32x4, + test_vec_2! { test_vec_find_any_ne_or_0_idx_1, vec_find_any_ne_or_0_idx, i32x4, i32x4 -> i32x4, [1, 2, 0, 4], [1, 2, 3, 4], [0, 8, 0, 0] diff --git a/stdarch/crates/core_arch/src/wasm32/simd128.rs b/stdarch/crates/core_arch/src/wasm32/simd128.rs index c864d6a516e08..e1a3754965907 100644 --- a/stdarch/crates/core_arch/src/wasm32/simd128.rs +++ b/stdarch/crates/core_arch/src/wasm32/simd128.rs @@ -86,10 +86,6 @@ unsafe extern "unadjusted" { fn llvm_i8x16_all_true(x: simd::i8x16) -> i32; #[link_name = "llvm.wasm.bitmask.v16i8"] fn llvm_bitmask_i8x16(a: simd::i8x16) -> i32; - #[link_name = "llvm.wasm.narrow.signed.v16i8.v8i16"] - fn llvm_narrow_i8x16_s(a: simd::i16x8, b: simd::i16x8) -> simd::i8x16; - #[link_name = "llvm.wasm.narrow.unsigned.v16i8.v8i16"] - fn llvm_narrow_i8x16_u(a: simd::i16x8, b: simd::i16x8) -> simd::i8x16; #[link_name = "llvm.wasm.avgr.unsigned.v16i8"] fn llvm_avgr_u_i8x16(a: simd::i8x16, b: simd::i8x16) -> simd::i8x16; @@ -103,10 +99,6 @@ unsafe extern "unadjusted" { fn llvm_i16x8_all_true(x: simd::i16x8) -> i32; #[link_name = "llvm.wasm.bitmask.v8i16"] fn llvm_bitmask_i16x8(a: simd::i16x8) -> i32; - #[link_name = "llvm.wasm.narrow.signed.v8i16.v4i32"] - fn llvm_narrow_i16x8_s(a: simd::i32x4, b: simd::i32x4) -> simd::i16x8; - #[link_name = "llvm.wasm.narrow.unsigned.v8i16.v4i32"] - fn llvm_narrow_i16x8_u(a: simd::i32x4, b: simd::i32x4) -> simd::i16x8; #[link_name = "llvm.wasm.avgr.unsigned.v8i16"] fn llvm_avgr_u_i16x8(a: simd::i16x8, b: simd::i16x8) -> simd::i16x8; @@ -2281,7 +2273,23 @@ pub use i8x16_bitmask as u8x16_bitmask; #[doc(alias("i8x16.narrow_i16x8_s"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn i8x16_narrow_i16x8(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i8x16_s(a.as_i16x8(), b.as_i16x8()).v128() } + unsafe { + let v: simd::i16x16 = simd_shuffle!( + a.as_i16x8(), + b.as_i16x8(), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ); + + let max = simd_splat(i16::from(i8::MAX)); + let min = simd_splat(i16::from(i8::MIN)); + + let v = simd_select(simd_gt::<_, simd::i16x16>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i16x16>(v, min), min, v); + + let v: simd::i8x16 = simd_cast(v); + + v.v128() + } } /// Converts two input vectors into a smaller lane vector by narrowing each @@ -2295,7 +2303,23 @@ pub fn i8x16_narrow_i16x8(a: v128, b: v128) -> v128 { #[doc(alias("i8x16.narrow_i16x8_u"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn u8x16_narrow_i16x8(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i8x16_u(a.as_i16x8(), b.as_i16x8()).v128() } + unsafe { + let v: simd::i16x16 = simd_shuffle!( + a.as_i16x8(), + b.as_i16x8(), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ); + + let max = simd_splat(i16::from(u8::MAX)); + let min = simd_splat(i16::from(u8::MIN)); + + let v = simd_select(simd_gt::<_, simd::i16x16>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i16x16>(v, min), min, v); + + let v: simd::u8x16 = simd_cast(v); + + v.v128() + } } /// Shifts each lane to the left by the specified number of bits. @@ -2593,7 +2617,19 @@ pub use i16x8_bitmask as u16x8_bitmask; #[doc(alias("i16x8.narrow_i32x4_s"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn i16x8_narrow_i32x4(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i16x8_s(a.as_i32x4(), b.as_i32x4()).v128() } + unsafe { + let v: simd::i32x8 = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); + + let max = simd_splat(i32::from(i16::MAX)); + let min = simd_splat(i32::from(i16::MIN)); + + let v = simd_select(simd_gt::<_, simd::i32x8>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i32x8>(v, min), min, v); + + let v: simd::i16x8 = simd_cast(v); + + v.v128() + } } /// Converts two input vectors into a smaller lane vector by narrowing each @@ -2607,7 +2643,19 @@ pub fn i16x8_narrow_i32x4(a: v128, b: v128) -> v128 { #[doc(alias("i16x8.narrow_i32x4_u"))] #[stable(feature = "wasm_simd", since = "1.54.0")] pub fn u16x8_narrow_i32x4(a: v128, b: v128) -> v128 { - unsafe { llvm_narrow_i16x8_u(a.as_i32x4(), b.as_i32x4()).v128() } + unsafe { + let v: simd::i32x8 = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]); + + let max = simd_splat(i32::from(u16::MAX)); + let min = simd_splat(i32::from(u16::MIN)); + + let v = simd_select(simd_gt::<_, simd::i32x8>(v, max), max, v); + let v = simd_select(simd_lt::<_, simd::i32x8>(v, min), min, v); + + let v: simd::u16x8 = simd_cast(v); + + v.v128() + } } /// Converts low half of the smaller lane vector to a larger lane diff --git a/stdarch/crates/core_arch/src/x86/avx.rs b/stdarch/crates/core_arch/src/x86/avx.rs index 7b4b210bacf4c..74fc2db13dcdc 100644 --- a/stdarch/crates/core_arch/src/x86/avx.rs +++ b/stdarch/crates/core_arch/src/x86/avx.rs @@ -2426,7 +2426,6 @@ pub const fn _mm256_setzero_si256() -> __m256i { #[inline] #[target_feature(enable = "avx")] // This intrinsic has no corresponding instruction. -#[cfg_attr(test, assert_instr(vinsertf128))] #[stable(feature = "simd_x86", since = "1.27.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_set_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d { diff --git a/stdarch/crates/core_arch/src/x86/avx2.rs b/stdarch/crates/core_arch/src/x86/avx2.rs index 6a39a0aaf8feb..04a88e461f752 100644 --- a/stdarch/crates/core_arch/src/x86/avx2.rs +++ b/stdarch/crates/core_arch/src/x86/avx2.rs @@ -991,7 +991,21 @@ pub const fn _mm256_hadd_epi32(a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vphaddsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm256_hadds_epi16(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(phaddsw(a.as_i16x16(), b.as_i16x16())) } + let a = a.as_i16x16(); + let b = b.as_i16x16(); + unsafe { + let even: i16x16 = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30] + ); + let odd: i16x16 = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31] + ); + simd_saturating_add(even, odd).as_m256i() + } } /// Horizontally subtract adjacent pairs of 16-bit integers in `a` and `b`. @@ -1047,7 +1061,21 @@ pub const fn _mm256_hsub_epi32(a: __m256i, b: __m256i) -> __m256i { #[cfg_attr(test, assert_instr(vphsubsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm256_hsubs_epi16(a: __m256i, b: __m256i) -> __m256i { - unsafe { transmute(phsubsw(a.as_i16x16(), b.as_i16x16())) } + let a = a.as_i16x16(); + let b = b.as_i16x16(); + unsafe { + let even: i16x16 = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30] + ); + let odd: i16x16 = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31] + ); + simd_saturating_sub(even, odd).as_m256i() + } } /// Returns values from `slice` at offsets determined by `offsets * scale`, @@ -3791,10 +3819,6 @@ pub const fn _mm256_extract_epi16(a: __m256i) -> i32 { #[allow(improper_ctypes)] unsafe extern "C" { - #[link_name = "llvm.x86.avx2.phadd.sw"] - fn phaddsw(a: i16x16, b: i16x16) -> i16x16; - #[link_name = "llvm.x86.avx2.phsub.sw"] - fn phsubsw(a: i16x16, b: i16x16) -> i16x16; #[link_name = "llvm.x86.avx2.pmadd.wd"] fn pmaddwd(a: i16x16, b: i16x16) -> i32x8; #[link_name = "llvm.x86.avx2.pmadd.ub.sw"] @@ -4653,6 +4677,26 @@ mod tests { assert_eq_m256i(r, e); } + #[target_feature(enable = "avx2")] + #[cfg_attr(test, assert_instr(vpmaddwd))] + unsafe fn test_mm256_madd_epi16_mul_one(v: __m256i) -> __m256i { + // This is a trick used in the adler32 algorithm to get a widening addition. The + // multiplication by 1 is trivial, but must not be optimized out because then the vpmaddwd + // instruction is no longer selected. The assert_instr verifies that this is the case. + let one_v = _mm256_set1_epi16(1); + _mm256_madd_epi16(v, one_v) + } + + #[target_feature(enable = "avx2")] + #[cfg_attr(test, assert_instr(vpmaddwd))] + unsafe fn test_mm256_madd_epi16_shl(v: __m256i) -> __m256i { + // This is a trick used in the base64 algorithm to get a widening addition. Instead of a + // multiplication, a vector shl is used. In LLVM 22 that breaks the pattern recognition + // for the automatic optimization to vpmaddwd. + let shift_value = _mm256_set1_epi32(12i32); + _mm256_madd_epi16(v, shift_value) + } + #[simd_test(enable = "avx2")] const fn test_mm256_inserti128_si256() { let a = _mm256_setr_epi64x(1, 2, 3, 4); diff --git a/stdarch/crates/core_arch/src/x86/avx512bw.rs b/stdarch/crates/core_arch/src/x86/avx512bw.rs index 8e074fdcfa486..3ba171c0fa50f 100644 --- a/stdarch/crates/core_arch/src/x86/avx512bw.rs +++ b/stdarch/crates/core_arch/src/x86/avx512bw.rs @@ -12476,7 +12476,14 @@ pub unsafe fn _mm512_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32, #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { - vpmovswbmem256(mem_addr, a.as_i16x16(), k); + let mask = simd_select_bitmask(k, i16x16::splat(!0), i16x16::ZERO); + + let max = simd_splat(i16::from(i8::MAX)); + let min = simd_splat(i16::from(i8::MIN)); + + let v = simd_imax(simd_imin(a.as_i16x16(), max), min); + let truncated: i8x16 = simd_cast(v); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } /// Convert packed signed 16-bit integers in a to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr. @@ -12487,7 +12494,14 @@ pub unsafe fn _mm256_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovswb))] pub unsafe fn _mm_mask_cvtsepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { - vpmovswbmem128(mem_addr, a.as_i16x8(), k); + let mask = simd_select_bitmask(k, i16x8::splat(!0), i16x8::ZERO); + + let max = simd_splat(i16::from(i8::MAX)); + let min = simd_splat(i16::from(i8::MIN)); + + let v = simd_imax(simd_imin(a.as_i16x8(), max), min); + let truncated: i8x8 = simd_cast(v); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } /// Convert packed 16-bit integers in a to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr. @@ -12555,7 +12569,12 @@ pub unsafe fn _mm512_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask32 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16, a: __m256i) { - vpmovuswbmem256(mem_addr, a.as_i16x16(), k); + let mask = simd_select_bitmask(k, i16x16::splat(!0), i16x16::ZERO); + let mem_addr = mem_addr.cast::(); + let max = simd_splat(u16::from(u8::MAX)); + + let truncated: u8x16 = simd_cast(simd_imin(a.as_u16x16(), max)); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } /// Convert packed unsigned 16-bit integers in a to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask k) to unaligned memory at base_addr. @@ -12566,7 +12585,15 @@ pub unsafe fn _mm256_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask16 #[stable(feature = "stdarch_x86_avx512", since = "1.89")] #[cfg_attr(test, assert_instr(vpmovuswb))] pub unsafe fn _mm_mask_cvtusepi16_storeu_epi8(mem_addr: *mut i8, k: __mmask8, a: __m128i) { - vpmovuswbmem128(mem_addr, a.as_i16x8(), k); + let mask = simd_select_bitmask(k, i16x8::splat(!0), i16x8::ZERO); + let mem_addr = mem_addr.cast::(); + let max = simd_splat(u16::from(u8::MAX)); + + let v = a.as_u16x8(); + let v = simd_imin(v, max); + + let truncated: u8x8 = simd_cast(v); + simd_masked_store!(SimdAlign::Unaligned, mask, mem_addr, truncated); } #[allow(improper_ctypes)] @@ -12632,17 +12659,9 @@ unsafe extern "C" { #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.512"] fn vpmovswbmem(mem_addr: *mut i8, a: i16x32, mask: u32); - #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.256"] - fn vpmovswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16); - #[link_name = "llvm.x86.avx512.mask.pmovs.wb.mem.128"] - fn vpmovswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8); #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.512"] fn vpmovuswbmem(mem_addr: *mut i8, a: i16x32, mask: u32); - #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.256"] - fn vpmovuswbmem256(mem_addr: *mut i8, a: i16x16, mask: u16); - #[link_name = "llvm.x86.avx512.mask.pmovus.wb.mem.128"] - fn vpmovuswbmem128(mem_addr: *mut i8, a: i16x8, mask: u8); } #[cfg(test)] diff --git a/stdarch/crates/core_arch/src/x86/avx512fp16.rs b/stdarch/crates/core_arch/src/x86/avx512fp16.rs index 27f06691c5500..8ddc3d29a3a11 100644 --- a/stdarch/crates/core_arch/src/x86/avx512fp16.rs +++ b/stdarch/crates/core_arch/src/x86/avx512fp16.rs @@ -247,7 +247,7 @@ pub const fn _mm512_setr_ph( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_setzero_ph() -> __m128h { unsafe { transmute(f16x8::ZERO) } @@ -258,7 +258,7 @@ pub const fn _mm_setzero_ph() -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_setzero_ph() -> __m256h { f16x16::ZERO.as_m256h() @@ -269,7 +269,7 @@ pub const fn _mm256_setzero_ph() -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_setzero_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_setzero_ph() -> __m512h { f16x32::ZERO.as_m512h() @@ -283,7 +283,7 @@ pub const fn _mm512_setzero_ph() -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_undefined_ph() -> __m128h { f16x8::ZERO.as_m128h() @@ -297,7 +297,7 @@ pub const fn _mm_undefined_ph() -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_undefined_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_undefined_ph() -> __m256h { f16x16::ZERO.as_m256h() @@ -311,7 +311,7 @@ pub const fn _mm256_undefined_ph() -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_undefined_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_undefined_ph() -> __m512h { f16x32::ZERO.as_m512h() @@ -323,7 +323,7 @@ pub const fn _mm512_undefined_ph() -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castpd_ph(a: __m128d) -> __m128h { unsafe { transmute(a) } @@ -335,7 +335,7 @@ pub const fn _mm_castpd_ph(a: __m128d) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castpd_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h { unsafe { transmute(a) } @@ -347,7 +347,7 @@ pub const fn _mm256_castpd_ph(a: __m256d) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castpd_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h { unsafe { transmute(a) } @@ -359,7 +359,7 @@ pub const fn _mm512_castpd_ph(a: __m512d) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_pd) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castph_pd(a: __m128h) -> __m128d { unsafe { transmute(a) } @@ -371,7 +371,7 @@ pub const fn _mm_castph_pd(a: __m128h) -> __m128d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_pd) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph_pd(a: __m256h) -> __m256d { unsafe { transmute(a) } @@ -383,7 +383,7 @@ pub const fn _mm256_castph_pd(a: __m256h) -> __m256d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_pd) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph_pd(a: __m512h) -> __m512d { unsafe { transmute(a) } @@ -395,7 +395,7 @@ pub const fn _mm512_castph_pd(a: __m512h) -> __m512d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castps_ph(a: __m128) -> __m128h { unsafe { transmute(a) } @@ -407,7 +407,7 @@ pub const fn _mm_castps_ph(a: __m128) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castps_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castps_ph(a: __m256) -> __m256h { unsafe { transmute(a) } @@ -419,7 +419,7 @@ pub const fn _mm256_castps_ph(a: __m256) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castps_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castps_ph(a: __m512) -> __m512h { unsafe { transmute(a) } @@ -431,7 +431,7 @@ pub const fn _mm512_castps_ph(a: __m512) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_ps) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castph_ps(a: __m128h) -> __m128 { unsafe { transmute(a) } @@ -443,7 +443,7 @@ pub const fn _mm_castph_ps(a: __m128h) -> __m128 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_ps) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph_ps(a: __m256h) -> __m256 { unsafe { transmute(a) } @@ -455,7 +455,7 @@ pub const fn _mm256_castph_ps(a: __m256h) -> __m256 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_ps) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph_ps(a: __m512h) -> __m512 { unsafe { transmute(a) } @@ -467,7 +467,7 @@ pub const fn _mm512_castph_ps(a: __m512h) -> __m512 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h { unsafe { transmute(a) } @@ -479,7 +479,7 @@ pub const fn _mm_castsi128_ph(a: __m128i) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castsi256_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h { unsafe { transmute(a) } @@ -491,7 +491,7 @@ pub const fn _mm256_castsi256_ph(a: __m256i) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castsi512_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h { unsafe { transmute(a) } @@ -503,7 +503,7 @@ pub const fn _mm512_castsi512_ph(a: __m512i) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castph_si128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_castph_si128(a: __m128h) -> __m128i { unsafe { transmute(a) } @@ -515,7 +515,7 @@ pub const fn _mm_castph_si128(a: __m128h) -> __m128i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph_si256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph_si256(a: __m256h) -> __m256i { unsafe { transmute(a) } @@ -527,7 +527,7 @@ pub const fn _mm256_castph_si256(a: __m256h) -> __m256i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph_si512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph_si512(a: __m512h) -> __m512i { unsafe { transmute(a) } @@ -539,7 +539,7 @@ pub const fn _mm512_castph_si512(a: __m512h) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph256_ph128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } @@ -551,7 +551,7 @@ pub const fn _mm256_castph256_ph128(a: __m256h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]) } @@ -563,7 +563,7 @@ pub const fn _mm512_castph512_ph128(a: __m512h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph512_ph256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h { unsafe { simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } @@ -576,7 +576,7 @@ pub const fn _mm512_castph512_ph256(a: __m512h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_castph128_ph256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h { unsafe { @@ -595,7 +595,7 @@ pub const fn _mm256_castph128_ph256(a: __m128h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph128_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h { unsafe { @@ -617,7 +617,7 @@ pub const fn _mm512_castph128_ph512(a: __m128h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_castph256_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h { unsafe { @@ -639,7 +639,7 @@ pub const fn _mm512_castph256_ph512(a: __m256h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_zextph128_ph256) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h { unsafe { @@ -658,7 +658,7 @@ pub const fn _mm256_zextph128_ph256(a: __m128h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph256_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h { unsafe { @@ -680,7 +680,7 @@ pub const fn _mm512_zextph256_ph512(a: __m256h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_zextph128_ph512) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_zextph128_ph512(a: __m128h) -> __m512h { unsafe { @@ -730,7 +730,7 @@ macro_rules! cmp_asm { // FIXME: use LLVM intrinsics #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmp_ph_mask(a: __m128h, b: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -746,7 +746,7 @@ pub fn _mm_cmp_ph_mask(a: __m128h, b: __m128h) -> __mmask8 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmp_ph_mask(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -761,7 +761,7 @@ pub fn _mm_mask_cmp_ph_mask(k1: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cmp_ph_mask(a: __m256h, b: __m256h) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -777,7 +777,7 @@ pub fn _mm256_cmp_ph_mask(a: __m256h, b: __m256h) -> __mmask16 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cmp_ph_mask( k1: __mmask16, a: __m256h, @@ -796,7 +796,7 @@ pub fn _mm256_mask_cmp_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmp_ph_mask(a: __m512h, b: __m512h) -> __mmask32 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -812,7 +812,7 @@ pub fn _mm512_cmp_ph_mask(a: __m512h, b: __m512h) -> __mmask32 #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmp_ph_mask( k1: __mmask32, a: __m512h, @@ -833,7 +833,7 @@ pub fn _mm512_mask_cmp_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmp_round_ph_mask( a: __m512h, b: __m512h, @@ -868,7 +868,7 @@ pub fn _mm512_cmp_round_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmp_round_ph_mask( k1: __mmask32, a: __m512h, @@ -903,7 +903,7 @@ pub fn _mm512_mask_cmp_round_ph_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmp_round_sh_mask(a: __m128h, b: __m128h) -> __mmask8 { static_assert_uimm_bits!(IMM5, 5); static_assert_sae!(SAE); @@ -918,7 +918,7 @@ pub fn _mm_cmp_round_sh_mask(a: __m128h, b: __m #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmp_round_sh_mask( k1: __mmask8, a: __m128h, @@ -938,7 +938,7 @@ pub fn _mm_mask_cmp_round_sh_mask( #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmp_sh_mask(a: __m128h, b: __m128h) -> __mmask8 { static_assert_uimm_bits!(IMM5, 5); _mm_cmp_round_sh_mask::(a, b) @@ -951,7 +951,7 @@ pub fn _mm_cmp_sh_mask(a: __m128h, b: __m128h) -> __mmask8 { #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmp_sh_mask(k1: __mmask8, a: __m128h, b: __m128h) -> __mmask8 { static_assert_uimm_bits!(IMM5, 5); _mm_mask_cmp_round_sh_mask::(k1, a, b) @@ -965,7 +965,7 @@ pub fn _mm_mask_cmp_sh_mask(k1: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comi_round_sh(a: __m128h, b: __m128h) -> i32 { unsafe { static_assert_uimm_bits!(IMM5, 5); @@ -981,7 +981,7 @@ pub fn _mm_comi_round_sh(a: __m128h, b: __m128h #[inline] #[target_feature(enable = "avx512fp16")] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comi_sh(a: __m128h, b: __m128h) -> i32 { static_assert_uimm_bits!(IMM5, 5); _mm_comi_round_sh::(a, b) @@ -993,7 +993,7 @@ pub fn _mm_comi_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comieq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_EQ_OS>(a, b) } @@ -1004,7 +1004,7 @@ pub fn _mm_comieq_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comige_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GE_OS>(a, b) } @@ -1015,7 +1015,7 @@ pub fn _mm_comige_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comigt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GT_OS>(a, b) } @@ -1026,7 +1026,7 @@ pub fn _mm_comigt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comile_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LE_OS>(a, b) } @@ -1037,7 +1037,7 @@ pub fn _mm_comile_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comilt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LT_OS>(a, b) } @@ -1048,7 +1048,7 @@ pub fn _mm_comilt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comineq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_NEQ_US>(a, b) } @@ -1059,7 +1059,7 @@ pub fn _mm_comineq_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomieq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_EQ_OQ>(a, b) } @@ -1070,7 +1070,7 @@ pub fn _mm_ucomieq_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomige_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GE_OQ>(a, b) } @@ -1081,7 +1081,7 @@ pub fn _mm_ucomige_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomigt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_GT_OQ>(a, b) } @@ -1092,7 +1092,7 @@ pub fn _mm_ucomigt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomile_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LE_OQ>(a, b) } @@ -1103,7 +1103,7 @@ pub fn _mm_ucomile_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomilt_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_LT_OQ>(a, b) } @@ -1114,7 +1114,7 @@ pub fn _mm_ucomilt_sh(a: __m128h, b: __m128h) -> i32 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomineq_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_ucomineq_sh(a: __m128h, b: __m128h) -> i32 { _mm_comi_sh::<_CMP_NEQ_UQ>(a, b) } @@ -1248,7 +1248,7 @@ pub const unsafe fn _mm512_loadu_ph(mem_addr: *const f16) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_move_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1267,7 +1267,7 @@ pub const fn _mm_mask_move_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_move_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1285,7 +1285,7 @@ pub const fn _mm_maskz_move_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_sh) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_move_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1399,7 +1399,7 @@ pub const unsafe fn _mm512_storeu_ph(mem_addr: *mut f16, a: __m512h) { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_add(a, b) } @@ -1412,7 +1412,7 @@ pub const fn _mm_add_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1428,7 +1428,7 @@ pub const fn _mm_mask_add_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1443,7 +1443,7 @@ pub const fn _mm_maskz_add_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_add(a, b) } @@ -1456,7 +1456,7 @@ pub const fn _mm256_add_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1472,7 +1472,7 @@ pub const fn _mm256_mask_add_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1487,7 +1487,7 @@ pub const fn _mm256_maskz_add_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_add(a, b) } @@ -1500,7 +1500,7 @@ pub const fn _mm512_add_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1516,7 +1516,7 @@ pub const fn _mm512_mask_add_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1539,7 +1539,7 @@ pub const fn _mm512_maskz_add_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_add_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -1562,7 +1562,7 @@ pub fn _mm512_add_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_add_round_ph( src: __m512h, k: __mmask32, @@ -1590,7 +1590,7 @@ pub fn _mm512_mask_add_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_add_round_ph( k: __mmask32, a: __m512h, @@ -1618,7 +1618,7 @@ pub fn _mm512_maskz_add_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_add_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_add_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -1640,7 +1640,7 @@ pub fn _mm_add_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_add_round_sh( src: __m128h, k: __mmask8, @@ -1669,7 +1669,7 @@ pub fn _mm_mask_add_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_add_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_add_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -1682,7 +1682,7 @@ pub fn _mm_maskz_add_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) + _mm_cvtsh_h(b)) } @@ -1696,7 +1696,7 @@ pub const fn _mm_add_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1719,7 +1719,7 @@ pub const fn _mm_mask_add_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vaddsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1739,7 +1739,7 @@ pub const fn _mm_maskz_add_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_sub(a, b) } @@ -1752,7 +1752,7 @@ pub const fn _mm_sub_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1768,7 +1768,7 @@ pub const fn _mm_mask_sub_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -1783,7 +1783,7 @@ pub const fn _mm_maskz_sub_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_sub(a, b) } @@ -1796,7 +1796,7 @@ pub const fn _mm256_sub_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1812,7 +1812,7 @@ pub const fn _mm256_mask_sub_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -1827,7 +1827,7 @@ pub const fn _mm256_maskz_sub_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_sub(a, b) } @@ -1840,7 +1840,7 @@ pub const fn _mm512_sub_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1856,7 +1856,7 @@ pub const fn _mm512_mask_sub_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -1879,7 +1879,7 @@ pub const fn _mm512_maskz_sub_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_sub_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -1902,7 +1902,7 @@ pub fn _mm512_sub_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_sub_round_ph( src: __m512h, k: __mmask32, @@ -1931,7 +1931,7 @@ pub fn _mm512_mask_sub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_sub_round_ph( k: __mmask32, a: __m512h, @@ -1959,7 +1959,7 @@ pub fn _mm512_maskz_sub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sub_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_sub_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -1981,7 +1981,7 @@ pub fn _mm_sub_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sub_round_sh( src: __m128h, k: __mmask8, @@ -2010,7 +2010,7 @@ pub fn _mm_mask_sub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sub_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_sub_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -2023,7 +2023,7 @@ pub fn _mm_maskz_sub_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) - _mm_cvtsh_h(b)) } @@ -2037,7 +2037,7 @@ pub const fn _mm_sub_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2060,7 +2060,7 @@ pub const fn _mm_mask_sub_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsubsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2080,7 +2080,7 @@ pub const fn _mm_maskz_sub_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_mul(a, b) } @@ -2093,7 +2093,7 @@ pub const fn _mm_mul_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2109,7 +2109,7 @@ pub const fn _mm_mask_mul_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2124,7 +2124,7 @@ pub const fn _mm_maskz_mul_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_mul(a, b) } @@ -2137,7 +2137,7 @@ pub const fn _mm256_mul_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2153,7 +2153,7 @@ pub const fn _mm256_mask_mul_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2168,7 +2168,7 @@ pub const fn _mm256_maskz_mul_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_mul(a, b) } @@ -2181,7 +2181,7 @@ pub const fn _mm512_mul_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2197,7 +2197,7 @@ pub const fn _mm512_mask_mul_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2220,7 +2220,7 @@ pub const fn _mm512_maskz_mul_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mul_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -2243,7 +2243,7 @@ pub fn _mm512_mul_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_mul_round_ph( src: __m512h, k: __mmask32, @@ -2272,7 +2272,7 @@ pub fn _mm512_mask_mul_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_mul_round_ph( k: __mmask32, a: __m512h, @@ -2300,7 +2300,7 @@ pub fn _mm512_maskz_mul_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_mul_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -2322,7 +2322,7 @@ pub fn _mm_mul_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_round_sh( src: __m128h, k: __mmask8, @@ -2351,7 +2351,7 @@ pub fn _mm_mask_mul_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_mul_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -2364,7 +2364,7 @@ pub fn _mm_maskz_mul_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) * _mm_cvtsh_h(b)) } @@ -2378,7 +2378,7 @@ pub const fn _mm_mul_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2401,7 +2401,7 @@ pub const fn _mm_mask_mul_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmulsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2421,7 +2421,7 @@ pub const fn _mm_maskz_mul_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_div(a, b) } @@ -2434,7 +2434,7 @@ pub const fn _mm_div_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2450,7 +2450,7 @@ pub const fn _mm_mask_div_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2465,7 +2465,7 @@ pub const fn _mm_maskz_div_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { simd_div(a, b) } @@ -2478,7 +2478,7 @@ pub const fn _mm256_div_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2494,7 +2494,7 @@ pub const fn _mm256_mask_div_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { @@ -2509,7 +2509,7 @@ pub const fn _mm256_maskz_div_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { simd_div(a, b) } @@ -2522,7 +2522,7 @@ pub const fn _mm512_div_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2538,7 +2538,7 @@ pub const fn _mm512_mask_div_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { @@ -2561,7 +2561,7 @@ pub const fn _mm512_maskz_div_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_div_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -2584,7 +2584,7 @@ pub fn _mm512_div_round_ph(a: __m512h, b: __m512h) -> __m51 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_div_round_ph( src: __m512h, k: __mmask32, @@ -2613,7 +2613,7 @@ pub fn _mm512_mask_div_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_div_round_ph( k: __mmask32, a: __m512h, @@ -2641,7 +2641,7 @@ pub fn _mm512_maskz_div_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_div_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_div_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -2663,7 +2663,7 @@ pub fn _mm_div_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_div_round_sh( src: __m128h, k: __mmask8, @@ -2692,7 +2692,7 @@ pub fn _mm_mask_div_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_div_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_div_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -2705,7 +2705,7 @@ pub fn _mm_maskz_div_round_sh(k: __mmask8, a: __m128h, b: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h { unsafe { simd_insert!(a, 0, _mm_cvtsh_h(a) / _mm_cvtsh_h(b)) } @@ -2719,7 +2719,7 @@ pub const fn _mm_div_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2742,7 +2742,7 @@ pub const fn _mm_mask_div_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vdivsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { @@ -2764,7 +2764,7 @@ pub const fn _mm_maskz_div_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_pch(_mm_undefined_ph(), 0xff, a, b) } @@ -2777,7 +2777,7 @@ pub fn _mm_mul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { transmute(vfmulcph_128(transmute(a), transmute(b), transmute(src), k)) } } @@ -2790,7 +2790,7 @@ pub fn _mm_mask_mul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_pch(_mm_setzero_ph(), k, a, b) } @@ -2803,7 +2803,7 @@ pub fn _mm_maskz_mul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_mask_mul_pch(_mm256_undefined_ph(), 0xff, a, b) } @@ -2816,7 +2816,7 @@ pub fn _mm256_mul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { unsafe { transmute(vfmulcph_256(transmute(a), transmute(b), transmute(src), k)) } } @@ -2829,7 +2829,7 @@ pub fn _mm256_mask_mul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_mul_pch(_mm256_setzero_ph(), k, a, b) } @@ -2842,7 +2842,7 @@ pub fn _mm256_maskz_mul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_pch(_mm512_undefined_ph(), 0xffff, a, b) } @@ -2855,7 +2855,7 @@ pub fn _mm512_mul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -2868,7 +2868,7 @@ pub fn _mm512_mask_mul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) - #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_pch(_mm512_setzero_ph(), k, a, b) } @@ -2890,7 +2890,7 @@ pub fn _mm512_maskz_mul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_mul_round_pch::(_mm512_undefined_ph(), 0xffff, a, b) @@ -2913,7 +2913,7 @@ pub fn _mm512_mul_round_pch(a: __m512h, b: __m512h) -> __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_mul_round_pch( src: __m512h, k: __mmask16, @@ -2949,7 +2949,7 @@ pub fn _mm512_mask_mul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_mul_round_pch( k: __mmask16, a: __m512h, @@ -2968,7 +2968,7 @@ pub fn _mm512_maskz_mul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -2982,7 +2982,7 @@ pub fn _mm_mul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -2996,7 +2996,7 @@ pub fn _mm_mask_mul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_sch(f16x8::ZERO.as_m128h(), k, a, b) } @@ -3019,7 +3019,7 @@ pub fn _mm_maskz_mul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_mul_round_sch::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -3043,7 +3043,7 @@ pub fn _mm_mul_round_sch(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_mul_round_sch( src: __m128h, k: __mmask8, @@ -3080,7 +3080,7 @@ pub fn _mm_mask_mul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_mul_round_sch( k: __mmask8, a: __m128h, @@ -3098,7 +3098,7 @@ pub fn _mm_maskz_mul_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_mul_pch(a, b) } @@ -3111,7 +3111,7 @@ pub fn _mm_fmul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_pch(src, k, a, b) } @@ -3124,7 +3124,7 @@ pub fn _mm_mask_fmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_mul_pch(k, a, b) } @@ -3137,7 +3137,7 @@ pub fn _mm_maskz_fmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_mul_pch(a, b) } @@ -3150,7 +3150,7 @@ pub fn _mm256_fmul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_mul_pch(src, k, a, b) } @@ -3163,7 +3163,7 @@ pub fn _mm256_mask_fmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_maskz_mul_pch(k, a, b) } @@ -3175,7 +3175,7 @@ pub fn _mm256_maskz_fmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_mul_pch(a, b) } @@ -3188,7 +3188,7 @@ pub fn _mm512_fmul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_mul_pch(src, k, a, b) } @@ -3201,7 +3201,7 @@ pub fn _mm512_mask_fmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_maskz_mul_pch(k, a, b) } @@ -3221,7 +3221,7 @@ pub fn _mm512_maskz_fmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mul_round_pch::(a, b) @@ -3243,7 +3243,7 @@ pub fn _mm512_fmul_round_pch(a: __m512h, b: __m512h) -> __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmul_round_pch( src: __m512h, k: __mmask16, @@ -3270,7 +3270,7 @@ pub fn _mm512_mask_fmul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmul_round_pch( k: __mmask16, a: __m512h, @@ -3288,7 +3288,7 @@ pub fn _mm512_maskz_fmul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_mul_sch(a, b) } @@ -3301,7 +3301,7 @@ pub fn _mm_fmul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_mul_sch(src, k, a, b) } @@ -3314,7 +3314,7 @@ pub fn _mm_mask_fmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_mul_sch(k, a, b) } @@ -3335,7 +3335,7 @@ pub fn _mm_maskz_fmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mul_round_sch::(a, b) @@ -3358,7 +3358,7 @@ pub fn _mm_fmul_round_sch(a: __m128h, b: __m128h) -> __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmul_round_sch( src: __m128h, k: __mmask8, @@ -3386,7 +3386,7 @@ pub fn _mm_mask_fmul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmul_round_sch( k: __mmask8, a: __m128h, @@ -3405,7 +3405,7 @@ pub fn _mm_maskz_fmul_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_pch(_mm_undefined_ph(), 0xff, a, b) } @@ -3419,7 +3419,7 @@ pub fn _mm_cmul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { transmute(vfcmulcph_128(transmute(a), transmute(b), transmute(src), k)) } } @@ -3433,7 +3433,7 @@ pub fn _mm_mask_cmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_pch(_mm_setzero_ph(), k, a, b) } @@ -3447,7 +3447,7 @@ pub fn _mm_maskz_cmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_mask_cmul_pch(_mm256_undefined_ph(), 0xff, a, b) } @@ -3461,7 +3461,7 @@ pub fn _mm256_cmul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { unsafe { transmute(vfcmulcph_256(transmute(a), transmute(b), transmute(src), k)) } } @@ -3475,7 +3475,7 @@ pub fn _mm256_mask_cmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_cmul_pch(_mm256_setzero_ph(), k, a, b) } @@ -3489,7 +3489,7 @@ pub fn _mm256_maskz_cmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_pch(_mm512_undefined_ph(), 0xffff, a, b) } @@ -3503,7 +3503,7 @@ pub fn _mm512_cmul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_round_pch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -3517,7 +3517,7 @@ pub fn _mm512_mask_cmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_pch(_mm512_setzero_ph(), k, a, b) } @@ -3540,7 +3540,7 @@ pub fn _mm512_maskz_cmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cmul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_cmul_round_pch::(_mm512_undefined_ph(), 0xffff, a, b) @@ -3564,7 +3564,7 @@ pub fn _mm512_cmul_round_pch(a: __m512h, b: __m512h) -> __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cmul_round_pch( src: __m512h, k: __mmask16, @@ -3601,7 +3601,7 @@ pub fn _mm512_mask_cmul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cmul_round_pch( k: __mmask16, a: __m512h, @@ -3619,7 +3619,7 @@ pub fn _mm512_maskz_cmul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -3633,7 +3633,7 @@ pub fn _mm_cmul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_round_sch::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -3647,7 +3647,7 @@ pub fn _mm_mask_cmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_sch(f16x8::ZERO.as_m128h(), k, a, b) } @@ -3669,7 +3669,7 @@ pub fn _mm_maskz_cmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cmul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_cmul_round_sch::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -3693,7 +3693,7 @@ pub fn _mm_cmul_round_sch(a: __m128h, b: __m128h) -> __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cmul_round_sch( src: __m128h, k: __mmask8, @@ -3730,7 +3730,7 @@ pub fn _mm_mask_cmul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cmul_round_sch( k: __mmask8, a: __m128h, @@ -3749,7 +3749,7 @@ pub fn _mm_maskz_cmul_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h { _mm_cmul_pch(a, b) } @@ -3763,7 +3763,7 @@ pub fn _mm_fcmul_pch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_pch(src, k, a, b) } @@ -3777,7 +3777,7 @@ pub fn _mm_mask_fcmul_pch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_cmul_pch(k, a, b) } @@ -3791,7 +3791,7 @@ pub fn _mm_maskz_fcmul_pch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h { _mm256_cmul_pch(a, b) } @@ -3805,7 +3805,7 @@ pub fn _mm256_fcmul_pch(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_cmul_pch(src, k, a, b) } @@ -3819,7 +3819,7 @@ pub fn _mm256_mask_fcmul_pch(src: __m256h, k: __mmask8, a: __m256h, b: __m256h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { _mm256_maskz_cmul_pch(k, a, b) } @@ -3833,7 +3833,7 @@ pub fn _mm256_maskz_fcmul_pch(k: __mmask8, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h { _mm512_cmul_pch(a, b) } @@ -3847,7 +3847,7 @@ pub fn _mm512_fcmul_pch(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_cmul_pch(src, k, a, b) } @@ -3861,7 +3861,7 @@ pub fn _mm512_mask_fcmul_pch(src: __m512h, k: __mmask16, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { _mm512_maskz_cmul_pch(k, a, b) } @@ -3883,7 +3883,7 @@ pub fn _mm512_maskz_fcmul_pch(k: __mmask16, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmul_round_pch(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_cmul_round_pch::(a, b) @@ -3907,7 +3907,7 @@ pub fn _mm512_fcmul_round_pch(a: __m512h, b: __m512h) -> __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmul_round_pch( src: __m512h, k: __mmask16, @@ -3936,7 +3936,7 @@ pub fn _mm512_mask_fcmul_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmul_round_pch( k: __mmask16, a: __m512h, @@ -3955,7 +3955,7 @@ pub fn _mm512_maskz_fcmul_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h { _mm_cmul_sch(a, b) } @@ -3969,7 +3969,7 @@ pub fn _mm_fcmul_sch(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_cmul_sch(src, k, a, b) } @@ -3983,7 +3983,7 @@ pub fn _mm_mask_fcmul_sch(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_maskz_cmul_sch(k, a, b) } @@ -4005,7 +4005,7 @@ pub fn _mm_maskz_fcmul_sch(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmul_round_sch(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_cmul_round_sch::(a, b) @@ -4029,7 +4029,7 @@ pub fn _mm_fcmul_round_sch(a: __m128h, b: __m128h) -> __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmul_round_sch( src: __m128h, k: __mmask8, @@ -4058,7 +4058,7 @@ pub fn _mm_mask_fcmul_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmulcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmul_round_sch( k: __mmask8, a: __m128h, @@ -4074,7 +4074,7 @@ pub fn _mm_maskz_fcmul_round_sch( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_abs_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_abs_ph(v2: __m128h) -> __m128h { unsafe { transmute(_mm_and_si128(transmute(v2), _mm_set1_epi16(i16::MAX))) } @@ -4086,7 +4086,7 @@ pub const fn _mm_abs_ph(v2: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_abs_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h { unsafe { transmute(_mm256_and_si256(transmute(v2), _mm256_set1_epi16(i16::MAX))) } @@ -4098,7 +4098,7 @@ pub const fn _mm256_abs_ph(v2: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_abs_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h { unsafe { transmute(_mm512_and_si512(transmute(v2), _mm512_set1_epi16(i16::MAX))) } @@ -4112,7 +4112,7 @@ pub const fn _mm512_abs_ph(v2: __m512h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_conj_pch(a: __m128h) -> __m128h { unsafe { transmute(_mm_xor_si128(transmute(a), _mm_set1_epi32(i32::MIN))) } @@ -4126,7 +4126,7 @@ pub const fn _mm_conj_pch(a: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { @@ -4143,7 +4143,7 @@ pub const fn _mm_mask_conj_pch(src: __m128h, k: __mmask8, a: __m128h) -> __m128h /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_conj_pch(_mm_setzero_ph(), k, a) @@ -4156,7 +4156,7 @@ pub const fn _mm_maskz_conj_pch(k: __mmask8, a: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_conj_pch(a: __m256h) -> __m256h { unsafe { transmute(_mm256_xor_si256(transmute(a), _mm256_set1_epi32(i32::MIN))) } @@ -4170,7 +4170,7 @@ pub const fn _mm256_conj_pch(a: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m256h { unsafe { @@ -4187,7 +4187,7 @@ pub const fn _mm256_mask_conj_pch(src: __m256h, k: __mmask8, a: __m256h) -> __m2 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_conj_pch) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h { _mm256_mask_conj_pch(_mm256_setzero_ph(), k, a) @@ -4200,7 +4200,7 @@ pub const fn _mm256_maskz_conj_pch(k: __mmask8, a: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_conj_pch) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_conj_pch(a: __m512h) -> __m512h { unsafe { transmute(_mm512_xor_si512(transmute(a), _mm512_set1_epi32(i32::MIN))) } @@ -4214,7 +4214,7 @@ pub const fn _mm512_conj_pch(a: __m512h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_conj_pch) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m512h { unsafe { @@ -4231,7 +4231,7 @@ pub const fn _mm512_mask_conj_pch(src: __m512h, k: __mmask16, a: __m512h) -> __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_conj_pch) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h { _mm512_mask_conj_pch(_mm512_setzero_ph(), k, a) @@ -4245,7 +4245,7 @@ pub const fn _mm512_maskz_conj_pch(k: __mmask16, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_mask3_fmadd_pch(a, b, c, 0xff) } @@ -4259,7 +4259,7 @@ pub fn _mm_fmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { let r: __m128 = transmute(_mm_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4276,7 +4276,7 @@ pub fn _mm_mask_fmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { transmute(vfmaddcph_mask3_128( @@ -4297,7 +4297,7 @@ pub fn _mm_mask3_fmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { transmute(vfmaddcph_maskz_128( @@ -4317,7 +4317,7 @@ pub fn _mm_maskz_fmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { _mm256_mask3_fmadd_pch(a, b, c, 0xff) } @@ -4331,7 +4331,7 @@ pub fn _mm256_fmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h { unsafe { let r: __m256 = transmute(_mm256_mask3_fmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4348,7 +4348,7 @@ pub fn _mm256_mask_fmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h { unsafe { transmute(vfmaddcph_mask3_256( @@ -4369,7 +4369,7 @@ pub fn _mm256_mask3_fmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { transmute(vfmaddcph_maskz_256( @@ -4389,7 +4389,7 @@ pub fn _mm256_maskz_fmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) - #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -4403,7 +4403,7 @@ pub fn _mm512_fmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h { _mm512_mask_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -4417,7 +4417,7 @@ pub fn _mm512_mask_fmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) - #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h { _mm512_mask3_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -4431,7 +4431,7 @@ pub fn _mm512_mask3_fmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_maskz_fmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -4453,7 +4453,7 @@ pub fn _mm512_maskz_fmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmadd_round_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask3_fmadd_round_pch::(a, b, c, 0xffff) @@ -4477,7 +4477,7 @@ pub fn _mm512_fmadd_round_pch(a: __m512h, b: __m512h, c: __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmadd_round_pch( a: __m512h, k: __mmask16, @@ -4509,7 +4509,7 @@ pub fn _mm512_mask_fmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmadd_round_pch( a: __m512h, b: __m512h, @@ -4546,7 +4546,7 @@ pub fn _mm512_mask3_fmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmadd_round_pch( k: __mmask16, a: __m512h, @@ -4574,7 +4574,7 @@ pub fn _mm512_maskz_fmadd_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -4589,7 +4589,7 @@ pub fn _mm_fmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { _mm_mask_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -4604,7 +4604,7 @@ pub fn _mm_mask_fmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { _mm_mask3_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -4619,7 +4619,7 @@ pub fn _mm_mask3_fmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_maskz_fmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -4641,7 +4641,7 @@ pub fn _mm_maskz_fmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_round_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -4674,7 +4674,7 @@ pub fn _mm_fmadd_round_sch(a: __m128h, b: __m128h, c: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_round_sch( a: __m128h, k: __mmask8, @@ -4708,7 +4708,7 @@ pub fn _mm_mask_fmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_round_sch( a: __m128h, b: __m128h, @@ -4742,7 +4742,7 @@ pub fn _mm_mask3_fmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_round_sch( k: __mmask8, a: __m128h, @@ -4770,7 +4770,7 @@ pub fn _mm_maskz_fmadd_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_mask3_fcmadd_pch(a, b, c, 0xff) } @@ -4785,7 +4785,7 @@ pub fn _mm_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { let r: __m128 = transmute(_mm_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4803,7 +4803,7 @@ pub fn _mm_mask_fcmadd_pch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { transmute(vfcmaddcph_mask3_128( @@ -4825,7 +4825,7 @@ pub fn _mm_mask3_fcmadd_pch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { transmute(vfcmaddcph_maskz_128( @@ -4846,7 +4846,7 @@ pub fn _mm_maskz_fcmadd_pch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { _mm256_mask3_fcmadd_pch(a, b, c, 0xff) } @@ -4861,7 +4861,7 @@ pub fn _mm256_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) -> __m256h { unsafe { let r: __m256 = transmute(_mm256_mask3_fcmadd_pch(a, b, c, k)); // using `0xff` would have been fine here, but this is what CLang does @@ -4879,7 +4879,7 @@ pub fn _mm256_mask_fcmadd_pch(a: __m256h, k: __mmask8, b: __m256h, c: __m256h) - #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) -> __m256h { unsafe { transmute(vfcmaddcph_mask3_256( @@ -4901,7 +4901,7 @@ pub fn _mm256_mask3_fcmadd_pch(a: __m256h, b: __m256h, c: __m256h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { transmute(vfcmaddcph_maskz_256( @@ -4922,7 +4922,7 @@ pub fn _mm256_maskz_fcmadd_pch(k: __mmask8, a: __m256h, b: __m256h, c: __m256h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -4937,7 +4937,7 @@ pub fn _mm512_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) -> __m512h { _mm512_mask_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -4952,7 +4952,7 @@ pub fn _mm512_mask_fcmadd_pch(a: __m512h, k: __mmask16, b: __m512h, c: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) -> __m512h { _mm512_mask3_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -4967,7 +4967,7 @@ pub fn _mm512_mask3_fcmadd_pch(a: __m512h, b: __m512h, c: __m512h, k: __mmask16) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_maskz_fcmadd_round_pch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -4990,7 +4990,7 @@ pub fn _mm512_maskz_fcmadd_pch(k: __mmask16, a: __m512h, b: __m512h, c: __m512h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fcmadd_round_pch(a: __m512h, b: __m512h, c: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask3_fcmadd_round_pch::(a, b, c, 0xffff) @@ -5015,7 +5015,7 @@ pub fn _mm512_fcmadd_round_pch(a: __m512h, b: __m512h, c: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fcmadd_round_pch( a: __m512h, k: __mmask16, @@ -5048,7 +5048,7 @@ pub fn _mm512_mask_fcmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fcmadd_round_pch( a: __m512h, b: __m512h, @@ -5086,7 +5086,7 @@ pub fn _mm512_mask3_fcmadd_round_pch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fcmadd_round_pch( k: __mmask16, a: __m512h, @@ -5115,7 +5115,7 @@ pub fn _mm512_maskz_fcmadd_round_pch( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c) } @@ -5131,7 +5131,7 @@ pub fn _mm_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { _mm_mask_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, k, b, c) } @@ -5147,7 +5147,7 @@ pub fn _mm_mask_fcmadd_sch(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { _mm_mask3_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(a, b, c, k) } @@ -5163,7 +5163,7 @@ pub fn _mm_mask3_fcmadd_sch(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_maskz_fcmadd_round_sch::<_MM_FROUND_CUR_DIRECTION>(k, a, b, c) } @@ -5187,7 +5187,7 @@ pub fn _mm_maskz_fcmadd_sch(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fcmadd_round_sch(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -5221,7 +5221,7 @@ pub fn _mm_fcmadd_round_sch(a: __m128h, b: __m128h, c: __m1 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fcmadd_round_sch( a: __m128h, k: __mmask8, @@ -5256,7 +5256,7 @@ pub fn _mm_mask_fcmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fcmadd_round_sch( a: __m128h, b: __m128h, @@ -5291,7 +5291,7 @@ pub fn _mm_mask3_fcmadd_round_sch( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfcmaddcsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fcmadd_round_sch( k: __mmask8, a: __m128h, @@ -5317,7 +5317,7 @@ pub fn _mm_maskz_fcmadd_round_sch( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(a, b, c) } @@ -5331,7 +5331,7 @@ pub const fn _mm_fmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), a) } @@ -5345,7 +5345,7 @@ pub const fn _mm_mask_fmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), c) } @@ -5359,7 +5359,7 @@ pub const fn _mm_mask3_fmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmadd_ph(a, b, c), _mm_setzero_ph()) } @@ -5372,7 +5372,7 @@ pub const fn _mm_maskz_fmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(a, b, c) } @@ -5386,7 +5386,7 @@ pub const fn _mm256_fmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), a) } @@ -5400,7 +5400,7 @@ pub const fn _mm256_mask_fmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), c) } @@ -5414,7 +5414,7 @@ pub const fn _mm256_mask3_fmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmadd_ph(a, b, c), _mm256_setzero_ph()) } @@ -5427,7 +5427,7 @@ pub const fn _mm256_maskz_fmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(a, b, c) } @@ -5441,7 +5441,7 @@ pub const fn _mm512_fmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), a) } @@ -5455,7 +5455,7 @@ pub const fn _mm512_mask_fmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), c) } @@ -5469,7 +5469,7 @@ pub const fn _mm512_mask3_fmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmadd_ph(a, b, c), _mm512_setzero_ph()) } @@ -5491,7 +5491,7 @@ pub const fn _mm512_maskz_fmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmadd_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -5516,7 +5516,7 @@ pub fn _mm512_fmadd_round_ph(a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmadd_round_ph( a: __m512h, k: __mmask32, @@ -5546,7 +5546,7 @@ pub fn _mm512_mask_fmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmadd_round_ph( a: __m512h, b: __m512h, @@ -5576,7 +5576,7 @@ pub fn _mm512_mask3_fmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmadd_round_ph( k: __mmask32, a: __m512h, @@ -5601,7 +5601,7 @@ pub fn _mm512_maskz_fmadd_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -5622,7 +5622,7 @@ pub const fn _mm_fmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -5645,7 +5645,7 @@ pub const fn _mm_mask_fmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -5668,7 +5668,7 @@ pub const fn _mm_mask3_fmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -5700,7 +5700,7 @@ pub const fn _mm_maskz_fmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmadd_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -5730,7 +5730,7 @@ pub fn _mm_fmadd_round_sh(a: __m128h, b: __m128h, c: __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmadd_round_sh( a: __m128h, k: __mmask8, @@ -5767,7 +5767,7 @@ pub fn _mm_mask_fmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmadd_round_sh( a: __m128h, b: __m128h, @@ -5804,7 +5804,7 @@ pub fn _mm_mask3_fmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmadd_round_sh( k: __mmask8, a: __m128h, @@ -5832,7 +5832,7 @@ pub fn _mm_maskz_fmadd_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -5846,7 +5846,7 @@ pub const fn _mm_fmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), a) } @@ -5860,7 +5860,7 @@ pub const fn _mm_mask_fmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), c) } @@ -5874,7 +5874,7 @@ pub const fn _mm_mask3_fmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsub_ph(a, b, c), _mm_setzero_ph()) } @@ -5887,7 +5887,7 @@ pub const fn _mm_maskz_fmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -5901,7 +5901,7 @@ pub const fn _mm256_fmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), a) } @@ -5915,7 +5915,7 @@ pub const fn _mm256_mask_fmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), c) } @@ -5929,7 +5929,7 @@ pub const fn _mm256_mask3_fmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsub_ph(a, b, c), _mm256_setzero_ph()) } @@ -5942,7 +5942,7 @@ pub const fn _mm256_maskz_fmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(a, b, simd_neg(c)) } @@ -5956,7 +5956,7 @@ pub const fn _mm512_fmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), a) } @@ -5970,7 +5970,7 @@ pub const fn _mm512_mask_fmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), c) } @@ -5984,7 +5984,7 @@ pub const fn _mm512_mask3_fmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsub_ph(a, b, c), _mm512_setzero_ph()) } @@ -6006,7 +6006,7 @@ pub const fn _mm512_maskz_fmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmsub_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -6031,7 +6031,7 @@ pub fn _mm512_fmsub_round_ph(a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmsub_round_ph( a: __m512h, k: __mmask32, @@ -6061,7 +6061,7 @@ pub fn _mm512_mask_fmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmsub_round_ph( a: __m512h, b: __m512h, @@ -6091,7 +6091,7 @@ pub fn _mm512_mask3_fmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmsub_round_ph( k: __mmask32, a: __m512h, @@ -6116,7 +6116,7 @@ pub fn _mm512_maskz_fmsub_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6137,7 +6137,7 @@ pub const fn _mm_fmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6160,7 +6160,7 @@ pub const fn _mm_mask_fmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -6183,7 +6183,7 @@ pub const fn _mm_mask3_fmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6215,7 +6215,7 @@ pub const fn _mm_maskz_fmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fmsub_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -6245,7 +6245,7 @@ pub fn _mm_fmsub_round_sh(a: __m128h, b: __m128h, c: __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fmsub_round_sh( a: __m128h, k: __mmask8, @@ -6282,7 +6282,7 @@ pub fn _mm_mask_fmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fmsub_round_sh( a: __m128h, b: __m128h, @@ -6311,7 +6311,7 @@ pub fn _mm_mask3_fmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fmsub_round_sh( k: __mmask8, a: __m128h, @@ -6338,7 +6338,7 @@ pub fn _mm_maskz_fmsub_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(simd_neg(a), b, c) } @@ -6352,7 +6352,7 @@ pub const fn _mm_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), a) } @@ -6366,7 +6366,7 @@ pub const fn _mm_mask_fnmadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), c) } @@ -6380,7 +6380,7 @@ pub const fn _mm_mask3_fnmadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmadd_ph(a, b, c), _mm_setzero_ph()) } @@ -6393,7 +6393,7 @@ pub const fn _mm_maskz_fnmadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(simd_neg(a), b, c) } @@ -6407,7 +6407,7 @@ pub const fn _mm256_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), a) } @@ -6421,7 +6421,7 @@ pub const fn _mm256_mask_fnmadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), c) } @@ -6435,7 +6435,7 @@ pub const fn _mm256_mask3_fnmadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mma #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmadd_ph(a, b, c), _mm256_setzero_ph()) } @@ -6448,7 +6448,7 @@ pub const fn _mm256_maskz_fnmadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(simd_neg(a), b, c) } @@ -6462,7 +6462,7 @@ pub const fn _mm512_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), a) } @@ -6476,7 +6476,7 @@ pub const fn _mm512_mask_fnmadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), c) } @@ -6490,7 +6490,7 @@ pub const fn _mm512_mask3_fnmadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mma #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmadd_ph(a, b, c), _mm512_setzero_ph()) } @@ -6512,7 +6512,7 @@ pub const fn _mm512_maskz_fnmadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fnmadd_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -6537,7 +6537,7 @@ pub fn _mm512_fnmadd_round_ph(a: __m512h, b: __m512h, c: __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fnmadd_round_ph( a: __m512h, k: __mmask32, @@ -6567,7 +6567,7 @@ pub fn _mm512_mask_fnmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fnmadd_round_ph( a: __m512h, b: __m512h, @@ -6597,7 +6597,7 @@ pub fn _mm512_mask3_fnmadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fnmadd_round_ph( k: __mmask32, a: __m512h, @@ -6622,7 +6622,7 @@ pub fn _mm512_maskz_fnmadd_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6643,7 +6643,7 @@ pub const fn _mm_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6666,7 +6666,7 @@ pub const fn _mm_mask_fnmadd_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -6689,7 +6689,7 @@ pub const fn _mm_mask3_fnmadd_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -6721,7 +6721,7 @@ pub const fn _mm_maskz_fnmadd_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fnmadd_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -6751,7 +6751,7 @@ pub fn _mm_fnmadd_round_sh(a: __m128h, b: __m128h, c: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fnmadd_round_sh( a: __m128h, k: __mmask8, @@ -6788,7 +6788,7 @@ pub fn _mm_mask_fnmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fnmadd_round_sh( a: __m128h, b: __m128h, @@ -6825,7 +6825,7 @@ pub fn _mm_mask3_fnmadd_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fnmadd_round_sh( k: __mmask8, a: __m128h, @@ -6852,7 +6852,7 @@ pub fn _mm_maskz_fnmadd_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -6866,7 +6866,7 @@ pub const fn _mm_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), a) } @@ -6880,7 +6880,7 @@ pub const fn _mm_mask_fnmsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), c) } @@ -6894,7 +6894,7 @@ pub const fn _mm_mask3_fnmsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fnmsub_ph(a, b, c), _mm_setzero_ph()) } @@ -6907,7 +6907,7 @@ pub const fn _mm_maskz_fnmsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -6921,7 +6921,7 @@ pub const fn _mm256_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), a) } @@ -6935,7 +6935,7 @@ pub const fn _mm256_mask_fnmsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m2 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), c) } @@ -6949,7 +6949,7 @@ pub const fn _mm256_mask3_fnmsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mma #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fnmsub_ph(a, b, c), _mm256_setzero_ph()) } @@ -6962,7 +6962,7 @@ pub const fn _mm256_maskz_fnmsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_fma(simd_neg(a), b, simd_neg(c)) } @@ -6976,7 +6976,7 @@ pub const fn _mm512_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), a) } @@ -6990,7 +6990,7 @@ pub const fn _mm512_mask_fnmsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), c) } @@ -7004,7 +7004,7 @@ pub const fn _mm512_mask3_fnmsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mma #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fnmsub_ph(a, b, c), _mm512_setzero_ph()) } @@ -7026,7 +7026,7 @@ pub const fn _mm512_maskz_fnmsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fnmsub_round_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -7051,7 +7051,7 @@ pub fn _mm512_fnmsub_round_ph(a: __m512h, b: __m512h, c: __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fnmsub_round_ph( a: __m512h, k: __mmask32, @@ -7081,7 +7081,7 @@ pub fn _mm512_mask_fnmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fnmsub_round_ph( a: __m512h, b: __m512h, @@ -7111,7 +7111,7 @@ pub fn _mm512_mask3_fnmsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fnmsub_round_ph( k: __mmask32, a: __m512h, @@ -7136,7 +7136,7 @@ pub fn _mm512_maskz_fnmsub_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7157,7 +7157,7 @@ pub const fn _mm_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7180,7 +7180,7 @@ pub const fn _mm_mask_fnmsub_sh(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { @@ -7203,7 +7203,7 @@ pub const fn _mm_mask3_fnmsub_sh(a: __m128h, b: __m128h, c: __m128h, k: __mmask8 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7235,7 +7235,7 @@ pub const fn _mm_maskz_fnmsub_sh(k: __mmask8, a: __m128h, b: __m128h, c: __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fnmsub_round_sh(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -7265,7 +7265,7 @@ pub fn _mm_fnmsub_round_sh(a: __m128h, b: __m128h, c: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fnmsub_round_sh( a: __m128h, k: __mmask8, @@ -7302,7 +7302,7 @@ pub fn _mm_mask_fnmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask3_fnmsub_round_sh( a: __m128h, b: __m128h, @@ -7339,7 +7339,7 @@ pub fn _mm_mask3_fnmsub_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfnmsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_fnmsub_round_sh( k: __mmask8, a: __m128h, @@ -7366,7 +7366,7 @@ pub fn _mm_maskz_fnmsub_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { @@ -7384,7 +7384,7 @@ pub const fn _mm_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), a) } @@ -7398,7 +7398,7 @@ pub const fn _mm_mask_fmaddsub_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), c) } @@ -7412,7 +7412,7 @@ pub const fn _mm_mask3_fmaddsub_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmaddsub_ph(a, b, c), _mm_setzero_ph()) } @@ -7425,7 +7425,7 @@ pub const fn _mm_maskz_fmaddsub_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { @@ -7447,7 +7447,7 @@ pub const fn _mm256_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), a) } @@ -7461,7 +7461,7 @@ pub const fn _mm256_mask_fmaddsub_ph(a: __m256h, k: __mmask16, b: __m256h, c: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), c) } @@ -7475,7 +7475,7 @@ pub const fn _mm256_mask3_fmaddsub_ph(a: __m256h, b: __m256h, c: __m256h, k: __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmaddsub_ph(a, b, c), _mm256_setzero_ph()) } @@ -7488,7 +7488,7 @@ pub const fn _mm256_maskz_fmaddsub_ph(k: __mmask16, a: __m256h, b: __m256h, c: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { @@ -7513,7 +7513,7 @@ pub const fn _mm512_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), a) } @@ -7527,7 +7527,7 @@ pub const fn _mm512_mask_fmaddsub_ph(a: __m512h, k: __mmask32, b: __m512h, c: __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), c) } @@ -7541,7 +7541,7 @@ pub const fn _mm512_mask3_fmaddsub_ph(a: __m512h, b: __m512h, c: __m512h, k: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmaddsub_ph(a, b, c), _mm512_setzero_ph()) } @@ -7563,7 +7563,7 @@ pub const fn _mm512_maskz_fmaddsub_ph(k: __mmask32, a: __m512h, b: __m512h, c: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmaddsub_round_ph( a: __m512h, b: __m512h, @@ -7592,7 +7592,7 @@ pub fn _mm512_fmaddsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmaddsub_round_ph( a: __m512h, k: __mmask32, @@ -7622,7 +7622,7 @@ pub fn _mm512_mask_fmaddsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmaddsub_round_ph( a: __m512h, b: __m512h, @@ -7652,7 +7652,7 @@ pub fn _mm512_mask3_fmaddsub_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmaddsub, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmaddsub_round_ph( k: __mmask32, a: __m512h, @@ -7676,7 +7676,7 @@ pub fn _mm512_maskz_fmaddsub_round_ph( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { _mm_fmaddsub_ph(a, b, unsafe { simd_neg(c) }) @@ -7690,7 +7690,7 @@ pub const fn _mm_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), a) } @@ -7704,7 +7704,7 @@ pub const fn _mm_mask_fmsubadd_ph(a: __m128h, k: __mmask8, b: __m128h, c: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmask8) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), c) } @@ -7718,7 +7718,7 @@ pub const fn _mm_mask3_fmsubadd_ph(a: __m128h, b: __m128h, c: __m128h, k: __mmas #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_fmsubadd_ph(a, b, c), _mm_setzero_ph()) } @@ -7731,7 +7731,7 @@ pub const fn _mm_maskz_fmsubadd_ph(k: __mmask8, a: __m128h, b: __m128h, c: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { _mm256_fmaddsub_ph(a, b, unsafe { simd_neg(c) }) @@ -7745,7 +7745,7 @@ pub const fn _mm256_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), a) } @@ -7759,7 +7759,7 @@ pub const fn _mm256_mask_fmsubadd_ph(a: __m256h, k: __mmask16, b: __m256h, c: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __mmask16) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), c) } @@ -7773,7 +7773,7 @@ pub const fn _mm256_mask3_fmsubadd_ph(a: __m256h, b: __m256h, c: __m256h, k: __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_fmsubadd_ph(a, b, c), _mm256_setzero_ph()) } @@ -7786,7 +7786,7 @@ pub const fn _mm256_maskz_fmsubadd_ph(k: __mmask16, a: __m256h, b: __m256h, c: _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { _mm512_fmaddsub_ph(a, b, unsafe { simd_neg(c) }) @@ -7800,7 +7800,7 @@ pub const fn _mm512_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), a) } @@ -7814,7 +7814,7 @@ pub const fn _mm512_mask_fmsubadd_ph(a: __m512h, k: __mmask32, b: __m512h, c: __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __mmask32) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), c) } @@ -7828,7 +7828,7 @@ pub const fn _mm512_mask3_fmsubadd_ph(a: __m512h, b: __m512h, c: __m512h, k: __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_fmsubadd_ph(a, b, c), _mm512_setzero_ph()) } @@ -7850,7 +7850,7 @@ pub const fn _mm512_maskz_fmsubadd_ph(k: __mmask32, a: __m512h, b: __m512h, c: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fmsubadd_round_ph( a: __m512h, b: __m512h, @@ -7879,7 +7879,7 @@ pub fn _mm512_fmsubadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fmsubadd_round_ph( a: __m512h, k: __mmask32, @@ -7909,7 +7909,7 @@ pub fn _mm512_mask_fmsubadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask3_fmsubadd_round_ph( a: __m512h, b: __m512h, @@ -7939,7 +7939,7 @@ pub fn _mm512_mask3_fmsubadd_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfmsubadd, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_fmsubadd_round_ph( k: __mmask32, a: __m512h, @@ -7963,7 +7963,7 @@ pub fn _mm512_maskz_fmsubadd_round_ph( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rcp_ph(a: __m128h) -> __m128h { _mm_mask_rcp_ph(_mm_undefined_ph(), 0xff, a) } @@ -7976,7 +7976,7 @@ pub fn _mm_rcp_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { vrcpph_128(a, src, k) } } @@ -7989,7 +7989,7 @@ pub fn _mm_mask_rcp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_rcp_ph(_mm_setzero_ph(), k, a) } @@ -8001,7 +8001,7 @@ pub fn _mm_maskz_rcp_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_rcp_ph(a: __m256h) -> __m256h { _mm256_mask_rcp_ph(_mm256_undefined_ph(), 0xffff, a) } @@ -8014,7 +8014,7 @@ pub fn _mm256_rcp_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { vrcpph_256(a, src, k) } } @@ -8027,7 +8027,7 @@ pub fn _mm256_mask_rcp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h { _mm256_mask_rcp_ph(_mm256_setzero_ph(), k, a) } @@ -8039,7 +8039,7 @@ pub fn _mm256_maskz_rcp_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_rcp_ph(a: __m512h) -> __m512h { _mm512_mask_rcp_ph(_mm512_undefined_ph(), 0xffffffff, a) } @@ -8052,7 +8052,7 @@ pub fn _mm512_rcp_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { unsafe { vrcpph_512(a, src, k) } } @@ -8065,7 +8065,7 @@ pub fn _mm512_mask_rcp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_rcp_ph(_mm512_setzero_ph(), k, a) } @@ -8079,7 +8079,7 @@ pub fn _mm512_maskz_rcp_ph(k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -8093,7 +8093,7 @@ pub fn _mm_rcp_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { vrcpsh(a, b, src, k) } } @@ -8107,7 +8107,7 @@ pub fn _mm_mask_rcp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrcpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_rcp_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8120,7 +8120,7 @@ pub fn _mm_maskz_rcp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h { _mm_mask_rsqrt_ph(_mm_undefined_ph(), 0xff, a) } @@ -8134,7 +8134,7 @@ pub fn _mm_rsqrt_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { vrsqrtph_128(a, src, k) } } @@ -8148,7 +8148,7 @@ pub fn _mm_mask_rsqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_rsqrt_ph(_mm_setzero_ph(), k, a) } @@ -8161,7 +8161,7 @@ pub fn _mm_maskz_rsqrt_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h { _mm256_mask_rsqrt_ph(_mm256_undefined_ph(), 0xffff, a) } @@ -8175,7 +8175,7 @@ pub fn _mm256_rsqrt_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { vrsqrtph_256(a, src, k) } } @@ -8189,7 +8189,7 @@ pub fn _mm256_mask_rsqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h { _mm256_mask_rsqrt_ph(_mm256_setzero_ph(), k, a) } @@ -8202,7 +8202,7 @@ pub fn _mm256_maskz_rsqrt_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h { _mm512_mask_rsqrt_ph(_mm512_undefined_ph(), 0xffffffff, a) } @@ -8216,7 +8216,7 @@ pub fn _mm512_rsqrt_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { unsafe { vrsqrtph_512(a, src, k) } } @@ -8230,7 +8230,7 @@ pub fn _mm512_mask_rsqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_rsqrt_ph(_mm512_setzero_ph(), k, a) } @@ -8244,7 +8244,7 @@ pub fn _mm512_maskz_rsqrt_ph(k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -8258,7 +8258,7 @@ pub fn _mm_rsqrt_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { vrsqrtsh(a, b, src, k) } } @@ -8272,7 +8272,7 @@ pub fn _mm_mask_rsqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_rsqrt_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8284,7 +8284,7 @@ pub fn _mm_maskz_rsqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sqrt_ph(a: __m128h) -> __m128h { unsafe { simd_fsqrt(a) } } @@ -8296,7 +8296,7 @@ pub fn _mm_sqrt_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), src) } } @@ -8308,7 +8308,7 @@ pub fn _mm_mask_sqrt_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_sqrt_ph(a), _mm_setzero_ph()) } } @@ -8320,7 +8320,7 @@ pub fn _mm_maskz_sqrt_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h { unsafe { simd_fsqrt(a) } } @@ -8332,7 +8332,7 @@ pub fn _mm256_sqrt_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), src) } } @@ -8344,7 +8344,7 @@ pub fn _mm256_mask_sqrt_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_sqrt_ph(a), _mm256_setzero_ph()) } } @@ -8356,7 +8356,7 @@ pub fn _mm256_maskz_sqrt_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h { unsafe { simd_fsqrt(a) } } @@ -8368,7 +8368,7 @@ pub fn _mm512_sqrt_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), src) } } @@ -8380,7 +8380,7 @@ pub fn _mm512_mask_sqrt_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_sqrt_ph(a), _mm512_setzero_ph()) } } @@ -8400,7 +8400,7 @@ pub fn _mm512_maskz_sqrt_ph(k: __mmask32, a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_sqrt_round_ph(a: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -8423,7 +8423,7 @@ pub fn _mm512_sqrt_round_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_sqrt_round_ph( src: __m512h, k: __mmask32, @@ -8450,7 +8450,7 @@ pub fn _mm512_mask_sqrt_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_sqrt_round_ph(k: __mmask32, a: __m512h) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -8466,7 +8466,7 @@ pub fn _mm512_maskz_sqrt_round_ph(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -8479,7 +8479,7 @@ pub fn _mm_sqrt_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_sqrt_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -8492,7 +8492,7 @@ pub fn _mm_mask_sqrt_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_sqrt_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8513,7 +8513,7 @@ pub fn _mm_maskz_sqrt_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_sqrt_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_sqrt_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -8535,7 +8535,7 @@ pub fn _mm_sqrt_round_sh(a: __m128h, b: __m128h) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_sqrt_round_sh( src: __m128h, k: __mmask8, @@ -8564,7 +8564,7 @@ pub fn _mm_mask_sqrt_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vsqrtsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_sqrt_round_sh( k: __mmask8, a: __m128h, @@ -8582,7 +8582,7 @@ pub fn _mm_maskz_sqrt_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { vmaxph_128(a, b) } } @@ -8596,7 +8596,7 @@ pub fn _mm_max_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), src) } } @@ -8610,7 +8610,7 @@ pub fn _mm_mask_max_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_max_ph(a, b), _mm_setzero_ph()) } } @@ -8623,7 +8623,7 @@ pub fn _mm_maskz_max_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { vmaxph_256(a, b) } } @@ -8637,7 +8637,7 @@ pub fn _mm256_max_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), src) } } @@ -8651,7 +8651,7 @@ pub fn _mm256_mask_max_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_max_ph(a, b), _mm256_setzero_ph()) } } @@ -8664,7 +8664,7 @@ pub fn _mm256_maskz_max_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h { _mm512_max_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b) } @@ -8678,7 +8678,7 @@ pub fn _mm512_max_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), src) } } @@ -8692,7 +8692,7 @@ pub fn _mm512_mask_max_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_max_ph(a, b), _mm512_setzero_ph()) } } @@ -8707,7 +8707,7 @@ pub fn _mm512_maskz_max_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_max_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -8725,7 +8725,7 @@ pub fn _mm512_max_round_ph(a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_max_round_ph( src: __m512h, k: __mmask32, @@ -8748,7 +8748,7 @@ pub fn _mm512_mask_max_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vmaxph, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_max_round_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -8765,7 +8765,7 @@ pub fn _mm512_maskz_max_round_ph(k: __mmask32, a: __m512h, b: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_max_sh(_mm_undefined_ph(), 0xff, a, b) } @@ -8779,7 +8779,7 @@ pub fn _mm_max_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_max_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -8793,7 +8793,7 @@ pub fn _mm_mask_max_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_max_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -8808,7 +8808,7 @@ pub fn _mm_maskz_max_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_max_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_max_round_sh::(_mm_undefined_ph(), 0xff, a, b) @@ -8825,7 +8825,7 @@ pub fn _mm_max_round_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_max_round_sh( src: __m128h, k: __mmask8, @@ -8849,7 +8849,7 @@ pub fn _mm_mask_max_round_sh( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vmaxsh, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_max_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_max_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -8863,7 +8863,7 @@ pub fn _mm_maskz_max_round_sh(k: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h { unsafe { vminph_128(a, b) } } @@ -8877,7 +8877,7 @@ pub fn _mm_min_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), src) } } @@ -8891,7 +8891,7 @@ pub fn _mm_mask_min_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, _mm_min_ph(a, b), _mm_setzero_ph()) } } @@ -8904,7 +8904,7 @@ pub fn _mm_maskz_min_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h { unsafe { vminph_256(a, b) } } @@ -8918,7 +8918,7 @@ pub fn _mm256_min_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), src) } } @@ -8932,7 +8932,7 @@ pub fn _mm256_mask_min_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_min_ph(a, b), _mm256_setzero_ph()) } } @@ -8945,7 +8945,7 @@ pub fn _mm256_maskz_min_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h { _mm512_min_round_ph::<_MM_FROUND_CUR_DIRECTION>(a, b) } @@ -8959,7 +8959,7 @@ pub fn _mm512_min_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), src) } } @@ -8973,7 +8973,7 @@ pub fn _mm512_mask_min_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_min_ph(a, b), _mm512_setzero_ph()) } } @@ -8987,7 +8987,7 @@ pub fn _mm512_maskz_min_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_min_round_ph(a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -9005,7 +9005,7 @@ pub fn _mm512_min_round_ph(a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_min_round_ph( src: __m512h, k: __mmask32, @@ -9028,7 +9028,7 @@ pub fn _mm512_mask_min_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vminph, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_min_round_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { static_assert_sae!(SAE); @@ -9045,7 +9045,7 @@ pub fn _mm512_maskz_min_round_ph(k: __mmask32, a: __m512h, b: __ #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_min_sh(_mm_undefined_ph(), 0xff, a, b) } @@ -9059,7 +9059,7 @@ pub fn _mm_min_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_min_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -9073,7 +9073,7 @@ pub fn _mm_mask_min_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_min_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -9088,7 +9088,7 @@ pub fn _mm_maskz_min_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_min_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_min_round_sh::(_mm_undefined_ph(), 0xff, a, b) @@ -9105,7 +9105,7 @@ pub fn _mm_min_round_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_min_round_sh( src: __m128h, k: __mmask8, @@ -9129,7 +9129,7 @@ pub fn _mm_mask_min_round_sh( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vminsh, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_min_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_min_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -9143,7 +9143,7 @@ pub fn _mm_maskz_min_round_sh(k: __mmask8, a: __m128h, b: __m128 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getexp_ph(a: __m128h) -> __m128h { _mm_mask_getexp_ph(_mm_undefined_ph(), 0xff, a) } @@ -9157,7 +9157,7 @@ pub fn _mm_getexp_ph(a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { vgetexpph_128(a, src, k) } } @@ -9171,7 +9171,7 @@ pub fn _mm_mask_getexp_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h { _mm_mask_getexp_ph(_mm_setzero_ph(), k, a) } @@ -9184,7 +9184,7 @@ pub fn _mm_maskz_getexp_ph(k: __mmask8, a: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_getexp_ph(a: __m256h) -> __m256h { _mm256_mask_getexp_ph(_mm256_undefined_ph(), 0xffff, a) } @@ -9198,7 +9198,7 @@ pub fn _mm256_getexp_ph(a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { vgetexpph_256(a, src, k) } } @@ -9212,7 +9212,7 @@ pub fn _mm256_mask_getexp_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h { _mm256_mask_getexp_ph(_mm256_setzero_ph(), k, a) } @@ -9225,7 +9225,7 @@ pub fn _mm256_maskz_getexp_ph(k: __mmask16, a: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_getexp_ph(a: __m512h) -> __m512h { _mm512_mask_getexp_ph(_mm512_undefined_ph(), 0xffffffff, a) } @@ -9239,7 +9239,7 @@ pub fn _mm512_getexp_ph(a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_getexp_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a) } @@ -9253,7 +9253,7 @@ pub fn _mm512_mask_getexp_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h { _mm512_mask_getexp_ph(_mm512_setzero_ph(), k, a) } @@ -9268,7 +9268,7 @@ pub fn _mm512_maskz_getexp_ph(k: __mmask32, a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_getexp_round_ph(a: __m512h) -> __m512h { static_assert_sae!(SAE); _mm512_mask_getexp_round_ph::(_mm512_undefined_ph(), 0xffffffff, a) @@ -9284,7 +9284,7 @@ pub fn _mm512_getexp_round_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_getexp_round_ph( src: __m512h, k: __mmask32, @@ -9306,7 +9306,7 @@ pub fn _mm512_mask_getexp_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpph, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_getexp_round_ph(k: __mmask32, a: __m512h) -> __m512h { static_assert_sae!(SAE); _mm512_mask_getexp_round_ph::(_mm512_setzero_ph(), k, a) @@ -9321,7 +9321,7 @@ pub fn _mm512_maskz_getexp_round_ph(k: __mmask32, a: __m512h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -9336,7 +9336,7 @@ pub fn _mm_getexp_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_getexp_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -9351,7 +9351,7 @@ pub fn _mm_mask_getexp_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_getexp_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -9367,7 +9367,7 @@ pub fn _mm_maskz_getexp_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getexp_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_getexp_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -9384,7 +9384,7 @@ pub fn _mm_getexp_round_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_getexp_round_sh( src: __m128h, k: __mmask8, @@ -9408,7 +9408,7 @@ pub fn _mm_mask_getexp_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vgetexpsh, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_getexp_round_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_sae!(SAE); _mm_mask_getexp_round_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -9436,7 +9436,7 @@ pub fn _mm_maskz_getexp_round_sh(k: __mmask8, a: __m128h, b: __m #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vgetmantph, NORM = 0, SIGN = 0))] #[rustc_legacy_const_generics(1, 2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_getmant_ph( a: __m128h, ) -> __m128h { @@ -9468,7 +9468,7 @@ pub fn _mm_getmant_ph( a: __m256h, ) -> __m256h { @@ -9574,7 +9574,7 @@ pub fn _mm256_getmant_ph( a: __m512h, ) -> __m512h { @@ -9680,7 +9680,7 @@ pub fn _mm512_getmant_ph( a: __m128h, b: __m128h, @@ -9911,7 +9911,7 @@ pub fn _mm_getmant_sh(a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_ph::(_mm_undefined_ph(), 0xff, a) @@ -10131,7 +10131,7 @@ pub fn _mm_roundscale_ph(a: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_roundscale_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -10156,7 +10156,7 @@ pub fn _mm_mask_roundscale_ph(src: __m128h, k: __mmask8, a: __m #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_roundscale_ph(k: __mmask8, a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_ph::(_mm_setzero_ph(), k, a) @@ -10178,7 +10178,7 @@ pub fn _mm_maskz_roundscale_ph(k: __mmask8, a: __m128h) -> __m1 #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_roundscale_ph(a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_roundscale_ph::(_mm256_undefined_ph(), 0xffff, a) @@ -10201,7 +10201,7 @@ pub fn _mm256_roundscale_ph(a: __m256h) -> __m256h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_roundscale_ph( src: __m256h, k: __mmask16, @@ -10230,7 +10230,7 @@ pub fn _mm256_mask_roundscale_ph( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_roundscale_ph(k: __mmask16, a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_roundscale_ph::(_mm256_setzero_ph(), k, a) @@ -10252,7 +10252,7 @@ pub fn _mm256_maskz_roundscale_ph(k: __mmask16, a: __m256h) -> #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_roundscale_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_roundscale_ph::(_mm512_undefined_ph(), 0xffffffff, a) @@ -10275,7 +10275,7 @@ pub fn _mm512_roundscale_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_roundscale_ph( src: __m512h, k: __mmask32, @@ -10302,7 +10302,7 @@ pub fn _mm512_mask_roundscale_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_roundscale_ph(k: __mmask32, a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_roundscale_ph::(_mm512_setzero_ph(), k, a) @@ -10325,7 +10325,7 @@ pub fn _mm512_maskz_roundscale_ph(k: __mmask32, a: __m512h) -> #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(1, 2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_roundscale_round_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -10350,7 +10350,7 @@ pub fn _mm512_roundscale_round_ph(a: __m512h) - #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_roundscale_round_ph( src: __m512h, k: __mmask32, @@ -10380,7 +10380,7 @@ pub fn _mm512_mask_roundscale_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscaleph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_roundscale_round_ph( k: __mmask32, a: __m512h, @@ -10407,7 +10407,7 @@ pub fn _mm512_maskz_roundscale_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_roundscale_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -10430,7 +10430,7 @@ pub fn _mm_roundscale_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_roundscale_sh( src: __m128h, k: __mmask8, @@ -10458,7 +10458,7 @@ pub fn _mm_mask_roundscale_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_roundscale_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_roundscale_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -10483,7 +10483,7 @@ pub fn _mm_maskz_roundscale_sh(k: __mmask8, a: __m128h, b: __m1 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_roundscale_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -10509,7 +10509,7 @@ pub fn _mm_roundscale_round_sh(a: __m128h, b: _ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_roundscale_round_sh( src: __m128h, k: __mmask8, @@ -10542,7 +10542,7 @@ pub fn _mm_mask_roundscale_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vrndscalesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_roundscale_round_sh( k: __mmask8, a: __m128h, @@ -10560,7 +10560,7 @@ pub fn _mm_maskz_roundscale_round_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_ph(_mm_undefined_ph(), 0xff, a, b) } @@ -10572,7 +10572,7 @@ pub fn _mm_scalef_ph(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { vscalefph_128(a, b, src, k) } } @@ -10584,7 +10584,7 @@ pub fn _mm_mask_scalef_ph(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_ph(_mm_setzero_ph(), k, a, b) } @@ -10596,7 +10596,7 @@ pub fn _mm_maskz_scalef_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h { _mm256_mask_scalef_ph(_mm256_undefined_ph(), 0xffff, a, b) } @@ -10608,7 +10608,7 @@ pub fn _mm256_scalef_ph(a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { vscalefph_256(a, b, src, k) } } @@ -10620,7 +10620,7 @@ pub fn _mm256_mask_scalef_ph(src: __m256h, k: __mmask16, a: __m256h, b: __m256h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { _mm256_mask_scalef_ph(_mm256_setzero_ph(), k, a, b) } @@ -10632,7 +10632,7 @@ pub fn _mm256_maskz_scalef_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h { _mm512_mask_scalef_ph(_mm512_undefined_ph(), 0xffffffff, a, b) } @@ -10644,7 +10644,7 @@ pub fn _mm512_scalef_ph(a: __m512h, b: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_scalef_round_ph::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -10656,7 +10656,7 @@ pub fn _mm512_mask_scalef_ph(src: __m512h, k: __mmask32, a: __m512h, b: __m512h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { _mm512_mask_scalef_ph(_mm512_setzero_ph(), k, a, b) } @@ -10677,7 +10677,7 @@ pub fn _mm512_maskz_scalef_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_scalef_round_ph(a: __m512h, b: __m512h) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_scalef_round_ph::(_mm512_undefined_ph(), 0xffffffff, a, b) @@ -10699,7 +10699,7 @@ pub fn _mm512_scalef_round_ph(a: __m512h, b: __m512h) -> __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_scalef_round_ph( src: __m512h, k: __mmask32, @@ -10728,7 +10728,7 @@ pub fn _mm512_mask_scalef_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_scalef_round_ph( k: __mmask32, a: __m512h, @@ -10746,7 +10746,7 @@ pub fn _mm512_maskz_scalef_round_ph( #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -10759,7 +10759,7 @@ pub fn _mm_scalef_sh(a: __m128h, b: __m128h) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_round_sh::<_MM_FROUND_CUR_DIRECTION>(src, k, a, b) } @@ -10772,7 +10772,7 @@ pub fn _mm_mask_scalef_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { _mm_mask_scalef_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -10794,7 +10794,7 @@ pub fn _mm_maskz_scalef_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_scalef_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_scalef_round_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -10817,7 +10817,7 @@ pub fn _mm_scalef_round_sh(a: __m128h, b: __m128h) -> __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_scalef_round_sh( src: __m128h, k: __mmask8, @@ -10847,7 +10847,7 @@ pub fn _mm_mask_scalef_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vscalefsh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_scalef_round_sh( k: __mmask8, a: __m128h, @@ -10873,7 +10873,7 @@ pub fn _mm_maskz_scalef_round_sh( #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_reduce_ph(a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_ph::(_mm_undefined_ph(), 0xff, a) @@ -10896,7 +10896,7 @@ pub fn _mm_reduce_ph(a: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_reduce_ph(src: __m128h, k: __mmask8, a: __m128h) -> __m128h { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -10921,7 +10921,7 @@ pub fn _mm_mask_reduce_ph(src: __m128h, k: __mmask8, a: __m128h #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_reduce_ph(k: __mmask8, a: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_ph::(_mm_setzero_ph(), k, a) @@ -10943,7 +10943,7 @@ pub fn _mm_maskz_reduce_ph(k: __mmask8, a: __m128h) -> __m128h #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_reduce_ph(a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_reduce_ph::(_mm256_undefined_ph(), 0xffff, a) @@ -10966,7 +10966,7 @@ pub fn _mm256_reduce_ph(a: __m256h) -> __m256h { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_reduce_ph(src: __m256h, k: __mmask16, a: __m256h) -> __m256h { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -10991,7 +10991,7 @@ pub fn _mm256_mask_reduce_ph(src: __m256h, k: __mmask16, a: __m #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_reduce_ph(k: __mmask16, a: __m256h) -> __m256h { static_assert_uimm_bits!(IMM8, 8); _mm256_mask_reduce_ph::(_mm256_setzero_ph(), k, a) @@ -11013,7 +11013,7 @@ pub fn _mm256_maskz_reduce_ph(k: __mmask16, a: __m256h) -> __m2 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_reduce_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_ph::(_mm512_undefined_ph(), 0xffffffff, a) @@ -11036,7 +11036,7 @@ pub fn _mm512_reduce_ph(a: __m512h) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_reduce_ph(src: __m512h, k: __mmask32, a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_round_ph::(src, k, a) @@ -11059,7 +11059,7 @@ pub fn _mm512_mask_reduce_ph(src: __m512h, k: __mmask32, a: __m #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_reduce_ph(k: __mmask32, a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); _mm512_mask_reduce_ph::(_mm512_setzero_ph(), k, a) @@ -11083,7 +11083,7 @@ pub fn _mm512_maskz_reduce_ph(k: __mmask32, a: __m512h) -> __m5 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(1, 2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_reduce_round_ph(a: __m512h) -> __m512h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -11109,7 +11109,7 @@ pub fn _mm512_reduce_round_ph(a: __m512h) -> __ #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_reduce_round_ph( src: __m512h, k: __mmask32, @@ -11141,7 +11141,7 @@ pub fn _mm512_mask_reduce_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreduceph, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_reduce_round_ph( k: __mmask32, a: __m512h, @@ -11168,7 +11168,7 @@ pub fn _mm512_maskz_reduce_round_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_reduce_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -11192,7 +11192,7 @@ pub fn _mm_reduce_sh(a: __m128h, b: __m128h) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_reduce_sh( src: __m128h, k: __mmask8, @@ -11221,7 +11221,7 @@ pub fn _mm_mask_reduce_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_reduce_sh(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); _mm_mask_reduce_sh::(f16x8::ZERO.as_m128h(), k, a, b) @@ -11246,7 +11246,7 @@ pub fn _mm_maskz_reduce_sh(k: __mmask8, a: __m128h, b: __m128h) #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(2, 3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_reduce_round_sh(a: __m128h, b: __m128h) -> __m128h { static_assert_uimm_bits!(IMM8, 8); static_assert_sae!(SAE); @@ -11273,7 +11273,7 @@ pub fn _mm_reduce_round_sh(a: __m128h, b: __m12 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(4, 5)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_reduce_round_sh( src: __m128h, k: __mmask8, @@ -11307,7 +11307,7 @@ pub fn _mm_mask_reduce_round_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vreducesh, IMM8 = 0, SAE = 8))] #[rustc_legacy_const_generics(3, 4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_reduce_round_sh( k: __mmask8, a: __m128h, @@ -11582,7 +11582,7 @@ macro_rules! fpclass_asm { // FIXME: use LLVM intrinsics #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fpclass_ph_mask(a: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11609,7 +11609,7 @@ pub fn _mm_fpclass_ph_mask(a: __m128h) -> __mmask8 { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fpclass_ph_mask(k1: __mmask8, a: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11635,7 +11635,7 @@ pub fn _mm_mask_fpclass_ph_mask(k1: __mmask8, a: __m128h) -> __ #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_fpclass_ph_mask(a: __m256h) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11662,7 +11662,7 @@ pub fn _mm256_fpclass_ph_mask(a: __m256h) -> __mmask16 { #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_fpclass_ph_mask(k1: __mmask16, a: __m256h) -> __mmask16 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11688,7 +11688,7 @@ pub fn _mm256_mask_fpclass_ph_mask(k1: __mmask16, a: __m256h) - #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_fpclass_ph_mask(a: __m512h) -> __mmask32 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11715,7 +11715,7 @@ pub fn _mm512_fpclass_ph_mask(a: __m512h) -> __mmask32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclassph, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_fpclass_ph_mask(k1: __mmask32, a: __m512h) -> __mmask32 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11741,7 +11741,7 @@ pub fn _mm512_mask_fpclass_ph_mask(k1: __mmask32, a: __m512h) - #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_fpclass_sh_mask(a: __m128h) -> __mmask8 { _mm_mask_fpclass_sh_mask::(0xff, a) } @@ -11765,7 +11765,7 @@ pub fn _mm_fpclass_sh_mask(a: __m128h) -> __mmask8 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vfpclasssh, IMM8 = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_fpclass_sh_mask(k1: __mmask8, a: __m128h) -> __mmask8 { unsafe { static_assert_uimm_bits!(IMM8, 8); @@ -11779,7 +11779,7 @@ pub fn _mm_mask_fpclass_sh_mask(k1: __mmask8, a: __m128h) -> __ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_blend_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { unsafe { simd_select_bitmask(k, b, a) } @@ -11791,7 +11791,7 @@ pub const fn _mm_mask_blend_ph(k: __mmask8, a: __m128h, b: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_blend_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m256h { unsafe { simd_select_bitmask(k, b, a) } @@ -11803,7 +11803,7 @@ pub const fn _mm256_mask_blend_ph(k: __mmask16, a: __m256h, b: __m256h) -> __m25 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_blend_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m512h { unsafe { simd_select_bitmask(k, b, a) } @@ -11815,7 +11815,7 @@ pub const fn _mm512_mask_blend_ph(k: __mmask32, a: __m512h, b: __m512h) -> __m51 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutex2var_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h { _mm_castsi128_ph(_mm_permutex2var_epi16( _mm_castph_si128(a), @@ -11830,7 +11830,7 @@ pub fn _mm_permutex2var_ph(a: __m128h, idx: __m128i, b: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutex2var_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h { _mm256_castsi256_ph(_mm256_permutex2var_epi16( _mm256_castph_si256(a), @@ -11845,7 +11845,7 @@ pub fn _mm256_permutex2var_ph(a: __m256h, idx: __m256i, b: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex2var_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h { _mm512_castsi512_ph(_mm512_permutex2var_epi16( _mm512_castph_si512(a), @@ -11860,7 +11860,7 @@ pub fn _mm512_permutex2var_ph(a: __m512h, idx: __m512i, b: __m512h) -> __m512h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_permutexvar_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h { _mm_castsi128_ph(_mm_permutexvar_epi16(idx, _mm_castph_si128(a))) } @@ -11871,7 +11871,7 @@ pub fn _mm_permutexvar_ph(idx: __m128i, a: __m128h) -> __m128h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutexvar_ph) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h { _mm256_castsi256_ph(_mm256_permutexvar_epi16(idx, _mm256_castph_si256(a))) } @@ -11882,7 +11882,7 @@ pub fn _mm256_permutexvar_ph(idx: __m256i, a: __m256h) -> __m256h { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutexvar_ph) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h { _mm512_castsi512_ph(_mm512_permutexvar_epi16(idx, _mm512_castph_si512(a))) } @@ -11894,7 +11894,7 @@ pub fn _mm512_permutexvar_ph(idx: __m512i, a: __m512h) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h { unsafe { vcvtw2ph_128(a.as_i16x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -11907,7 +11907,7 @@ pub fn _mm_cvtepi16_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { simd_select_bitmask(k, _mm_cvtepi16_ph(a), src) } } @@ -11919,7 +11919,7 @@ pub fn _mm_mask_cvtepi16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepi16_ph(_mm_setzero_ph(), k, a) } @@ -11931,7 +11931,7 @@ pub fn _mm_maskz_cvtepi16_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h { unsafe { vcvtw2ph_256(a.as_i16x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -11944,7 +11944,7 @@ pub fn _mm256_cvtepi16_ph(a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_cvtepi16_ph(a), src) } } @@ -11956,7 +11956,7 @@ pub fn _mm256_mask_cvtepi16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h { _mm256_mask_cvtepi16_ph(_mm256_setzero_ph(), k, a) } @@ -11968,7 +11968,7 @@ pub fn _mm256_maskz_cvtepi16_ph(k: __mmask16, a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h { unsafe { vcvtw2ph_512(a.as_i16x32(), _MM_FROUND_CUR_DIRECTION) } } @@ -11981,7 +11981,7 @@ pub fn _mm512_cvtepi16_ph(a: __m512i) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_cvtepi16_ph(a), src) } } @@ -11993,7 +11993,7 @@ pub fn _mm512_mask_cvtepi16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h { _mm512_mask_cvtepi16_ph(_mm512_setzero_ph(), k, a) } @@ -12014,7 +12014,7 @@ pub fn _mm512_maskz_cvtepi16_ph(k: __mmask32, a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepi16_ph(a: __m512i) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -12039,7 +12039,7 @@ pub fn _mm512_cvt_roundepi16_ph(a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepi16_ph( src: __m512h, k: __mmask32, @@ -12067,7 +12067,7 @@ pub fn _mm512_mask_cvt_roundepi16_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepi16_ph(k: __mmask32, a: __m512i) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepi16_ph::(_mm512_setzero_ph(), k, a) @@ -12080,7 +12080,7 @@ pub fn _mm512_maskz_cvt_roundepi16_ph(k: __mmask32, a: __m5 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h { unsafe { vcvtuw2ph_128(a.as_u16x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12093,7 +12093,7 @@ pub fn _mm_cvtepu16_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { simd_select_bitmask(k, _mm_cvtepu16_ph(a), src) } } @@ -12105,7 +12105,7 @@ pub fn _mm_mask_cvtepu16_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepu16_ph(_mm_setzero_ph(), k, a) } @@ -12117,7 +12117,7 @@ pub fn _mm_maskz_cvtepu16_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h { unsafe { vcvtuw2ph_256(a.as_u16x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -12130,7 +12130,7 @@ pub fn _mm256_cvtepu16_ph(a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256h { unsafe { simd_select_bitmask(k, _mm256_cvtepu16_ph(a), src) } } @@ -12142,7 +12142,7 @@ pub fn _mm256_mask_cvtepu16_ph(src: __m256h, k: __mmask16, a: __m256i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h { _mm256_mask_cvtepu16_ph(_mm256_setzero_ph(), k, a) } @@ -12154,7 +12154,7 @@ pub fn _mm256_maskz_cvtepu16_ph(k: __mmask16, a: __m256i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h { unsafe { vcvtuw2ph_512(a.as_u16x32(), _MM_FROUND_CUR_DIRECTION) } } @@ -12167,7 +12167,7 @@ pub fn _mm512_cvtepu16_ph(a: __m512i) -> __m512h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512h { unsafe { simd_select_bitmask(k, _mm512_cvtepu16_ph(a), src) } } @@ -12179,7 +12179,7 @@ pub fn _mm512_mask_cvtepu16_ph(src: __m512h, k: __mmask32, a: __m512i) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h { _mm512_mask_cvtepu16_ph(_mm512_setzero_ph(), k, a) } @@ -12200,7 +12200,7 @@ pub fn _mm512_maskz_cvtepu16_ph(k: __mmask32, a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepu16_ph(a: __m512i) -> __m512h { unsafe { static_assert_rounding!(ROUNDING); @@ -12225,7 +12225,7 @@ pub fn _mm512_cvt_roundepu16_ph(a: __m512i) -> __m512h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepu16_ph( src: __m512h, k: __mmask32, @@ -12253,7 +12253,7 @@ pub fn _mm512_mask_cvt_roundepu16_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuw2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepu16_ph(k: __mmask32, a: __m512i) -> __m512h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepu16_ph::(_mm512_setzero_ph(), k, a) @@ -12266,7 +12266,7 @@ pub fn _mm512_maskz_cvt_roundepu16_ph(k: __mmask32, a: __m5 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h { _mm_mask_cvtepi32_ph(_mm_setzero_ph(), 0xff, a) } @@ -12279,7 +12279,7 @@ pub fn _mm_cvtepi32_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtdq2ph_128(a.as_i32x4(), src, k) } } @@ -12292,7 +12292,7 @@ pub fn _mm_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepi32_ph(_mm_setzero_ph(), k, a) } @@ -12304,7 +12304,7 @@ pub fn _mm_maskz_cvtepi32_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h { unsafe { vcvtdq2ph_256(a.as_i32x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12317,7 +12317,7 @@ pub fn _mm256_cvtepi32_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { simd_select_bitmask(k, _mm256_cvtepi32_ph(a), src) } } @@ -12329,7 +12329,7 @@ pub fn _mm256_mask_cvtepi32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepi32_ph(_mm_setzero_ph(), k, a) } @@ -12341,7 +12341,7 @@ pub fn _mm256_maskz_cvtepi32_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h { unsafe { vcvtdq2ph_512(a.as_i32x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -12354,7 +12354,7 @@ pub fn _mm512_cvtepi32_ph(a: __m512i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h { unsafe { simd_select_bitmask(k, _mm512_cvtepi32_ph(a), src) } } @@ -12366,7 +12366,7 @@ pub fn _mm512_mask_cvtepi32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h { _mm512_mask_cvtepi32_ph(f16x16::ZERO.as_m256h(), k, a) } @@ -12387,7 +12387,7 @@ pub fn _mm512_maskz_cvtepi32_ph(k: __mmask16, a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepi32_ph(a: __m512i) -> __m256h { unsafe { static_assert_rounding!(ROUNDING); @@ -12412,7 +12412,7 @@ pub fn _mm512_cvt_roundepi32_ph(a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepi32_ph( src: __m256h, k: __mmask16, @@ -12440,7 +12440,7 @@ pub fn _mm512_mask_cvt_roundepi32_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtdq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepi32_ph(k: __mmask16, a: __m512i) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepi32_ph::(f16x16::ZERO.as_m256h(), k, a) @@ -12454,7 +12454,7 @@ pub fn _mm512_maskz_cvt_roundepi32_ph(k: __mmask16, a: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h { unsafe { vcvtsi2sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -12476,7 +12476,7 @@ pub fn _mm_cvti32_sh(a: __m128h, b: i32) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundi32_sh(a: __m128h, b: i32) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -12491,7 +12491,7 @@ pub fn _mm_cvt_roundi32_sh(a: __m128h, b: i32) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h { _mm_mask_cvtepu32_ph(_mm_setzero_ph(), 0xff, a) } @@ -12504,7 +12504,7 @@ pub fn _mm_cvtepu32_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtudq2ph_128(a.as_u32x4(), src, k) } } @@ -12517,7 +12517,7 @@ pub fn _mm_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepu32_ph(_mm_setzero_ph(), k, a) } @@ -12529,7 +12529,7 @@ pub fn _mm_maskz_cvtepu32_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h { unsafe { vcvtudq2ph_256(a.as_u32x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12542,7 +12542,7 @@ pub fn _mm256_cvtepu32_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { simd_select_bitmask(k, _mm256_cvtepu32_ph(a), src) } } @@ -12554,7 +12554,7 @@ pub fn _mm256_mask_cvtepu32_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepu32_ph(_mm_setzero_ph(), k, a) } @@ -12566,7 +12566,7 @@ pub fn _mm256_maskz_cvtepu32_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h { unsafe { vcvtudq2ph_512(a.as_u32x16(), _MM_FROUND_CUR_DIRECTION) } } @@ -12579,7 +12579,7 @@ pub fn _mm512_cvtepu32_ph(a: __m512i) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256h { unsafe { simd_select_bitmask(k, _mm512_cvtepu32_ph(a), src) } } @@ -12591,7 +12591,7 @@ pub fn _mm512_mask_cvtepu32_ph(src: __m256h, k: __mmask16, a: __m512i) -> __m256 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h { _mm512_mask_cvtepu32_ph(f16x16::ZERO.as_m256h(), k, a) } @@ -12612,7 +12612,7 @@ pub fn _mm512_maskz_cvtepu32_ph(k: __mmask16, a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepu32_ph(a: __m512i) -> __m256h { unsafe { static_assert_rounding!(ROUNDING); @@ -12637,7 +12637,7 @@ pub fn _mm512_cvt_roundepu32_ph(a: __m512i) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepu32_ph( src: __m256h, k: __mmask16, @@ -12665,7 +12665,7 @@ pub fn _mm512_mask_cvt_roundepu32_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtudq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepu32_ph(k: __mmask16, a: __m512i) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepu32_ph::(f16x16::ZERO.as_m256h(), k, a) @@ -12679,7 +12679,7 @@ pub fn _mm512_maskz_cvt_roundepu32_ph(k: __mmask16, a: __m5 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h { unsafe { vcvtusi2sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -12701,7 +12701,7 @@ pub fn _mm_cvtu32_sh(a: __m128h, b: u32) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundu32_sh(a: __m128h, b: u32) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -12716,7 +12716,7 @@ pub fn _mm_cvt_roundu32_sh(a: __m128h, b: u32) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h { _mm_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12729,7 +12729,7 @@ pub fn _mm_cvtepi64_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtqq2ph_128(a.as_i64x2(), src, k) } } @@ -12742,7 +12742,7 @@ pub fn _mm_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepi64_ph(_mm_setzero_ph(), k, a) } @@ -12754,7 +12754,7 @@ pub fn _mm_maskz_cvtepi64_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h { _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12767,7 +12767,7 @@ pub fn _mm256_cvtepi64_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { vcvtqq2ph_256(a.as_i64x4(), src, k) } } @@ -12780,7 +12780,7 @@ pub fn _mm256_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepi64_ph(_mm_setzero_ph(), k, a) } @@ -12792,7 +12792,7 @@ pub fn _mm256_maskz_cvtepi64_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h { unsafe { vcvtqq2ph_512(a.as_i64x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12805,7 +12805,7 @@ pub fn _mm512_cvtepi64_ph(a: __m512i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h { unsafe { simd_select_bitmask(k, _mm512_cvtepi64_ph(a), src) } } @@ -12817,7 +12817,7 @@ pub fn _mm512_mask_cvtepi64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h { _mm512_mask_cvtepi64_ph(f16x8::ZERO.as_m128h(), k, a) } @@ -12838,7 +12838,7 @@ pub fn _mm512_maskz_cvtepi64_ph(k: __mmask8, a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepi64_ph(a: __m512i) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -12863,7 +12863,7 @@ pub fn _mm512_cvt_roundepi64_ph(a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepi64_ph( src: __m128h, k: __mmask8, @@ -12891,7 +12891,7 @@ pub fn _mm512_mask_cvt_roundepi64_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepi64_ph(k: __mmask8, a: __m512i) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepi64_ph::(f16x8::ZERO.as_m128h(), k, a) @@ -12904,7 +12904,7 @@ pub fn _mm512_maskz_cvt_roundepi64_ph(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h { _mm_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12917,7 +12917,7 @@ pub fn _mm_cvtepu64_ph(a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { unsafe { vcvtuqq2ph_128(a.as_u64x2(), src, k) } } @@ -12930,7 +12930,7 @@ pub fn _mm_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h { _mm_mask_cvtepu64_ph(_mm_setzero_ph(), k, a) } @@ -12942,7 +12942,7 @@ pub fn _mm_maskz_cvtepu64_ph(k: __mmask8, a: __m128i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h { _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), 0xff, a) } @@ -12955,7 +12955,7 @@ pub fn _mm256_cvtepu64_ph(a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h { unsafe { vcvtuqq2ph_256(a.as_u64x4(), src, k) } } @@ -12968,7 +12968,7 @@ pub fn _mm256_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m256i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h { _mm256_mask_cvtepu64_ph(_mm_setzero_ph(), k, a) } @@ -12980,7 +12980,7 @@ pub fn _mm256_maskz_cvtepu64_ph(k: __mmask8, a: __m256i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h { unsafe { vcvtuqq2ph_512(a.as_u64x8(), _MM_FROUND_CUR_DIRECTION) } } @@ -12993,7 +12993,7 @@ pub fn _mm512_cvtepu64_ph(a: __m512i) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h { unsafe { simd_select_bitmask(k, _mm512_cvtepu64_ph(a), src) } } @@ -13005,7 +13005,7 @@ pub fn _mm512_mask_cvtepu64_ph(src: __m128h, k: __mmask8, a: __m512i) -> __m128h #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h { _mm512_mask_cvtepu64_ph(f16x8::ZERO.as_m128h(), k, a) } @@ -13026,7 +13026,7 @@ pub fn _mm512_maskz_cvtepu64_ph(k: __mmask8, a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundepu64_ph(a: __m512i) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -13051,7 +13051,7 @@ pub fn _mm512_cvt_roundepu64_ph(a: __m512i) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundepu64_ph( src: __m128h, k: __mmask8, @@ -13079,7 +13079,7 @@ pub fn _mm512_mask_cvt_roundepu64_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtuqq2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundepu64_ph(k: __mmask8, a: __m512i) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundepu64_ph::(f16x8::ZERO.as_m128h(), k, a) @@ -13092,7 +13092,7 @@ pub fn _mm512_maskz_cvt_roundepu64_ph(k: __mmask8, a: __m51 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtxps_ph(a: __m128) -> __m128h { _mm_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a) } @@ -13105,7 +13105,7 @@ pub fn _mm_cvtxps_ph(a: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h { unsafe { vcvtps2phx_128(a, src, k) } } @@ -13118,7 +13118,7 @@ pub fn _mm_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h { _mm_mask_cvtxps_ph(_mm_setzero_ph(), k, a) } @@ -13130,7 +13130,7 @@ pub fn _mm_maskz_cvtxps_ph(k: __mmask8, a: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h { _mm256_mask_cvtxps_ph(_mm_setzero_ph(), 0xff, a) } @@ -13143,7 +13143,7 @@ pub fn _mm256_cvtxps_ph(a: __m256) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h { unsafe { vcvtps2phx_256(a, src, k) } } @@ -13156,7 +13156,7 @@ pub fn _mm256_mask_cvtxps_ph(src: __m128h, k: __mmask8, a: __m256) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h { _mm256_mask_cvtxps_ph(_mm_setzero_ph(), k, a) } @@ -13168,7 +13168,7 @@ pub fn _mm256_maskz_cvtxps_ph(k: __mmask8, a: __m256) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h { _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), 0xffff, a) } @@ -13181,7 +13181,7 @@ pub fn _mm512_cvtxps_ph(a: __m512) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h { unsafe { vcvtps2phx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13194,7 +13194,7 @@ pub fn _mm512_mask_cvtxps_ph(src: __m256h, k: __mmask16, a: __m512) -> __m256h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h { _mm512_mask_cvtxps_ph(f16x16::ZERO.as_m256h(), k, a) } @@ -13215,7 +13215,7 @@ pub fn _mm512_maskz_cvtxps_ph(k: __mmask16, a: __m512) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtx_roundps_ph(a: __m512) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvtx_roundps_ph::(f16x16::ZERO.as_m256h(), 0xffff, a) @@ -13238,7 +13238,7 @@ pub fn _mm512_cvtx_roundps_ph(a: __m512) -> __m256h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtx_roundps_ph( src: __m256h, k: __mmask16, @@ -13267,7 +13267,7 @@ pub fn _mm512_mask_cvtx_roundps_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtps2phx, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtx_roundps_ph(k: __mmask16, a: __m512) -> __m256h { static_assert_rounding!(ROUNDING); _mm512_mask_cvtx_roundps_ph::(f16x16::ZERO.as_m256h(), k, a) @@ -13281,7 +13281,7 @@ pub fn _mm512_maskz_cvtx_roundps_ph(k: __mmask16, a: __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h { _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -13295,7 +13295,7 @@ pub fn _mm_cvtss_sh(a: __m128h, b: __m128) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __m128h { unsafe { vcvtss2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13309,7 +13309,7 @@ pub fn _mm_mask_cvtss_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128) -> __ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h { _mm_mask_cvtss_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -13331,7 +13331,7 @@ pub fn _mm_maskz_cvtss_sh(k: __mmask8, a: __m128h, b: __m128) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundss_sh(a: __m128h, b: __m128) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_cvt_roundss_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -13355,7 +13355,7 @@ pub fn _mm_cvt_roundss_sh(a: __m128h, b: __m128) -> __m128h #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundss_sh( src: __m128h, k: __mmask8, @@ -13386,7 +13386,7 @@ pub fn _mm_mask_cvt_roundss_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtss2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundss_sh( k: __mmask8, a: __m128h, @@ -13403,7 +13403,7 @@ pub fn _mm_maskz_cvt_roundss_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h { _mm_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a) } @@ -13416,7 +13416,7 @@ pub fn _mm_cvtpd_ph(a: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h { unsafe { vcvtpd2ph_128(a, src, k) } } @@ -13429,7 +13429,7 @@ pub fn _mm_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h { _mm_mask_cvtpd_ph(_mm_setzero_ph(), k, a) } @@ -13441,7 +13441,7 @@ pub fn _mm_maskz_cvtpd_ph(k: __mmask8, a: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h { _mm256_mask_cvtpd_ph(_mm_setzero_ph(), 0xff, a) } @@ -13454,7 +13454,7 @@ pub fn _mm256_cvtpd_ph(a: __m256d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h { unsafe { vcvtpd2ph_256(a, src, k) } } @@ -13467,7 +13467,7 @@ pub fn _mm256_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m256d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h { _mm256_mask_cvtpd_ph(_mm_setzero_ph(), k, a) } @@ -13479,7 +13479,7 @@ pub fn _mm256_maskz_cvtpd_ph(k: __mmask8, a: __m256d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h { _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), 0xff, a) } @@ -13492,7 +13492,7 @@ pub fn _mm512_cvtpd_ph(a: __m512d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h { unsafe { vcvtpd2ph_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13505,7 +13505,7 @@ pub fn _mm512_mask_cvtpd_ph(src: __m128h, k: __mmask8, a: __m512d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h { _mm512_mask_cvtpd_ph(f16x8::ZERO.as_m128h(), k, a) } @@ -13526,7 +13526,7 @@ pub fn _mm512_maskz_cvtpd_ph(k: __mmask8, a: __m512d) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundpd_ph(a: __m512d) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundpd_ph::(f16x8::ZERO.as_m128h(), 0xff, a) @@ -13549,7 +13549,7 @@ pub fn _mm512_cvt_roundpd_ph(a: __m512d) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundpd_ph( src: __m128h, k: __mmask8, @@ -13578,7 +13578,7 @@ pub fn _mm512_mask_cvt_roundpd_ph( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtpd2ph, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundpd_ph(k: __mmask8, a: __m512d) -> __m128h { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundpd_ph::(f16x8::ZERO.as_m128h(), k, a) @@ -13592,7 +13592,7 @@ pub fn _mm512_maskz_cvt_roundpd_ph(k: __mmask8, a: __m512d) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h { _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), 0xff, a, b) } @@ -13606,7 +13606,7 @@ pub fn _mm_cvtsd_sh(a: __m128h, b: __m128d) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> __m128h { unsafe { vcvtsd2sh(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -13620,7 +13620,7 @@ pub fn _mm_mask_cvtsd_sh(src: __m128h, k: __mmask8, a: __m128h, b: __m128d) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h { _mm_mask_cvtsd_sh(f16x8::ZERO.as_m128h(), k, a, b) } @@ -13642,7 +13642,7 @@ pub fn _mm_maskz_cvtsd_sh(k: __mmask8, a: __m128h, b: __m128d) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsd_sh(a: __m128h, b: __m128d) -> __m128h { static_assert_rounding!(ROUNDING); _mm_mask_cvt_roundsd_sh::(f16x8::ZERO.as_m128h(), 0xff, a, b) @@ -13666,7 +13666,7 @@ pub fn _mm_cvt_roundsd_sh(a: __m128h, b: __m128d) -> __m128 #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundsd_sh( src: __m128h, k: __mmask8, @@ -13697,7 +13697,7 @@ pub fn _mm_mask_cvt_roundsd_sh( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsd2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundsd_sh( k: __mmask8, a: __m128h, @@ -13714,7 +13714,7 @@ pub fn _mm_maskz_cvt_roundsd_sh( #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i { _mm_mask_cvtph_epi16(_mm_undefined_si128(), 0xff, a) } @@ -13727,7 +13727,7 @@ pub fn _mm_cvtph_epi16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2w_128(a, src.as_i16x8(), k)) } } @@ -13739,7 +13739,7 @@ pub fn _mm_mask_cvtph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epi16(_mm_setzero_si128(), k, a) } @@ -13751,7 +13751,7 @@ pub fn _mm_maskz_cvtph_epi16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i { _mm256_mask_cvtph_epi16(_mm256_undefined_si256(), 0xffff, a) } @@ -13764,7 +13764,7 @@ pub fn _mm256_cvtph_epi16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvtph2w_256(a, src.as_i16x16(), k)) } } @@ -13776,7 +13776,7 @@ pub fn _mm256_mask_cvtph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvtph_epi16(_mm256_setzero_si256(), k, a) } @@ -13788,7 +13788,7 @@ pub fn _mm256_maskz_cvtph_epi16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i { _mm512_mask_cvtph_epi16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -13801,7 +13801,7 @@ pub fn _mm512_cvtph_epi16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvtph2w_512( @@ -13820,7 +13820,7 @@ pub fn _mm512_mask_cvtph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvtph_epi16(_mm512_setzero_si512(), k, a) } @@ -13841,7 +13841,7 @@ pub fn _mm512_maskz_cvtph_epi16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epi16(a: __m512h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -13864,7 +13864,7 @@ pub fn _mm512_cvt_roundph_epi16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epi16( src: __m512i, k: __mmask32, @@ -13892,7 +13892,7 @@ pub fn _mm512_mask_cvt_roundph_epi16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2w, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epi16(k: __mmask32, a: __m512h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi16::(_mm512_setzero_si512(), k, a) @@ -13905,7 +13905,7 @@ pub fn _mm512_maskz_cvt_roundph_epi16(k: __mmask32, a: __m5 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i { _mm_mask_cvtph_epu16(_mm_undefined_si128(), 0xff, a) } @@ -13918,7 +13918,7 @@ pub fn _mm_cvtph_epu16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2uw_128(a, src.as_u16x8(), k)) } } @@ -13930,7 +13930,7 @@ pub fn _mm_mask_cvtph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epu16(_mm_setzero_si128(), k, a) } @@ -13942,7 +13942,7 @@ pub fn _mm_maskz_cvtph_epu16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i { _mm256_mask_cvtph_epu16(_mm256_undefined_si256(), 0xffff, a) } @@ -13955,7 +13955,7 @@ pub fn _mm256_cvtph_epu16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvtph2uw_256(a, src.as_u16x16(), k)) } } @@ -13967,7 +13967,7 @@ pub fn _mm256_mask_cvtph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvtph_epu16(_mm256_setzero_si256(), k, a) } @@ -13979,7 +13979,7 @@ pub fn _mm256_maskz_cvtph_epu16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i { _mm512_mask_cvtph_epu16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -13992,7 +13992,7 @@ pub fn _mm512_cvtph_epu16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvtph2uw_512( @@ -14011,7 +14011,7 @@ pub fn _mm512_mask_cvtph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvtph_epu16(_mm512_setzero_si512(), k, a) } @@ -14026,7 +14026,7 @@ pub fn _mm512_maskz_cvtph_epu16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epu16(a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_epu16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -14043,7 +14043,7 @@ pub fn _mm512_cvt_roundph_epu16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epu16( src: __m512i, k: __mmask32, @@ -14065,7 +14065,7 @@ pub fn _mm512_mask_cvt_roundph_epu16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uw, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epu16(k: __mmask32, a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_epu16::(_mm512_setzero_si512(), k, a) @@ -14078,7 +14078,7 @@ pub fn _mm512_maskz_cvt_roundph_epu16(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i { _mm_mask_cvttph_epi16(_mm_undefined_si128(), 0xff, a) } @@ -14091,7 +14091,7 @@ pub fn _mm_cvttph_epi16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2w_128(a, src.as_i16x8(), k)) } } @@ -14104,7 +14104,7 @@ pub fn _mm_mask_cvttph_epi16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epi16(_mm_setzero_si128(), k, a) } @@ -14116,7 +14116,7 @@ pub fn _mm_maskz_cvttph_epi16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i { _mm256_mask_cvttph_epi16(_mm256_undefined_si256(), 0xffff, a) } @@ -14129,7 +14129,7 @@ pub fn _mm256_cvttph_epi16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvttph2w_256(a, src.as_i16x16(), k)) } } @@ -14142,7 +14142,7 @@ pub fn _mm256_mask_cvttph_epi16(src: __m256i, k: __mmask16, a: __m256h) -> __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvttph_epi16(_mm256_setzero_si256(), k, a) } @@ -14154,7 +14154,7 @@ pub fn _mm256_maskz_cvttph_epi16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i { _mm512_mask_cvttph_epi16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -14167,7 +14167,7 @@ pub fn _mm512_cvttph_epi16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvttph2w_512( @@ -14187,7 +14187,7 @@ pub fn _mm512_mask_cvttph_epi16(src: __m512i, k: __mmask32, a: __m512h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvttph_epi16(_mm512_setzero_si512(), k, a) } @@ -14202,7 +14202,7 @@ pub fn _mm512_maskz_cvttph_epi16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epi16(a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -14219,7 +14219,7 @@ pub fn _mm512_cvtt_roundph_epi16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epi16( src: __m512i, k: __mmask32, @@ -14242,7 +14242,7 @@ pub fn _mm512_mask_cvtt_roundph_epi16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2w, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epi16(k: __mmask32, a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi16::(_mm512_setzero_si512(), k, a) @@ -14255,7 +14255,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi16(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i { _mm_mask_cvttph_epu16(_mm_undefined_si128(), 0xff, a) } @@ -14268,7 +14268,7 @@ pub fn _mm_cvttph_epu16(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2uw_128(a, src.as_u16x8(), k)) } } @@ -14281,7 +14281,7 @@ pub fn _mm_mask_cvttph_epu16(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epu16(_mm_setzero_si128(), k, a) } @@ -14293,7 +14293,7 @@ pub fn _mm_maskz_cvttph_epu16(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i { _mm256_mask_cvttph_epu16(_mm256_undefined_si256(), 0xffff, a) } @@ -14306,7 +14306,7 @@ pub fn _mm256_cvttph_epu16(a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m256i { unsafe { transmute(vcvttph2uw_256(a, src.as_u16x16(), k)) } } @@ -14319,7 +14319,7 @@ pub fn _mm256_mask_cvttph_epu16(src: __m256i, k: __mmask16, a: __m256h) -> __m25 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i { _mm256_mask_cvttph_epu16(_mm256_setzero_si256(), k, a) } @@ -14331,7 +14331,7 @@ pub fn _mm256_maskz_cvttph_epu16(k: __mmask16, a: __m256h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i { _mm512_mask_cvttph_epu16(_mm512_undefined_epi32(), 0xffffffff, a) } @@ -14344,7 +14344,7 @@ pub fn _mm512_cvttph_epu16(a: __m512h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m512i { unsafe { transmute(vcvttph2uw_512( @@ -14364,7 +14364,7 @@ pub fn _mm512_mask_cvttph_epu16(src: __m512i, k: __mmask32, a: __m512h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i { _mm512_mask_cvttph_epu16(_mm512_setzero_si512(), k, a) } @@ -14379,7 +14379,7 @@ pub fn _mm512_maskz_cvttph_epu16(k: __mmask32, a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epu16(a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu16::(_mm512_undefined_epi32(), 0xffffffff, a) @@ -14396,7 +14396,7 @@ pub fn _mm512_cvtt_roundph_epu16(a: __m512h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epu16( src: __m512i, k: __mmask32, @@ -14419,7 +14419,7 @@ pub fn _mm512_mask_cvtt_roundph_epu16( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uw, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epu16(k: __mmask32, a: __m512h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu16::(_mm512_setzero_si512(), k, a) @@ -14432,7 +14432,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu16(k: __mmask32, a: __m512h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i { _mm_mask_cvtph_epi32(_mm_undefined_si128(), 0xff, a) } @@ -14444,7 +14444,7 @@ pub fn _mm_cvtph_epi32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2dq_128(a, src.as_i32x4(), k)) } } @@ -14456,7 +14456,7 @@ pub fn _mm_mask_cvtph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epi32(_mm_setzero_si128(), k, a) } @@ -14468,7 +14468,7 @@ pub fn _mm_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i { _mm256_mask_cvtph_epi32(_mm256_undefined_si256(), 0xff, a) } @@ -14480,7 +14480,7 @@ pub fn _mm256_cvtph_epi32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2dq_256(a, src.as_i32x8(), k)) } } @@ -14492,7 +14492,7 @@ pub fn _mm256_mask_cvtph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epi32(_mm256_setzero_si256(), k, a) } @@ -14504,7 +14504,7 @@ pub fn _mm256_maskz_cvtph_epi32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i { _mm512_mask_cvtph_epi32(_mm512_undefined_epi32(), 0xffff, a) } @@ -14516,7 +14516,7 @@ pub fn _mm512_cvtph_epi32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvtph2dq_512( @@ -14535,7 +14535,7 @@ pub fn _mm512_mask_cvtph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvtph_epi32(_mm512_setzero_si512(), k, a) } @@ -14556,7 +14556,7 @@ pub fn _mm512_maskz_cvtph_epi32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epi32(a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi32::(_mm512_undefined_epi32(), 0xffff, a) @@ -14578,7 +14578,7 @@ pub fn _mm512_cvt_roundph_epi32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epi32( src: __m512i, k: __mmask16, @@ -14606,7 +14606,7 @@ pub fn _mm512_mask_cvt_roundph_epi32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2dq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epi32(k: __mmask16, a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi32::(_mm512_setzero_si512(), k, a) @@ -14619,7 +14619,7 @@ pub fn _mm512_maskz_cvt_roundph_epi32(k: __mmask16, a: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_i32(a: __m128h) -> i32 { unsafe { vcvtsh2si32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -14640,7 +14640,7 @@ pub fn _mm_cvtsh_i32(a: __m128h) -> i32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_i32(a: __m128h) -> i32 { unsafe { static_assert_rounding!(ROUNDING); @@ -14655,7 +14655,7 @@ pub fn _mm_cvt_roundsh_i32(a: __m128h) -> i32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i { _mm_mask_cvtph_epu32(_mm_undefined_si128(), 0xff, a) } @@ -14667,7 +14667,7 @@ pub fn _mm_cvtph_epu32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2udq_128(a, src.as_u32x4(), k)) } } @@ -14679,7 +14679,7 @@ pub fn _mm_mask_cvtph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epu32(_mm_setzero_si128(), k, a) } @@ -14691,7 +14691,7 @@ pub fn _mm_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i { _mm256_mask_cvtph_epu32(_mm256_undefined_si256(), 0xff, a) } @@ -14703,7 +14703,7 @@ pub fn _mm256_cvtph_epu32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2udq_256(a, src.as_u32x8(), k)) } } @@ -14715,7 +14715,7 @@ pub fn _mm256_mask_cvtph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epu32(_mm256_setzero_si256(), k, a) } @@ -14727,7 +14727,7 @@ pub fn _mm256_maskz_cvtph_epu32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i { _mm512_mask_cvtph_epu32(_mm512_undefined_epi32(), 0xffff, a) } @@ -14739,7 +14739,7 @@ pub fn _mm512_cvtph_epu32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvtph2udq_512( @@ -14758,7 +14758,7 @@ pub fn _mm512_mask_cvtph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvtph_epu32(_mm512_setzero_si512(), k, a) } @@ -14779,7 +14779,7 @@ pub fn _mm512_maskz_cvtph_epu32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epu32(a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu32::(_mm512_undefined_epi32(), 0xffff, a) @@ -14801,7 +14801,7 @@ pub fn _mm512_cvt_roundph_epu32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epu32( src: __m512i, k: __mmask16, @@ -14829,7 +14829,7 @@ pub fn _mm512_mask_cvt_roundph_epu32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2udq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epu32(k: __mmask16, a: __m256h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu32::(_mm512_setzero_si512(), k, a) @@ -14842,7 +14842,7 @@ pub fn _mm512_maskz_cvt_roundph_epu32(k: __mmask16, a: __m2 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_u32(a: __m128h) -> u32 { unsafe { vcvtsh2usi32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -14857,7 +14857,7 @@ pub fn _mm_cvtsh_u32(a: __m128h) -> u32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_u32(a: __m128h) -> u32 { unsafe { static_assert_rounding!(SAE); @@ -14872,7 +14872,7 @@ pub fn _mm_cvt_roundsh_u32(a: __m128h) -> u32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i { _mm_mask_cvttph_epi32(_mm_undefined_si128(), 0xff, a) } @@ -14884,7 +14884,7 @@ pub fn _mm_cvttph_epi32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2dq_128(a, src.as_i32x4(), k)) } } @@ -14896,7 +14896,7 @@ pub fn _mm_mask_cvttph_epi32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epi32(_mm_setzero_si128(), k, a) } @@ -14908,7 +14908,7 @@ pub fn _mm_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i { _mm256_mask_cvttph_epi32(_mm256_undefined_si256(), 0xff, a) } @@ -14920,7 +14920,7 @@ pub fn _mm256_cvttph_epi32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2dq_256(a, src.as_i32x8(), k)) } } @@ -14932,7 +14932,7 @@ pub fn _mm256_mask_cvttph_epi32(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epi32(_mm256_setzero_si256(), k, a) } @@ -14944,7 +14944,7 @@ pub fn _mm256_maskz_cvttph_epi32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i { _mm512_mask_cvttph_epi32(_mm512_undefined_epi32(), 0xffff, a) } @@ -14956,7 +14956,7 @@ pub fn _mm512_cvttph_epi32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvttph2dq_512( @@ -14975,7 +14975,7 @@ pub fn _mm512_mask_cvttph_epi32(src: __m512i, k: __mmask16, a: __m256h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvttph_epi32(_mm512_setzero_si512(), k, a) } @@ -14990,7 +14990,7 @@ pub fn _mm512_maskz_cvttph_epi32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epi32(a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi32::(_mm512_undefined_epi32(), 0xffff, a) @@ -15006,7 +15006,7 @@ pub fn _mm512_cvtt_roundph_epi32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epi32( src: __m512i, k: __mmask16, @@ -15028,7 +15028,7 @@ pub fn _mm512_mask_cvtt_roundph_epi32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2dq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epi32(k: __mmask16, a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi32::(_mm512_setzero_si512(), k, a) @@ -15041,7 +15041,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi32(k: __mmask16, a: __m256h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_i32(a: __m128h) -> i32 { unsafe { vcvttsh2si32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -15056,7 +15056,7 @@ pub fn _mm_cvttsh_i32(a: __m128h) -> i32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_i32(a: __m128h) -> i32 { unsafe { static_assert_sae!(SAE); @@ -15071,7 +15071,7 @@ pub fn _mm_cvtt_roundsh_i32(a: __m128h) -> i32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i { _mm_mask_cvttph_epu32(_mm_undefined_si128(), 0xff, a) } @@ -15083,7 +15083,7 @@ pub fn _mm_cvttph_epu32(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2udq_128(a, src.as_u32x4(), k)) } } @@ -15095,7 +15095,7 @@ pub fn _mm_mask_cvttph_epu32(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epu32(_mm_setzero_si128(), k, a) } @@ -15107,7 +15107,7 @@ pub fn _mm_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i { _mm256_mask_cvttph_epu32(_mm256_undefined_si256(), 0xff, a) } @@ -15119,7 +15119,7 @@ pub fn _mm256_cvttph_epu32(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2udq_256(a, src.as_u32x8(), k)) } } @@ -15131,7 +15131,7 @@ pub fn _mm256_mask_cvttph_epu32(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epu32(_mm256_setzero_si256(), k, a) } @@ -15143,7 +15143,7 @@ pub fn _mm256_maskz_cvttph_epu32(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i { _mm512_mask_cvttph_epu32(_mm512_undefined_epi32(), 0xffff, a) } @@ -15155,7 +15155,7 @@ pub fn _mm512_cvttph_epu32(a: __m256h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m512i { unsafe { transmute(vcvttph2udq_512( @@ -15174,7 +15174,7 @@ pub fn _mm512_mask_cvttph_epu32(src: __m512i, k: __mmask16, a: __m256h) -> __m51 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i { _mm512_mask_cvttph_epu32(_mm512_setzero_si512(), k, a) } @@ -15189,7 +15189,7 @@ pub fn _mm512_maskz_cvttph_epu32(k: __mmask16, a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epu32(a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu32::(_mm512_undefined_epi32(), 0xffff, a) @@ -15205,7 +15205,7 @@ pub fn _mm512_cvtt_roundph_epu32(a: __m256h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epu32( src: __m512i, k: __mmask16, @@ -15227,7 +15227,7 @@ pub fn _mm512_mask_cvtt_roundph_epu32( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2udq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epu32(k: __mmask16, a: __m256h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu32::(_mm512_setzero_si512(), k, a) @@ -15240,7 +15240,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu32(k: __mmask16, a: __m256h) #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_u32(a: __m128h) -> u32 { unsafe { vcvttsh2usi32(a, _MM_FROUND_CUR_DIRECTION) } } @@ -15255,7 +15255,7 @@ pub fn _mm_cvttsh_u32(a: __m128h) -> u32 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_u32(a: __m128h) -> u32 { unsafe { static_assert_sae!(SAE); @@ -15270,7 +15270,7 @@ pub fn _mm_cvtt_roundsh_u32(a: __m128h) -> u32 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i { _mm_mask_cvtph_epi64(_mm_undefined_si128(), 0xff, a) } @@ -15282,7 +15282,7 @@ pub fn _mm_cvtph_epi64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2qq_128(a, src.as_i64x2(), k)) } } @@ -15294,7 +15294,7 @@ pub fn _mm_mask_cvtph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epi64(_mm_setzero_si128(), k, a) } @@ -15306,7 +15306,7 @@ pub fn _mm_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i { _mm256_mask_cvtph_epi64(_mm256_undefined_si256(), 0xff, a) } @@ -15318,7 +15318,7 @@ pub fn _mm256_cvtph_epi64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2qq_256(a, src.as_i64x4(), k)) } } @@ -15330,7 +15330,7 @@ pub fn _mm256_mask_cvtph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epi64(_mm256_setzero_si256(), k, a) } @@ -15342,7 +15342,7 @@ pub fn _mm256_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i { _mm512_mask_cvtph_epi64(_mm512_undefined_epi32(), 0xff, a) } @@ -15354,7 +15354,7 @@ pub fn _mm512_cvtph_epi64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvtph2qq_512( @@ -15373,7 +15373,7 @@ pub fn _mm512_mask_cvtph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvtph_epi64(_mm512_setzero_si512(), k, a) } @@ -15394,7 +15394,7 @@ pub fn _mm512_maskz_cvtph_epi64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epi64(a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi64::(_mm512_undefined_epi32(), 0xff, a) @@ -15416,7 +15416,7 @@ pub fn _mm512_cvt_roundph_epi64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epi64( src: __m512i, k: __mmask8, @@ -15444,7 +15444,7 @@ pub fn _mm512_mask_cvt_roundph_epi64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2qq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epi64(k: __mmask8, a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epi64::(_mm512_setzero_si512(), k, a) @@ -15457,7 +15457,7 @@ pub fn _mm512_maskz_cvt_roundph_epi64(k: __mmask8, a: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i { _mm_mask_cvtph_epu64(_mm_undefined_si128(), 0xff, a) } @@ -15469,7 +15469,7 @@ pub fn _mm_cvtph_epu64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvtph2uqq_128(a, src.as_u64x2(), k)) } } @@ -15481,7 +15481,7 @@ pub fn _mm_mask_cvtph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvtph_epu64(_mm_setzero_si128(), k, a) } @@ -15493,7 +15493,7 @@ pub fn _mm_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i { _mm256_mask_cvtph_epu64(_mm256_undefined_si256(), 0xff, a) } @@ -15505,7 +15505,7 @@ pub fn _mm256_cvtph_epu64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvtph2uqq_256(a, src.as_u64x4(), k)) } } @@ -15517,7 +15517,7 @@ pub fn _mm256_mask_cvtph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvtph_epu64(_mm256_setzero_si256(), k, a) } @@ -15529,7 +15529,7 @@ pub fn _mm256_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i { _mm512_mask_cvtph_epu64(_mm512_undefined_epi32(), 0xff, a) } @@ -15541,7 +15541,7 @@ pub fn _mm512_cvtph_epu64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvtph2uqq_512( @@ -15560,7 +15560,7 @@ pub fn _mm512_mask_cvtph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvtph_epu64(_mm512_setzero_si512(), k, a) } @@ -15581,7 +15581,7 @@ pub fn _mm512_maskz_cvtph_epu64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_epu64(a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu64::(_mm512_undefined_epi32(), 0xff, a) @@ -15603,7 +15603,7 @@ pub fn _mm512_cvt_roundph_epu64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_epu64( src: __m512i, k: __mmask8, @@ -15631,7 +15631,7 @@ pub fn _mm512_mask_cvt_roundph_epu64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2uqq, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_epu64(k: __mmask8, a: __m128h) -> __m512i { static_assert_rounding!(ROUNDING); _mm512_mask_cvt_roundph_epu64::(_mm512_setzero_si512(), k, a) @@ -15644,7 +15644,7 @@ pub fn _mm512_maskz_cvt_roundph_epu64(k: __mmask8, a: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i { _mm_mask_cvttph_epi64(_mm_undefined_si128(), 0xff, a) } @@ -15656,7 +15656,7 @@ pub fn _mm_cvttph_epi64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2qq_128(a, src.as_i64x2(), k)) } } @@ -15668,7 +15668,7 @@ pub fn _mm_mask_cvttph_epi64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epi64(_mm_setzero_si128(), k, a) } @@ -15680,7 +15680,7 @@ pub fn _mm_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i { _mm256_mask_cvttph_epi64(_mm256_undefined_si256(), 0xff, a) } @@ -15692,7 +15692,7 @@ pub fn _mm256_cvttph_epi64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2qq_256(a, src.as_i64x4(), k)) } } @@ -15704,7 +15704,7 @@ pub fn _mm256_mask_cvttph_epi64(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epi64(_mm256_setzero_si256(), k, a) } @@ -15716,7 +15716,7 @@ pub fn _mm256_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i { _mm512_mask_cvttph_epi64(_mm512_undefined_epi32(), 0xff, a) } @@ -15728,7 +15728,7 @@ pub fn _mm512_cvttph_epi64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvttph2qq_512( @@ -15747,7 +15747,7 @@ pub fn _mm512_mask_cvttph_epi64(src: __m512i, k: __mmask8, a: __m128h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvttph_epi64(_mm512_setzero_si512(), k, a) } @@ -15762,7 +15762,7 @@ pub fn _mm512_maskz_cvttph_epi64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epi64(a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi64::(_mm512_undefined_epi32(), 0xff, a) @@ -15778,7 +15778,7 @@ pub fn _mm512_cvtt_roundph_epi64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epi64( src: __m512i, k: __mmask8, @@ -15800,7 +15800,7 @@ pub fn _mm512_mask_cvtt_roundph_epi64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2qq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epi64(k: __mmask8, a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epi64::(_mm512_setzero_si512(), k, a) @@ -15813,7 +15813,7 @@ pub fn _mm512_maskz_cvtt_roundph_epi64(k: __mmask8, a: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i { _mm_mask_cvttph_epu64(_mm_undefined_si128(), 0xff, a) } @@ -15825,7 +15825,7 @@ pub fn _mm_cvttph_epu64(a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { unsafe { transmute(vcvttph2uqq_128(a, src.as_u64x2(), k)) } } @@ -15837,7 +15837,7 @@ pub fn _mm_mask_cvttph_epu64(src: __m128i, k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i { _mm_mask_cvttph_epu64(_mm_setzero_si128(), k, a) } @@ -15849,7 +15849,7 @@ pub fn _mm_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m128i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i { _mm256_mask_cvttph_epu64(_mm256_undefined_si256(), 0xff, a) } @@ -15861,7 +15861,7 @@ pub fn _mm256_cvttph_epu64(a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256i { unsafe { transmute(vcvttph2uqq_256(a, src.as_u64x4(), k)) } } @@ -15873,7 +15873,7 @@ pub fn _mm256_mask_cvttph_epu64(src: __m256i, k: __mmask8, a: __m128h) -> __m256 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i { _mm256_mask_cvttph_epu64(_mm256_setzero_si256(), k, a) } @@ -15885,7 +15885,7 @@ pub fn _mm256_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m256i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i { _mm512_mask_cvttph_epu64(_mm512_undefined_epi32(), 0xff, a) } @@ -15897,7 +15897,7 @@ pub fn _mm512_cvttph_epu64(a: __m128h) -> __m512i { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512i { unsafe { transmute(vcvttph2uqq_512( @@ -15916,7 +15916,7 @@ pub fn _mm512_mask_cvttph_epu64(src: __m512i, k: __mmask8, a: __m128h) -> __m512 #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i { _mm512_mask_cvttph_epu64(_mm512_setzero_si512(), k, a) } @@ -15931,7 +15931,7 @@ pub fn _mm512_maskz_cvttph_epu64(k: __mmask8, a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtt_roundph_epu64(a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu64::(_mm512_undefined_epi32(), 0xff, a) @@ -15947,7 +15947,7 @@ pub fn _mm512_cvtt_roundph_epu64(a: __m128h) -> __m512i { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtt_roundph_epu64( src: __m512i, k: __mmask8, @@ -15969,7 +15969,7 @@ pub fn _mm512_mask_cvtt_roundph_epu64( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttph2uqq, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtt_roundph_epu64(k: __mmask8, a: __m128h) -> __m512i { static_assert_sae!(SAE); _mm512_mask_cvtt_roundph_epu64::(_mm512_setzero_si512(), k, a) @@ -15982,7 +15982,7 @@ pub fn _mm512_maskz_cvtt_roundph_epu64(k: __mmask8, a: __m128h) #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 { _mm_mask_cvtxph_ps(_mm_setzero_ps(), 0xff, a) } @@ -15995,7 +15995,7 @@ pub fn _mm_cvtxph_ps(a: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 { unsafe { vcvtph2psx_128(a, src, k) } } @@ -16008,7 +16008,7 @@ pub fn _mm_mask_cvtxph_ps(src: __m128, k: __mmask8, a: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 { _mm_mask_cvtxph_ps(_mm_setzero_ps(), k, a) } @@ -16020,7 +16020,7 @@ pub fn _mm_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 { _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), 0xff, a) } @@ -16033,7 +16033,7 @@ pub fn _mm256_cvtxph_ps(a: __m128h) -> __m256 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 { unsafe { vcvtph2psx_256(a, src, k) } } @@ -16046,7 +16046,7 @@ pub fn _mm256_mask_cvtxph_ps(src: __m256, k: __mmask8, a: __m128h) -> __m256 { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 { _mm256_mask_cvtxph_ps(_mm256_setzero_ps(), k, a) } @@ -16058,7 +16058,7 @@ pub fn _mm256_maskz_cvtxph_ps(k: __mmask8, a: __m128h) -> __m256 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 { _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), 0xffff, a) } @@ -16071,7 +16071,7 @@ pub fn _mm512_cvtxph_ps(a: __m256h) -> __m512 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 { unsafe { vcvtph2psx_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16084,7 +16084,7 @@ pub fn _mm512_mask_cvtxph_ps(src: __m512, k: __mmask16, a: __m256h) -> __m512 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 { _mm512_mask_cvtxph_ps(_mm512_setzero_ps(), k, a) } @@ -16099,7 +16099,7 @@ pub fn _mm512_maskz_cvtxph_ps(k: __mmask16, a: __m256h) -> __m512 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtx_roundph_ps(a: __m256h) -> __m512 { static_assert_sae!(SAE); _mm512_mask_cvtx_roundph_ps::(_mm512_setzero_ps(), 0xffff, a) @@ -16116,7 +16116,7 @@ pub fn _mm512_cvtx_roundph_ps(a: __m256h) -> __m512 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtx_roundph_ps( src: __m512, k: __mmask16, @@ -16139,7 +16139,7 @@ pub fn _mm512_mask_cvtx_roundph_ps( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2psx, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtx_roundph_ps(k: __mmask16, a: __m256h) -> __m512 { static_assert_sae!(SAE); _mm512_mask_cvtx_roundph_ps::(_mm512_setzero_ps(), k, a) @@ -16153,7 +16153,7 @@ pub fn _mm512_maskz_cvtx_roundph_ps(k: __mmask16, a: __m256h) -> #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 { _mm_mask_cvtsh_ss(a, 0xff, a, b) } @@ -16167,7 +16167,7 @@ pub fn _mm_cvtsh_ss(a: __m128, b: __m128h) -> __m128 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m128 { unsafe { vcvtsh2ss(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16181,7 +16181,7 @@ pub fn _mm_mask_cvtsh_ss(src: __m128, k: __mmask8, a: __m128, b: __m128h) -> __m #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 { _mm_mask_cvtsh_ss(_mm_set_ss(0.0), k, a, b) } @@ -16197,7 +16197,7 @@ pub fn _mm_maskz_cvtsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_ss(a: __m128, b: __m128h) -> __m128 { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_ss::(_mm_undefined_ps(), 0xff, a, b) @@ -16215,7 +16215,7 @@ pub fn _mm_cvt_roundsh_ss(a: __m128, b: __m128h) -> __m128 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundsh_ss( src: __m128, k: __mmask8, @@ -16240,7 +16240,7 @@ pub fn _mm_mask_cvt_roundsh_ss( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2ss, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundsh_ss(k: __mmask8, a: __m128, b: __m128h) -> __m128 { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_ss::(_mm_set_ss(0.0), k, a, b) @@ -16253,7 +16253,7 @@ pub fn _mm_maskz_cvt_roundsh_ss(k: __mmask8, a: __m128, b: __m12 #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtph_pd(a: __m128h) -> __m128d { _mm_mask_cvtph_pd(_mm_setzero_pd(), 0xff, a) } @@ -16266,7 +16266,7 @@ pub fn _mm_cvtph_pd(a: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d { unsafe { vcvtph2pd_128(a, src, k) } } @@ -16279,7 +16279,7 @@ pub fn _mm_mask_cvtph_pd(src: __m128d, k: __mmask8, a: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d { _mm_mask_cvtph_pd(_mm_setzero_pd(), k, a) } @@ -16291,7 +16291,7 @@ pub fn _mm_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d { _mm256_mask_cvtph_pd(_mm256_setzero_pd(), 0xff, a) } @@ -16304,7 +16304,7 @@ pub fn _mm256_cvtph_pd(a: __m128h) -> __m256d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d { unsafe { vcvtph2pd_256(a, src, k) } } @@ -16317,7 +16317,7 @@ pub fn _mm256_mask_cvtph_pd(src: __m256d, k: __mmask8, a: __m128h) -> __m256d { #[inline] #[target_feature(enable = "avx512fp16,avx512vl")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d { _mm256_mask_cvtph_pd(_mm256_setzero_pd(), k, a) } @@ -16329,7 +16329,7 @@ pub fn _mm256_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m256d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d { _mm512_mask_cvtph_pd(_mm512_setzero_pd(), 0xff, a) } @@ -16342,7 +16342,7 @@ pub fn _mm512_cvtph_pd(a: __m128h) -> __m512d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d { unsafe { vcvtph2pd_512(a, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16355,7 +16355,7 @@ pub fn _mm512_mask_cvtph_pd(src: __m512d, k: __mmask8, a: __m128h) -> __m512d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d { _mm512_mask_cvtph_pd(_mm512_setzero_pd(), k, a) } @@ -16370,7 +16370,7 @@ pub fn _mm512_maskz_cvtph_pd(k: __mmask8, a: __m128h) -> __m512d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_cvt_roundph_pd(a: __m128h) -> __m512d { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_pd::(_mm512_setzero_pd(), 0xff, a) @@ -16387,7 +16387,7 @@ pub fn _mm512_cvt_roundph_pd(a: __m128h) -> __m512d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_mask_cvt_roundph_pd( src: __m512d, k: __mmask8, @@ -16410,7 +16410,7 @@ pub fn _mm512_mask_cvt_roundph_pd( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtph2pd, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm512_maskz_cvt_roundph_pd(k: __mmask8, a: __m128h) -> __m512d { static_assert_sae!(SAE); _mm512_mask_cvt_roundph_pd::(_mm512_setzero_pd(), k, a) @@ -16424,7 +16424,7 @@ pub fn _mm512_maskz_cvt_roundph_pd(k: __mmask8, a: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d { _mm_mask_cvtsh_sd(a, 0xff, a, b) } @@ -16438,7 +16438,7 @@ pub fn _mm_cvtsh_sd(a: __m128d, b: __m128h) -> __m128d { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> __m128d { unsafe { vcvtsh2sd(a, b, src, k, _MM_FROUND_CUR_DIRECTION) } } @@ -16451,7 +16451,7 @@ pub fn _mm_mask_cvtsh_sd(src: __m128d, k: __mmask8, a: __m128d, b: __m128h) -> _ #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d { _mm_mask_cvtsh_sd(_mm_set_sd(0.0), k, a, b) } @@ -16467,7 +16467,7 @@ pub fn _mm_maskz_cvtsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_sd(a: __m128d, b: __m128h) -> __m128d { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_sd::(a, 0xff, a, b) @@ -16485,7 +16485,7 @@ pub fn _mm_cvt_roundsh_sd(a: __m128d, b: __m128h) -> __m128d { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))] #[rustc_legacy_const_generics(4)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_mask_cvt_roundsh_sd( src: __m128d, k: __mmask8, @@ -16509,7 +16509,7 @@ pub fn _mm_mask_cvt_roundsh_sd( #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2sd, SAE = 8))] #[rustc_legacy_const_generics(3)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_maskz_cvt_roundsh_sd(k: __mmask8, a: __m128d, b: __m128h) -> __m128d { static_assert_sae!(SAE); _mm_mask_cvt_roundsh_sd::(_mm_set_sd(0.0), k, a, b) @@ -16553,7 +16553,7 @@ pub const fn _mm512_cvtsh_h(a: __m512h) -> f16 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si16) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 { unsafe { simd_extract!(a.as_i16x8(), 0) } @@ -16564,7 +16564,7 @@ pub const fn _mm_cvtsi128_si16(a: __m128i) -> i16 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi16_si128) #[inline] #[target_feature(enable = "avx512fp16")] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_cvtsi16_si128(a: i16) -> __m128i { unsafe { transmute(simd_insert!(i16x8::ZERO, 0, a)) } diff --git a/stdarch/crates/core_arch/src/x86/avxneconvert.rs b/stdarch/crates/core_arch/src/x86/avxneconvert.rs index 91b6be2b09d78..b8a3b9473af9e 100644 --- a/stdarch/crates/core_arch/src/x86/avxneconvert.rs +++ b/stdarch/crates/core_arch/src/x86/avxneconvert.rs @@ -87,7 +87,7 @@ pub unsafe fn _mm256_cvtneebf16_ps(a: *const __m256bh) -> __m256 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneeph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 { transmute(cvtneeph2ps_128(a)) } @@ -99,7 +99,7 @@ pub unsafe fn _mm_cvtneeph_ps(a: *const __m128h) -> __m128 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneeph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm256_cvtneeph_ps(a: *const __m256h) -> __m256 { transmute(cvtneeph2ps_256(a)) } @@ -135,7 +135,7 @@ pub unsafe fn _mm256_cvtneobf16_ps(a: *const __m256bh) -> __m256 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneoph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 { transmute(cvtneoph2ps_128(a)) } @@ -147,7 +147,7 @@ pub unsafe fn _mm_cvtneoph_ps(a: *const __m128h) -> __m128 { #[inline] #[target_feature(enable = "avxneconvert")] #[cfg_attr(test, assert_instr(vcvtneoph2ps))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub unsafe fn _mm256_cvtneoph_ps(a: *const __m256h) -> __m256 { transmute(cvtneoph2ps_256(a)) } diff --git a/stdarch/crates/core_arch/src/x86/mod.rs b/stdarch/crates/core_arch/src/x86/mod.rs index c40fbd3ca3178..9396507f08045 100644 --- a/stdarch/crates/core_arch/src/x86/mod.rs +++ b/stdarch/crates/core_arch/src/x86/mod.rs @@ -401,7 +401,7 @@ types! { } types! { - #![stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] + #![stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] /// 128-bit wide set of 8 `f16` types, x86-specific /// @@ -768,7 +768,7 @@ mod avxneconvert; pub use self::avxneconvert::*; mod avx512fp16; -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub use self::avx512fp16::*; mod kl; diff --git a/stdarch/crates/core_arch/src/x86/sse.rs b/stdarch/crates/core_arch/src/x86/sse.rs index b83274e60e72a..2c4439a3f3a55 100644 --- a/stdarch/crates/core_arch/src/x86/sse.rs +++ b/stdarch/crates/core_arch/src/x86/sse.rs @@ -968,7 +968,7 @@ pub const fn _mm_set_ps1(a: f32) -> __m128 { /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_ps) #[inline] #[target_feature(enable = "sse")] -#[cfg_attr(test, assert_instr(unpcklps))] +// This intrinsic has no corresponding instruction. #[stable(feature = "simd_x86", since = "1.27.0")] #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")] pub const fn _mm_set_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 { diff --git a/stdarch/crates/core_arch/src/x86/ssse3.rs b/stdarch/crates/core_arch/src/x86/ssse3.rs index 4426a3274c380..1d7a97944a37b 100644 --- a/stdarch/crates/core_arch/src/x86/ssse3.rs +++ b/stdarch/crates/core_arch/src/x86/ssse3.rs @@ -188,7 +188,13 @@ pub const fn _mm_hadd_epi16(a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(phaddsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm_hadds_epi16(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(phaddsw128(a.as_i16x8(), b.as_i16x8())) } + let a = a.as_i16x8(); + let b = b.as_i16x8(); + unsafe { + let even: i16x8 = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let odd: i16x8 = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_saturating_add(even, odd).as_m128i() + } } /// Horizontally adds the adjacent pairs of values contained in 2 packed @@ -240,7 +246,13 @@ pub const fn _mm_hsub_epi16(a: __m128i, b: __m128i) -> __m128i { #[cfg_attr(test, assert_instr(phsubsw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub fn _mm_hsubs_epi16(a: __m128i, b: __m128i) -> __m128i { - unsafe { transmute(phsubsw128(a.as_i16x8(), b.as_i16x8())) } + let a = a.as_i16x8(); + let b = b.as_i16x8(); + unsafe { + let even: i16x8 = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let odd: i16x8 = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + simd_saturating_sub(even, odd).as_m128i() + } } /// Horizontally subtract the adjacent pairs of values contained in 2 @@ -337,12 +349,6 @@ unsafe extern "C" { #[link_name = "llvm.x86.ssse3.pshuf.b.128"] fn pshufb128(a: u8x16, b: u8x16) -> u8x16; - #[link_name = "llvm.x86.ssse3.phadd.sw.128"] - fn phaddsw128(a: i16x8, b: i16x8) -> i16x8; - - #[link_name = "llvm.x86.ssse3.phsub.sw.128"] - fn phsubsw128(a: i16x8, b: i16x8) -> i16x8; - #[link_name = "llvm.x86.ssse3.pmadd.ub.sw.128"] fn pmaddubsw128(a: u8x16, b: i8x16) -> i16x8; diff --git a/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs b/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs index 87e3651ba7441..2a511328bb382 100644 --- a/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs +++ b/stdarch/crates/core_arch/src/x86_64/avx512fp16.rs @@ -10,7 +10,7 @@ use stdarch_test::assert_instr; #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvti64_sh(a: __m128h, b: i64) -> __m128h { unsafe { vcvtsi642sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -32,7 +32,7 @@ pub fn _mm_cvti64_sh(a: __m128h, b: i64) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundi64_sh(a: __m128h, b: i64) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -48,7 +48,7 @@ pub fn _mm_cvt_roundi64_sh(a: __m128h, b: i64) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtu64_sh(a: __m128h, b: u64) -> __m128h { unsafe { vcvtusi642sh(a, b, _MM_FROUND_CUR_DIRECTION) } } @@ -70,7 +70,7 @@ pub fn _mm_cvtu64_sh(a: __m128h, b: u64) -> __m128h { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtusi2sh, ROUNDING = 8))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundu64_sh(a: __m128h, b: u64) -> __m128h { unsafe { static_assert_rounding!(ROUNDING); @@ -85,7 +85,7 @@ pub fn _mm_cvt_roundu64_sh(a: __m128h, b: u64) -> __m128h { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_i64(a: __m128h) -> i64 { unsafe { vcvtsh2si64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -106,7 +106,7 @@ pub fn _mm_cvtsh_i64(a: __m128h) -> i64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2si, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_i64(a: __m128h) -> i64 { unsafe { static_assert_rounding!(ROUNDING); @@ -121,7 +121,7 @@ pub fn _mm_cvt_roundsh_i64(a: __m128h) -> i64 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtsh_u64(a: __m128h) -> u64 { unsafe { vcvtsh2usi64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -142,7 +142,7 @@ pub fn _mm_cvtsh_u64(a: __m128h) -> u64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvtsh2usi, ROUNDING = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvt_roundsh_u64(a: __m128h) -> u64 { unsafe { static_assert_rounding!(ROUNDING); @@ -157,7 +157,7 @@ pub fn _mm_cvt_roundsh_u64(a: __m128h) -> u64 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_i64(a: __m128h) -> i64 { unsafe { vcvttsh2si64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -172,7 +172,7 @@ pub fn _mm_cvttsh_i64(a: __m128h) -> i64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2si, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_i64(a: __m128h) -> i64 { unsafe { static_assert_sae!(SAE); @@ -187,7 +187,7 @@ pub fn _mm_cvtt_roundsh_i64(a: __m128h) -> i64 { #[inline] #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi))] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvttsh_u64(a: __m128h) -> u64 { unsafe { vcvttsh2usi64(a, _MM_FROUND_CUR_DIRECTION) } } @@ -202,7 +202,7 @@ pub fn _mm_cvttsh_u64(a: __m128h) -> u64 { #[target_feature(enable = "avx512fp16")] #[cfg_attr(test, assert_instr(vcvttsh2usi, SAE = 8))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub fn _mm_cvtt_roundsh_u64(a: __m128h) -> u64 { unsafe { static_assert_sae!(SAE); diff --git a/stdarch/crates/core_arch/src/x86_64/mod.rs b/stdarch/crates/core_arch/src/x86_64/mod.rs index c6dc7a85e7852..9caab44e46cd7 100644 --- a/stdarch/crates/core_arch/src/x86_64/mod.rs +++ b/stdarch/crates/core_arch/src/x86_64/mod.rs @@ -75,7 +75,7 @@ mod bt; pub use self::bt::*; mod avx512fp16; -#[stable(feature = "stdarch_x86_avx512fp16", since = "CURRENT_RUSTC_VERSION")] +#[stable(feature = "stdarch_x86_avx512fp16", since = "1.94.0")] pub use self::avx512fp16::*; mod amx; diff --git a/stdarch/crates/intrinsic-test/src/common/compare.rs b/stdarch/crates/intrinsic-test/src/common/compare.rs index 5214349171591..c22d7fd4ec0aa 100644 --- a/stdarch/crates/intrinsic-test/src/common/compare.rs +++ b/stdarch/crates/intrinsic-test/src/common/compare.rs @@ -109,13 +109,26 @@ pub fn compare_outputs( } }) .inspect(|(intrinsic, diffs)| { - println!("Difference for intrinsic: {intrinsic}"); + use std::io::Write; + + let stdout = std::io::stdout(); + let mut out = stdout.lock(); + + writeln!(out, "Difference for intrinsic: {intrinsic}").unwrap(); diffs.into_iter().for_each(|diff| match diff { - diff::Result::Left(c) => println!("C: {c}"), - diff::Result::Right(rust) => println!("Rust: {rust}"), + diff::Result::Left(c) => { + writeln!(out, "C: {c}").unwrap(); + } + diff::Result::Right(rust) => { + writeln!(out, "Rust: {rust}").unwrap(); + } _ => (), }); - println!("****************************************************************"); + writeln!( + out, + "****************************************************************" + ) + .unwrap(); }) .count(); diff --git a/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index a9bc377924dd0..9190c8518a667 100644 --- a/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -13,9 +13,9 @@ auto_llvm_sign_conversion: false neon-stable: &neon-stable FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] -# #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +# #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] neon-stable-fp16: &neon-stable-fp16 - FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']] + FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']] # #[cfg(not(target_arch = "arm64ec"))] target-not-arm64ec: &target-not-arm64ec @@ -70,6 +70,10 @@ aarch64-stable-jscvt: &aarch64-stable-jscvt neon-unstable-feat-lrcpc3: &neon-unstable-feat-lrcpc3 FnCall: [unstable, ['feature = "stdarch_neon_feat_lrcpc3"', 'issue = "none"']] +# #[cfg(target_has_atomic = "64")] +cfg-target-has-atomic-64: &cfg-target-has-atomic-64 + FnCall: [cfg, ['target_has_atomic = "64"']] + # #[unstable(feature = "stdarch_neon_fp8", issue = "none")] neon-unstable-fp8: &neon-unstable-fp8 FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']] @@ -3475,10 +3479,10 @@ intrinsics: - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" - arguments: ["a: {type[0]}"] + arguments: ["ptr: {type[0]}"] return_type: "{neon_type[1]}" attr: [*neon-stable] - assert_instr: [ld1] + assert_instr: [ld] safety: unsafe: [neon] types: @@ -3489,11 +3493,12 @@ intrinsics: - ["*const f64", float64x1x4_t] - ["*const f64", float64x2x4_t] compose: - - LLVMLink: - name: "vld1{neon_type[1].no}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: aarch64,arm64ec + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - ptr + - cast + - [] - name: "vld2{neon_type[1].lane_nox}" doc: Load multiple 2-element structures to two registers @@ -3694,16 +3699,12 @@ intrinsics: types: - ["*const f64", float64x1x2_t, f64, float64x1_t] compose: - - LLVMLink: - name: "vld2.{neon_type[1]}" - arguments: - - "ptr: *const {neon_type[3]}" - links: - - link: "llvm.aarch64.neon.ld2.v{neon_type[1].lane}{type[2]}.p0" - arch: aarch64,arm64ec - FnCall: - - "_vld2{neon_type[1].nox}" - - - "a as _" + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld2{neon_type[1].nox}" doc: Load multiple 2-element structures to two registers @@ -3711,6 +3712,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [ld2] + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4052,20 +4054,19 @@ intrinsics: types: - ['*const f64', float64x1x3_t, '*const float64x1_t', f64] compose: - - LLVMLink: - name: 'vld3{neon_type[1].nox}' - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers arguments: ["a: {type[0]}"] return_type: "{neon_type[1]}" attr: [*neon-stable] + big_endian_inverse: false safety: unsafe: [neon] assert_instr: [ld3] @@ -4197,14 +4198,12 @@ intrinsics: types: - ['*const f64', float64x1x4_t, f64, '*const float64x1_t'] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld4{neon_type[1].nox}" doc: Load multiple 4-element structures to four registers @@ -4212,6 +4211,7 @@ intrinsics: return_type: "{neon_type[1]}" attr: [*neon-stable] assert_instr: [ld4] + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4319,6 +4319,7 @@ intrinsics: - *neon-stable static_defs: - "const LANE: i32" + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4368,6 +4369,7 @@ intrinsics: - *neon-stable static_defs: - "const LANE: i32" + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4418,6 +4420,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*const i64', int64x1_t, 'static_assert!', 'LANE == 0'] - ['*const i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1'] @@ -4448,6 +4451,7 @@ intrinsics: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0',''] #- ['*const f64', float64x1_t,'static_assert!', 'LANE == 0',''] # Fails due to bad IR gen from rust @@ -4474,6 +4478,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*mut i64', int64x1_t,'static_assert!', 'LANE == 0'] - ['*mut i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1'] @@ -4502,6 +4507,7 @@ intrinsics: - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] - FnCall: [rustc_legacy_const_generics, ["2"]] - *neon-unstable-feat-lrcpc3 + - *cfg-target-has-atomic-64 types: - ['*mut u64', uint64x1_t, 'static_assert!', 'LANE == 0',''] - ['*mut f64', float64x1_t,'static_assert!', 'LANE == 0',''] @@ -6956,28 +6962,29 @@ intrinsics: - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]] - FnCall: ["vmovl{neon_type[0].noq}", [a]] - - name: "vpadd{neon_type.no}" - doc: Floating-point add pairwise - arguments: ["a: {neon_type}", "b: {neon_type}"] - return_type: "{type}" + - name: "vpadd{neon_type[0].no}" + doc: "Floating-point add pairwise" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" attr: [*neon-stable] assert_instr: [faddp] safety: safe types: - - float32x4_t - - float64x2_t + - [float32x4_t, "4"] + - [float64x2_t, "2"] compose: - - LLVMLink: - name: "faddp.{neon_type}" - links: - - link: "llvm.aarch64.neon.faddp.{neon_type}" - arch: aarch64,arm64ec - + - Let: + - even + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]] + - Let: + - odd + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]] + - FnCall: [simd_add, [even, odd]] - - name: "vpadd{neon_type.no}" + - name: "vpadd{neon_type[0].no}" doc: Floating-point add pairwise - arguments: ["a: {neon_type}", "b: {neon_type}"] - return_type: "{type}" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" attr: - *neon-fp16 - *neon-stable-fp16 @@ -6985,14 +6992,15 @@ intrinsics: assert_instr: [faddp] safety: safe types: - - float16x8_t + - [float16x8_t, "8"] compose: - - LLVMLink: - name: "faddp.{neon_type}" - links: - - link: "llvm.aarch64.neon.faddp.{neon_type}" - arch: aarch64,arm64ec - + - Let: + - even + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]] + - Let: + - odd + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]] + - FnCall: [simd_add, [even, odd]] - name: "vpmax{neon_type.no}" doc: Floating-point add pairwise @@ -8958,7 +8966,7 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] @@ -8983,7 +8991,7 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] @@ -9008,7 +9016,7 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] @@ -9037,7 +9045,7 @@ intrinsics: arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] return_type: "{neon_type[2]}" attr: - - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]] - FnCall: [rustc_legacy_const_generics, ['1', '3']] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] static_defs: ['const LANE1: i32, const LANE2: i32'] @@ -10158,7 +10166,7 @@ intrinsics: attr: - *neon-stable - FnCall: [rustc_legacy_const_generics, ['2']] - - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sri, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [bfxil, 'N = 2']]}]] safety: safe types: - i64 @@ -12168,6 +12176,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8_t, uint8x8x4_t, uint8x8_t] @@ -12235,6 +12244,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8x2_t, 'uint8x8_t', 'uint8x8_t'] @@ -12288,7 +12298,7 @@ intrinsics: types: - [uint8x8x3_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - [poly8x8x3_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] - big_endian_inverse: true + big_endian_inverse: false compose: - Let: - x @@ -12340,7 +12350,7 @@ intrinsics: types: - [uint8x8x4_t, 'uint8x8_t', 'uint8x16x2', 'uint8x8_t'] - [poly8x8x4_t, 'uint8x8_t', 'poly8x16x2', 'poly8x8_t'] - big_endian_inverse: true + big_endian_inverse: false compose: - Let: - x @@ -12449,6 +12459,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8_t, 'uint8x8x2_t', uint8x8_t] @@ -12510,7 +12521,7 @@ intrinsics: types: - [uint8x8_t, 'uint8x8x3_t', 'uint8x16x2', 'u8x8::splat(24)', 'uint8x8'] - [poly8x8_t, 'poly8x8x3_t', 'poly8x16x2', 'u8x8::splat(24)', 'poly8x8'] - big_endian_inverse: true + big_endian_inverse: false compose: - Let: - x @@ -12593,6 +12604,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ['uint8x16x2_t', uint8x8_t, 'vqtbl2', 'uint8x8_t'] @@ -12629,6 +12641,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8_t, 'uint8x16x2_t', uint8x8_t, 'vqtbx2'] @@ -12652,6 +12665,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ['int8x8_t', 'int8x16x3_t', uint8x8_t, 'vqtbl3'] @@ -12666,6 +12680,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ['uint8x8_t', 'uint8x16x3_t', uint8x8_t, 'vqtbl3'] @@ -12703,6 +12718,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8_t, 'uint8x16x3_t', uint8x8_t, 'vqtbx3'] @@ -12727,6 +12743,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ['int8x16x4_t', uint8x8_t, 'vqtbl4', 'int8x8_t'] @@ -12741,6 +12758,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ['uint8x16x4_t', uint8x8_t, 'vqtbl4', 'uint8x8_t'] @@ -12779,6 +12797,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbx]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - [uint8x8_t, 'uint8x16x4_t', uint8x8_t, 'vqtbx4'] @@ -12843,6 +12862,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ["vqtbl3", int8x16_t, uint8x8_t, int8x8_t] @@ -12862,6 +12882,7 @@ intrinsics: attr: - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tbl]]}]] - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + big_endian_inverse: false safety: safe types: - ["vqtbl4", int8x16_t, uint8x8_t, int8x8_t] @@ -13217,26 +13238,6 @@ intrinsics: - link: "llvm.aarch64.neon.usqadd.{neon_type[1]}" arch: aarch64,arm64ec - - name: "vpadd{neon_type.no}" - doc: "Add Pairwise" - arguments: ["a: {neon_type}", "b: {neon_type}"] - return_type: "{neon_type}" - attr: - - *neon-stable - assert_instr: [addp] - safety: safe - types: - - int8x16_t - - int16x8_t - - int32x4_t - - int64x2_t - compose: - - LLVMLink: - name: "vpadd{neon_type.no}" - links: - - link: "llvm.aarch64.neon.addp.{neon_type}" - arch: aarch64,arm64ec - - name: "vpadd{neon_type[0].no}" doc: "Add Pairwise" arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] @@ -13246,17 +13247,22 @@ intrinsics: assert_instr: [addp] safety: safe types: - - [uint8x16_t, int8x16_t] - - [uint16x8_t, int16x8_t] - - [uint32x4_t, int32x4_t] - - [uint64x2_t, int64x2_t] + - [int8x16_t, "16"] + - [int16x8_t, "8"] + - [int32x4_t, "4"] + - [int64x2_t, "2"] + - [uint8x16_t, "16"] + - [uint16x8_t, "8"] + - [uint32x4_t, "4"] + - [uint64x2_t, "2"] compose: - - FnCall: - - transmute - - - FnCall: - - 'vpadd{neon_type[1].no}' - - - FnCall: [transmute, [a]] - - FnCall: [transmute, [b]] + - Let: + - even + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::even::<{type[1]}>()"]] + - Let: + - odd + - FnCall: ["simd_shuffle!", [a, b, "crate::core_arch::macros::odd::<{type[1]}>()"]] + - FnCall: [simd_add, [even, odd]] - name: "vpaddd_s64" doc: "Add pairwise" @@ -13714,26 +13720,17 @@ intrinsics: static_defs: ['const N: i32'] safety: safe types: - - [int8x8_t, 'N >= 1 && N <= 8'] - - [int8x16_t, 'N >= 1 && N <= 8'] - - [int16x4_t, 'N >= 1 && N <= 16'] - - [int16x8_t, 'N >= 1 && N <= 16'] - - [int32x2_t, 'N >= 1 && N <= 32'] - - [int32x4_t, 'N >= 1 && N <= 32'] - - [int64x1_t, 'N >= 1 && N <= 64'] - - [int64x2_t, 'N >= 1 && N <= 64'] + - [int8x8_t, u8, '8', 'N >= 1 && N <= 8'] + - [int8x16_t, u8, '16', 'N >= 1 && N <= 8'] + - [int16x4_t, u16, '4', 'N >= 1 && N <= 16'] + - [int16x8_t, u16, '8', 'N >= 1 && N <= 16'] + - [int32x2_t, u32, '2', 'N >= 1 && N <= 32'] + - [int32x4_t, u32, '4', 'N >= 1 && N <= 32'] + - [int64x1_t, u64, '1', 'N >= 1 && N <= 64'] + - [int64x2_t, u64, '2', 'N >= 1 && N <= 64'] compose: - - FnCall: ['static_assert!', ['{type[1]}']] - - LLVMLink: - name: "vsri{neon_type[0].N}" - arguments: - - "a: {neon_type[0]}" - - "b: {neon_type[0]}" - - "n: i32" - links: - - link: "llvm.aarch64.neon.vsri.{neon_type[0]}" - arch: aarch64,arm64ec - - FnCall: ["_vsri{neon_type[0].N}", [a, b, N], [], true] + - FnCall: ['static_assert!', ['{type[3]}']] + - FnCall: ["super::shift_right_and_insert!", ['{type[1]}', '{type[2]}', N, a, b], [], true] - name: "vsri{neon_type[0].N}" doc: "Shift Right and Insert (immediate)" diff --git a/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index 52748a4cc056d..8e10fff984ac7 100644 --- a/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml +++ b/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -10,9 +10,9 @@ auto_big_endian: true neon-stable: &neon-stable FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] -# #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")] +# #[stable(feature = "stdarch_neon_fp16", since = "1.94.0")] neon-stable-fp16: &neon-stable-fp16 - FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']] + FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']] # #[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] neon-cfg-arm-unstable: &neon-cfg-arm-unstable @@ -55,9 +55,9 @@ neon-target-aarch64-arm64ec: &neon-target-aarch64-arm64ec neon-not-arm-stable: &neon-not-arm-stable FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] -# #[cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION"))] +# #[cfg_attr(not(target_arch = "arm"), stable(feature = "stdarch_neon_fp16", since = "1.94.0"))] neon-not-arm-stable-fp16: &neon-not-arm-stable-fp16 - FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "CURRENT_RUSTC_VERSION"']]}]] + FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "stdarch_neon_fp16"', 'since = "1.94.0"']]}]] # #[cfg_attr(all(test, not(target_env = "msvc"))] msvc-disabled: &msvc-disabled @@ -2603,8 +2603,8 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2617,13 +2617,12 @@ intrinsics: - ["*const f32", float32x2x4_t] - ["*const f32", float32x4x4_t] compose: - - LLVMLink: - name: "vld1x{neon_type[1].tuple}.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: arm + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2631,8 +2630,8 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2663,13 +2662,12 @@ intrinsics: - ["*const i64", int64x2x3_t] - ["*const i64", int64x2x4_t] compose: - - LLVMLink: - name: "ld1x{neon_type[1].tuple}.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}i{neon_type[1].base}.p0" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}i{neon_type[1].base}.p0" - arch: arm + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2677,10 +2675,11 @@ intrinsics: return_type: "{neon_type[1]}" attr: - *neon-v7 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -2722,12 +2721,11 @@ intrinsics: - ["*const p16", poly16x8x4_t, int16x8x4_t] compose: - FnCall: - - transmute - - - FnCall: - - "vld1{neon_type[2].no}" - - - FnCall: - - transmute - - - a + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2737,9 +2735,10 @@ intrinsics: - *neon-aes - *neon-v8 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -2750,12 +2749,11 @@ intrinsics: - ["*const p64", poly64x2x4_t, int64x2x4_t] compose: - FnCall: - - transmute - - - FnCall: - - "vld1{neon_type[2].no}" - - - FnCall: - - transmute - - - a + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2764,8 +2762,8 @@ intrinsics: attr: - *neon-aes - *neon-v8 - - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable safety: @@ -2774,12 +2772,11 @@ intrinsics: - ["*const p64", poly64x1x2_t, int64x1x2_t] compose: - FnCall: - - transmute - - - FnCall: - - "vld1{neon_type[2].no}" - - - FnCall: - - transmute - - - a + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{neon_type[1].no}" doc: "Load multiple single-element structures to one, two, three, or four registers" @@ -2788,7 +2785,7 @@ intrinsics: attr: - *neon-v7 - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] - - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld]]}]] - *arm-fp16 - *neon-unstable-f16 - *target-not-arm64ec @@ -2802,13 +2799,12 @@ intrinsics: - ["*const f16", float16x4x4_t] - ["*const f16", float16x8x4_t] compose: - - LLVMLink: - name: "vld1x{neon_type[1].tuple}.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0" - arch: arm + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld1{type[2]}_{neon_type[1]}" doc: "Load one single-element structure to one lane of one register" @@ -2980,6 +2976,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -3010,6 +3007,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -3106,6 +3104,7 @@ intrinsics: - *neon-cfg-arm-unstable static_defs: - "const LANE: i32" + big_endian_inverse: false safety: unsafe: [neon] types: @@ -3670,19 +3669,11 @@ intrinsics: safety: unsafe: [neon] types: - - ["*const f16", float16x4x3_t, f16] - - ["*const f16", float16x8x3_t, f16] + - ["*const f16", float16x4x3_t, f16, "4"] + - ["*const f16", float16x8x3_t, f16, "8"] compose: - - LLVMLink: - name: "vld3.{neon_type[1]}" - arguments: - - "ptr: {type[0]}" - links: - - link: "llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[2]}.p0" - arch: aarch64,arm64ec - - FnCall: - - "_vld3{neon_type[1].nox}" - - - "a as _" + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true] + - name: "vld3{neon_type[1].dup_nox}" doc: Load single 3-element structure and replicate to all lanes of two registers @@ -3876,23 +3867,17 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const i8', int8x8x3_t, '*const int8x8_t', i8] - - ['*const i16', int16x4x3_t, '*const int16x4_t', i16] - - ['*const i32', int32x2x3_t, '*const int32x2_t', i32] - - ['*const i8', int8x16x3_t, '*const int8x16_t', i8] - - ['*const i16', int16x8x3_t, '*const int16x8_t', i16] - - ['*const i32', int32x4x3_t, '*const int32x4_t', i32] - - ['*const f32', float32x2x3_t, '*const float32x2_t', f32] - - ['*const f32', float32x4x3_t, '*const float32x4_t', f32] + - ['*const i8', int8x8x3_t, i8, "8"] + - ['*const i16', int16x4x3_t, i16, "4"] + - ['*const i32', int32x2x3_t, i32, "2"] + - ['*const i8', int8x16x3_t, i8, "16"] + - ['*const i16', int16x8x3_t, i16, "8"] + - ['*const i32', int32x4x3_t, i32, "4"] + - ['*const f32', float32x2x3_t, f32, "2"] + - ['*const f32', float32x4x3_t, f32, "4"] compose: - - LLVMLink: - name: 'vld3{neon_type[1].nox}' - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "3", a], [], true] + - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers @@ -3907,14 +3892,12 @@ intrinsics: types: - ['*const i64', int64x1x3_t, '*const int64x1_t', i64] compose: - - LLVMLink: - name: "vld3{neon_type[1].nox}" - arguments: - - 'ptr: {type[2]}' - links: - - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld3{neon_type[1].nox}" doc: Load multiple 3-element structures to three registers @@ -4110,6 +4093,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable static_defs: ['const LANE: i32'] + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4140,6 +4124,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4372,23 +4357,16 @@ intrinsics: safety: unsafe: [neon] types: - - ['*const i8', int8x8x4_t, i8, '*const int8x8_t'] - - ['*const i32', int32x4x4_t, i32, '*const int32x4_t'] - - ['*const i16', int16x4x4_t, i16, '*const int16x4_t'] - - ['*const i32', int32x2x4_t, i32, '*const int32x2_t'] - - ['*const i8', int8x16x4_t, i8, '*const int8x16_t'] - - ['*const i16', int16x8x4_t, i16, '*const int16x8_t'] - - ['*const f32', float32x2x4_t, f32, '*const float32x2_t'] - - ['*const f32', float32x4x4_t, f32, '*const float32x4_t'] + - ['*const i8', int8x8x4_t, i8, "8"] + - ['*const i32', int32x4x4_t, i32, "4"] + - ['*const i16', int16x4x4_t, i16, "4"] + - ['*const i32', int32x2x4_t, i32, "2"] + - ['*const i8', int8x16x4_t, i8, "16"] + - ['*const i16', int16x8x4_t, i16, "8"] + - ['*const f32', float32x2x4_t, f32, "2"] + - ['*const f32', float32x4x4_t, f32, "4"] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true] - name: "vld4{neon_type[1].nox}" doc: Load multiple 4-element structures to four registers @@ -4401,14 +4379,12 @@ intrinsics: types: - ['*const i64', int64x1x4_t, i64, '*const int64x1_t'] compose: - - LLVMLink: - name: 'vld4{neon_type[1].nox}' - arguments: - - 'ptr: {type[3]}' - links: - - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0' - arch: aarch64,arm64ec - - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + - FnCall: + - 'crate::ptr::read_unaligned' + - - MethodCall: + - a + - cast + - [] - name: "vld4{neon_type[1].lane_nox}" doc: Load multiple 4-element structures to four registers @@ -4512,6 +4488,7 @@ intrinsics: - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld4]]}]] - *neon-not-arm-stable - *neon-cfg-arm-unstable + big_endian_inverse: false safety: unsafe: [neon] types: @@ -4633,6 +4610,7 @@ intrinsics: - *neon-not-arm-stable - *neon-cfg-arm-unstable static_defs: ["const LANE: i32"] + big_endian_inverse: false safety: unsafe: [neon] types: @@ -6511,13 +6489,10 @@ intrinsics: - ["s16", int16x4_t, int32x4_t] - ["s32", int32x2_t, int64x2_t] compose: - - LLVMLink: - name: "smull.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.smull.{neon_type[2]}" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vmulls.{neon_type[2]}" - arch: arm + - FnCall: + - simd_mul + - - FnCall: ['simd_cast', [a]] + - FnCall: ['simd_cast', [b]] - name: "vmull{neon_type[1].no}" doc: "Unsigned multiply long" @@ -6535,13 +6510,10 @@ intrinsics: - ["u16", uint16x4_t, uint32x4_t] - ["u32", uint32x2_t, uint64x2_t] compose: - - LLVMLink: - name: "smull.{neon_type[1]}" - links: - - link: "llvm.aarch64.neon.umull.{neon_type[2]}" - arch: aarch64,arm64ec - - link: "llvm.arm.neon.vmullu.{neon_type[2]}" - arch: arm + - FnCall: + - simd_mul + - - FnCall: ['simd_cast', [a]] + - FnCall: ['simd_cast', [b]] - name: "vmull{neon_type[1].no}" doc: "Polynomial multiply long" @@ -12437,19 +12409,10 @@ intrinsics: safety: unsafe: [neon] types: - - ["*const f16", float16x4x4_t, f16] - - ["*const f16", float16x8x4_t, f16] + - ["*const f16", float16x4x4_t, f16, "4"] + - ["*const f16", float16x8x4_t, f16, "8"] compose: - - LLVMLink: - name: "vld4.{neon_type[1]}" - arguments: - - "ptr: {type[0]}" - links: - - link: "llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0" - arch: aarch64,arm64ec - - FnCall: - - "_vld4{neon_type[1].nox}" - - - "a as _" + - FnCall: ["crate::core_arch::macros::deinterleaving_load!", [{ Type: "{type[2]}" }, "{type[3]}", "4", a], [], true] - name: "vld4{neon_type[1].dup_nox}" doc: Load single 4-element structure and replicate to all lanes of two registers diff --git a/stdarch/crates/stdarch-gen-arm/src/main.rs b/stdarch/crates/stdarch-gen-arm/src/main.rs index 9bf7d0981deb9..e14e2782485b9 100644 --- a/stdarch/crates/stdarch-gen-arm/src/main.rs +++ b/stdarch/crates/stdarch-gen-arm/src/main.rs @@ -139,6 +139,7 @@ fn parse_args() -> Vec<(PathBuf, Option)> { .into_iter() .filter_map(Result::ok) .filter(|f| f.file_type().is_file()) + .filter(|f| f.file_name().to_string_lossy().ends_with(".yml")) .map(|f| (f.into_path(), out_dir.clone())) .collect() } diff --git a/stdarch/crates/stdarch-gen-hexagon/Cargo.toml b/stdarch/crates/stdarch-gen-hexagon/Cargo.toml new file mode 100644 index 0000000000000..397c7816f8d1e --- /dev/null +++ b/stdarch/crates/stdarch-gen-hexagon/Cargo.toml @@ -0,0 +1,9 @@ +[package] +name = "stdarch-gen-hexagon" +version = "0.1.0" +authors = ["The Rust Project Developers"] +license = "MIT OR Apache-2.0" +edition = "2021" + +[dependencies] +regex = "1.10" diff --git a/stdarch/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h b/stdarch/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h new file mode 100644 index 0000000000000..19309a40d6dd1 --- /dev/null +++ b/stdarch/crates/stdarch-gen-hexagon/hvx_hexagon_protos.h @@ -0,0 +1,6003 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// Automatically generated file, do not edit! +//===----------------------------------------------------------------------===// + + +#ifndef _HVX_HEXAGON_PROTOS_H_ +#define _HVX_HEXAGON_PROTOS_H_ 1 + +#ifdef __HVX__ +#if __HVX_LENGTH__ == 128 +#define __BUILTIN_VECTOR_WRAP(a) a ## _128B +#else +#define __BUILTIN_VECTOR_WRAP(a) a +#endif + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Rd32=vextract(Vu32,Rs32) + C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs) + Instruction Type: LD + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=hi(Vss32) + C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=lo(Vss32) + C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vsplat(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=and(Qs4,Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=and(Qs4,!Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=not(Qs4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=or(Qs4,Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=or(Qs4,!Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vsetq(Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=xor(Qs4,Qt4) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) vmem(Rt32+#s4)=Vs32 + C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) vmem(Rt32+#s4):nt=Vs32 + C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) vmem(Rt32+#s4):nt=Vs32 + C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) vmem(Rt32+#s4)=Vs32 + C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) + Instruction Type: CVI_VM_ST + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vabsdiff(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vabsdiff(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vabs(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vabs(Vu32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vabs(Vu32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vabs(Vu32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.b+=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.b+=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.h+=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.h+=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vadd(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wub_vadd_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vadd_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vadd_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vadd_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vadd_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.w+=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condacc_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.w+=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condacc_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vadd_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=valign(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=valign(Vu32,Vv32,#u3) + C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_valign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vand(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vand(Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QR(HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32|=vand(Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vand(Vu32,Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vand_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)(Vu,Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vand(Vu32,Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Q_vandor_QVR(Qx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasl(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasl_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasl(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasl(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasl_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vasl(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vaslacc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasl(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasr(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasr_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vasr(Vu32.w,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasracc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VwVwR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vasr(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vasr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=Vu32 + C Intrinsic Prototype: HVX_Vector Q6_V_equals_V(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=Vuu32 + C Intrinsic Prototype: HVX_VectorPair Q6_W_equals_W(HVX_VectorPair Vuu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_equals_W(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)(Vuu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vavg_VhVh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vavg_VubVub_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vavg_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vavg_VuhVuh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vavg_VwVw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vcl0(Vu32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcl0_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vcl0_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vcl0(Vu32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vcl0_Vuw(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vcl0_Vuw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vcombine(Vu32,Vv32) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vcombine_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=#0 + C Intrinsic Prototype: HVX_Vector Q6_V_vzero() + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)() +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vdeal(Vu32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeal_Vb(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vdeal_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vdeale(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vdeale_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vdeal(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vdeal_Vh(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vdeal_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vdeal(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vdeal_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vdelta(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vdmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpy_VubRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vdmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vdmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vdmpyacc_VhVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vdmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vdmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vdmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vdmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vdmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vdmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vdmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_WhRh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwWhRh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)(Vx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhRh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhRh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_WhRuh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwWhRuh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)(Vx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhRuh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhRuh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpy_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vdmpyacc_VwVhVh_sat(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vdsad_WuhRuh(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vdsadacc_WuwWuhRuh(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w=vinsert(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vinsert_VwR(HVX_Vector Vx, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vinsert_VwR(Vx,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)(Vx,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vlalign(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vlalign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vlalign(Vu32,Vv32,#u3) + C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vlalign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vlsr(Vu32.uh,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vlsr_VuhR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vlsr_VuhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vlsr(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vlsr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vlsr(Vu32.uw,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vlsr_VuwR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vlsr_VuwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vlsr(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vlsr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32_VbVbR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32or_VbVbVbR(Vx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)(Vx,Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16_VbVhR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16or_WhVbVhR(Vxx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)(Vxx,Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmax(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vmax_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vmax(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vmax_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vmax(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vmax_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmax(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vmax_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmin(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vmin_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vmin(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vmin_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vmin(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vmin_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmin(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vmin_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpaacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubWub(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpa(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpa_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpa(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpaacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpyacc_WhVubRb(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpyacc_WhVubVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpyacc_WhVbVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpye(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Rt32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpy_VhRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhRh_sat(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpy_VhRh_s1_rnd_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpy_VhRh_s1_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpy_VhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpy_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpy_VhVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyieo(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyieo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyieacc_VwVwVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyie(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyie_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyieacc_VwVwVuh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyi_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyiacc_VhVhVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyi_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vmpyiacc_VhVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyio(Vu32.w,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyio_VwVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyi_VwRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyiacc_VwVwRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyi_VwRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyiacc_VwVwRh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyo_VwVh_s1_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpyacc_WuhVubRub(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuh_vmpyacc_WuhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpy_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpyacc_WuwVuhRuh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpy_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vmpyacc_WuwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vmux(Qt4,Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vmux_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vnavg(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vnavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vnavg(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vnavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vnavg(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vnavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vnormamt(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vnormamt_Vh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vnormamt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vnormamt(Vu32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vnormamt_Vw(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vnormamt_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vnot(Vu32) + C Intrinsic Prototype: HVX_Vector Q6_V_vnot_V(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vnot_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vor(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vor_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vpacke(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vpacke_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpacke(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpacke_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vpack(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vpack(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vpacko(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vpacko_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpacko(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpacko_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpack(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vpack(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vpopcount(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vpopcount_Vh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vpopcount_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vrdelta(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vrdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubRb(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpyacc_VwVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vrmpy_WubRbI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)(Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vrmpyacc_WwWubRbI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)(Vxx,Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpyacc_VwVubVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vrmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vrmpy(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vrmpyacc_VwVbVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpyacc_VuwVubRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrmpy_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)(Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrmpyacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)(Vxx,Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vrmpyacc_VuwVubVub(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vror(Vu32,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vror_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vror_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vround(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vround(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vround(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vround(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrsad_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)(Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wuw_vrsadacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)(Vxx,Vuu,Rt,Iu1) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vsat(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vsat_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsat(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vsat_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsxt(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsxt_Vb(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vsxt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsxt(Vu32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsxt_Vh(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vsxt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vshuffe(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vshuffe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vshuff(Vu32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuff_Vb(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vshuff_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vshuffe(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vshuffe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vshuff(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuff_Vh(HVX_Vector Vu) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vshuff_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vshuffo(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vshuffo_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vshuff(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vshuff_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vshuffoe(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vshuffoe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vshuffoe(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vshuffoe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vshuffo(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vshuffo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vsub_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vsub_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.b-=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condnac_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.b-=Vu32.b + C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_condnac_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vsub_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.h-=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condnac_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.h-=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_condnac_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vsub_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vsub_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vsub(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vsub_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vsub_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wub_vsub_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vsub_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vsub_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vsub_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsub_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vsub_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (!Qv4) Vx32.w-=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condnac_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: if (Qv4) Vx32.w-=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_condnac_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w):sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsub_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vsub_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32=vswap(Qt4,Vu32,Vv32) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vswap_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vtmpy(Vuu32.b,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpy_WbRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.b,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpyacc_WhWbRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vtmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vtmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vtmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vtmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vtmpy(Vuu32.h,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vtmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vunpack(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpack_Vb(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vunpack_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vunpack(Vu32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpack_Vh(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vunpack_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.h|=vunpacko(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vunpackoor_WhVb(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)(Vxx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vxx32.w|=vunpacko(Vu32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vunpackoor_WwVh(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)(Vxx,Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vunpack(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vunpack_Vub(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vunpack_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vunpack(Vu32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vunpack_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vunpack_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vd32=vxor(Vu32,Vv32) + C Intrinsic Prototype: HVX_Vector Q6_V_vxor_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vxor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uh=vzxt(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vzxt_Vub(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuh_vzxt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 60 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vzxt(Vu32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vzxt_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vzxt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 60 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vsplat(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vsplat_R(Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vb_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)(Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.h=vsplat(Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vsplat_R(Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)(Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Qd4=vsetq2(Rt32) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq2_R(Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vsetq2_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)(Rt)),-1) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Qd4.b=vshuffe(Qs4.h,Qt4.h) + C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Qb_vshuffe_QhQh(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Qd4.h=vshuffe(Qs4.w,Qt4.w) + C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Qh_vshuffe_QwQw(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vadd_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vadd_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qx4):carry + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)(Vu,Vv,Qx) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.h=vadd(vclb(Vu32.h),Vv32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vadd_vclb_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(vclb(Vu32.w),Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_vclb_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vadd(Vu32.h,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vaddacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vadd(Vu32.ub,Vv32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vaddacc_WhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vadd_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vadd(Vu32.uh,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vaddacc_WwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vadd_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vadd_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32=vand(!Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnR(HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vand_QnR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vx32|=vand(!Qu4,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vandor_VQnR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32=vand(!Qv4,Vu32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vand_QnV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32=vand(Qv4,Vu32) + C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vand_QV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VuwVuwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vlsr(Vu32.ub,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vlsr_VubR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vlsr_VubR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32_VbVbR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32or_VbVbVbI(Vx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)(Vx,Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,#u3) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vlut32_VbVbI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16_VbVhR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16or_WhVbVhI(Vxx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)(Vxx,Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wh_vlut16_VbVhI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)(Vu,Vv,Iu3) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vmax(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vmax_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vmin(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vmin_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.w=vmpa(Vuu32.uh,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpa_WuhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpa(Vuu32.uh,Rt32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpaacc_WwWuhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32=vmpye(Vu32.w,Vv32.uh) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_W_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRub(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyi_VwRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.ub) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vmpyiacc_VwVwRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vxx32+=vmpyo(Vu32.w,Vv32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_W_vmpyoacc_WVwVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vround(Vu32.uh,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vround_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vround(Vu32.uw,Vv32.uw):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vround_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vsat(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vsat_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vsub_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wb_vsub_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w,Qx4):carry + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsub_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)(Vu,Vv,Qx) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vsub_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vsub_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 62 +/* ========================================================================== + Assembly Syntax: Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat + C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) + Instruction Type: CVI_VA_DV + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wuw_vsub_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)(Vuu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 62 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vabs(Vu32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vabs_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)(Vu) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vabs(Vu32.b):sat + C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb_sat(HVX_Vector Vu) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vabs_Vb_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)(Vu) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vasl(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vaslacc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h+=vasr(Vu32.h,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_vasracc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VuhVuhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_VuhVuhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_VuwVuwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)(Vu,Vv,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vavg_VbVb_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vavg_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vavg_VuwVuw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vdd32=#0 + C Intrinsic Prototype: HVX_VectorPair Q6_W_vzero() + Instruction Type: MAPPING + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_W_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)() +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vv32.h).h + C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h + C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h + C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) + Instruction Type: CVI_GATHER_DV + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt,Mu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h + C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) + Instruction Type: CVI_GATHER_DV + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vtmp.w=vgather(Rt32,Mu2,Vv32.w).w + C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w + C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) + Instruction Type: CVI_GATHER + Execution Slots: SLOT01 + ========================================================================== */ + +#define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.h=vlut4(Vu32.uh,Rtt32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vlut4_VuhPh(Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)(Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpa_WubRub(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)(Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wh_vmpaacc_WhWubRub(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)(Vxx,Vuu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.h,Rtt32.h):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vmpa_VhVhVhPh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)(Vx,Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vmpa_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)(Vx,Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT2 + ========================================================================== */ + +#define Q6_Vh_vmps_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)(Vx,Vu,Rtt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_vmpyacc_WwVhRh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)(Vxx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vmpye(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vmpye_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)(Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vx32.uw+=vmpye(Vu32.uh,Rt32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuw_vmpyeacc_VuwVuhRuh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)(Vx,Vu,Rt) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=vnavg(Vu32.b,Vv32.b) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_vnavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.b=prefixsum(Qv4) + C Intrinsic Prototype: HVX_Vector Q6_Vb_prefixsum_Q(HVX_VectorPred Qv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vb_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.h=prefixsum(Qv4) + C Intrinsic Prototype: HVX_Vector Q6_Vh_prefixsum_Q(HVX_VectorPred Qv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: Vd32.w=prefixsum(Qv4) + C Intrinsic Prototype: HVX_Vector Q6_Vw_prefixsum_Q(HVX_VectorPred Qv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h+=Vw32 + C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatteracc_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_QRMVhV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER_DV + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)(Rt,Mu,Vvv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32 + C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER_DV + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatteracc_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)(Rt,Mu,Vvv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 + C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER_DV + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_QRMWwV(Qs,Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w=Vw32 + C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w+=Vw32 + C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatteracc_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)(Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 65 +/* ========================================================================== + Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32 + C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) + Instruction Type: CVI_SCATTER + Execution Slots: SLOT0 + ========================================================================== */ + +#define Q6_vscatter_QRMVwV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) +#endif /* __HEXAGON_ARCH___ >= 65 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat + C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vadd_VwVwQ_carry_sat(Vu,Vv,Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)(Vu,Vv,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1)) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vxx32.w=vasrinto(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Ww_vasrinto_WwVwVw(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vd32.uw=vrotr(Vu32.uw,Vv32.uw) + C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuw_vrotr_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 66 +/* ========================================================================== + Assembly Syntax: Vd32.w=vsatdw(Vu32.w,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vsatdw_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 66 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpy_WubWbI_h(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)(Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpyacc_WwWubWbI_h(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)(Vxx,Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpy_WubWbI_v(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)(Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v + C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Ww_v6mpyacc_WwWubWbI_v(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)(Vxx,Vuu,Vvv,Iu2) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vabs(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vabs_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vabs_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vabs(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vabs_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vabs_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vadd(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vadd(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vadd_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vadd_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vadd_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vadd_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vadd(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vadd(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vadd(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.w=vfmv(Vu32.w) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vfmv_Vw(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vw_vfmv_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign_fp)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=Vu32.qf16 + C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=Vuu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Wqf32(HVX_VectorPair Vuu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_equals_Wqf32(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf32)(Vuu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=Vu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_equals_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.b=vcvt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vb_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_b_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.h=vcvt(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vh_vcvt_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_h_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vb(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_b)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vcvt(Vu32.h) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vh(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vcvt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_h)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vcvt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vcvt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vub(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_ub)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vcvt(Vu32.uh) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vuh(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vcvt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_uh)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vcvt(Vu32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vcvt_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_sf_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vcvt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vub_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_ub_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vcvt(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcvt_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_uh_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vdmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vdmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpyacc_VsfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vdmpyacc_VsfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vfmax(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vfmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vfmax(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vfmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vfmin(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vfmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vfmin(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vfmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vfneg(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfneg_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vfneg_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vfneg(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfneg_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vfneg_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf)(Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vmax(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_vmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vmax(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_vmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vmin(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_vmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vmin(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VA + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_vmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vx32.hf+=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpyacc_VhfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vmpyacc_VhfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf_acc)(Vx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf32_vmpy_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wqf32_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wqf32_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wqf32_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf32_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVhfVhf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpyacc_WsfVhfVhf(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf_acc)(Vxx,Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vmpy(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.hf=vsub(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vhf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vhf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32_mix)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vsub(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_hf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 68 +/* ========================================================================== + Assembly Syntax: Vd32.sf=vsub(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vsf_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vsf_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_sf)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 68 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_WuhVub_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubrndsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat + C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vub_vasr_WuhVub_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_WwVuh_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhrndsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_sat(HVX_VectorPair Vuu, HVX_Vector Vv) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vuh_vasr_WwVuh_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhsat)(Vuu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 69 +/* ========================================================================== + Assembly Syntax: Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16 + C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmpy_VuhVuh_rs16(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vuh_vmpy_VuhVuh_rs16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhvs)(Vu,Vv) +#endif /* __HEXAGON_ARCH___ >= 69 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vadd(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vadd_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.h=Vu32.hf + C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_equals_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.hf=Vu32.h + C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vh(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vhf_equals_Vh(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_h)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.sf=Vu32.w + C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vw(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vsf_equals_Vw(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_w)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.w=Vu32.sf + C Intrinsic Prototype: HVX_Vector Q6_Vw_equals_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_equals_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_w_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.bf=vcvt(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vcvt_VsfVsf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vbf_vcvt_VsfVsf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_bf_sf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gt_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf)(Vu, Vv)), -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbfVbf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtand_QVbfVbf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_and)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbfVbf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtor_QVbfVbf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_or)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.gt(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbfVbf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_gtxacc_QVbfVbf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) \ + ((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtbf_xor)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.bf=vmax(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmax_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vbf_vmax_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vd32.bf=vmin(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_Vector Q6_Vbf_vmin_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_LATE Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vbf_vmin_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vmpy(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpy_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVbfVbf(HVX_VectorPair + Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution + Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vmpyacc_WsfVbfVbf(Vxx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_bf_acc)(Vxx, Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 73 +/* ========================================================================== + Assembly Syntax: Vdd32.sf=vsub(Vu32.bf,Vv32.bf) + C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VbfVbf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Wsf_vsub_VbfVbf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_bf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 73 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32=vgetqfext(Vu32.x,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfext_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vgetqfext_VR(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vx32|=vgetqfext(Vu32.x,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vgetqfextor_VVR(HVX_Vector Vx, + HVX_Vector Vu, Word32 Rt) Instruction Type: CVI_VX Execution Slots: + SLOT23 + ========================================================================== */ + +#define Q6_V_vgetqfextor_VVR(Vx, Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_get_qfext_oracc)(Vx, Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.x=vsetqfext(Vu32,Rt32) + C Intrinsic Prototype: HVX_Vector Q6_V_vsetqfext_VR(HVX_Vector Vu, Word32 Rt) + Instruction Type: CVI_VX + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vsetqfext_VR(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_set_qfext)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vabs(Vu32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vabs_V(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vabs_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vadd(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vadd_VV(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vadd_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.b=vcvt2(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt2_VhfVhf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vb_vcvt2_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_b_hf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt2(Vu32.b) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vb(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt2_Vb(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_b)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt2(Vu32.ub) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt2_Vub(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt2_Vub(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_hf_ub)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.ub=vcvt2(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt2_VhfVhf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vub_vcvt2_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt2_ub_hf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vcvt(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_Vector Q6_V_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector + Vv) Instruction Type: CVI_VX Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vcvt_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_f8_hf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vcvt(Vu32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_V(HVX_Vector Vu) + Instruction Type: CVI_VX_DV + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vcvt_V(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vfmax(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vfmax_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vfmax_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vfmin(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vfmin_VV(HVX_Vector Vu, HVX_Vector Vv) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vfmin_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.f8=vfneg(Vu32.f8) + C Intrinsic Prototype: HVX_Vector Q6_V_vfneg_V(HVX_Vector Vu) + Instruction Type: CVI_VX_LATE + Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_V_vfneg_V(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32=vmerge(Vu32.x,Vv32.w) + C Intrinsic Prototype: HVX_Vector Q6_V_vmerge_VVw(HVX_Vector Vu, HVX_Vector + Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_vmerge_VVw(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmerge_qf)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vmpy(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpy_VV(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vmpy_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vxx32.hf+=vmpy(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vmpyacc_WhfVV(HVX_VectorPair + Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution + Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vmpyacc_WhfVV(Vxx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_f8_acc)(Vxx, Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Rt32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfRhf(HVX_Vector Vu, Word32 + Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_VhfRhf(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_hf)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Rt32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Rhf(HVX_Vector Vu, + Word32 Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf16_vmpy_Vqf16Rhf(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_qf16)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Rt32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfRsf(HVX_Vector Vu, Word32 + Rt) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Vqf32_vmpy_VsfRsf(Vu, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_rt_sf)(Vu, Rt) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 79 +/* ========================================================================== + Assembly Syntax: Vdd32.hf=vsub(Vu32.f8,Vv32.f8) + C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vsub_VV(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VX_DV Execution Slots: SLOT23 + ========================================================================== */ + +#define Q6_Whf_vsub_VV(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_f8)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 79 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vabs(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vabs_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vabs(Vu32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vabs_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vabs(Vu32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vabs_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vabs(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vabs_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8) + C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector + Vv, Word32 Rt) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_valign4_VVR(Vu, Vv, Rt) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu, Vv, Rt) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.bf=Vuu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vbf_equals_Wqf32(HVX_VectorPair Vuu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vbf_equals_Wqf32(Vuu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.f8=Vu32.qf16 + C Intrinsic Prototype: HVX_Vector Q6_V_equals_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_V_equals_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.h=Vu32.hf:rnd + C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf_rnd(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vh_equals_Vhf_rnd(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vdd32.qf16=Vu32.f8 + C Intrinsic Prototype: HVX_VectorPair Q6_Wqf16_equals_V(HVX_Vector Vu) + Instruction Type: CVI_VP_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Wqf16_equals_V(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=Vu32.hf + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_equals_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=Vu32.qf16 + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_equals_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=Vu32.qf32 + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_equals_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=Vu32.sf + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_equals_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu, Vv)), -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu, Vv)), -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4|=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf) + C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred + Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution + Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \ + (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)( \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \ + Vv)), \ + -1) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.w=vilog2(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vw_vilog2_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vneg(Vu32.hf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vhf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vneg_Vhf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vneg(Vu32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vqf16(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vneg_Vqf16(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vneg(Vu32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vqf32(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vneg_Vqf32(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vneg(Vu32.sf) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vsf(HVX_Vector Vu) + Instruction Type: CVI_VS + Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vneg_Vsf(Vu) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16) + C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#if __HVX_ARCH__ >= 81 +/* ========================================================================== + Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32) + C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu, + HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123 + ========================================================================== */ + +#define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv) \ + __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu, Vv) +#endif /* __HEXAGON_ARCH___ >= 81 */ + +#endif /* __HVX__ */ + +#endif diff --git a/stdarch/crates/stdarch-gen-hexagon/src/main.rs b/stdarch/crates/stdarch-gen-hexagon/src/main.rs new file mode 100644 index 0000000000000..3cfbabfe0ab28 --- /dev/null +++ b/stdarch/crates/stdarch-gen-hexagon/src/main.rs @@ -0,0 +1,1717 @@ +//! Hexagon HVX Code Generator +//! +//! This generator creates v64.rs and v128.rs from scratch using the LLVM HVX +//! header file as the sole source of truth. It parses the C intrinsic prototypes +//! and generates Rust wrapper functions with appropriate attributes. +//! +//! The two generated files provide: +//! - v64.rs: 64-byte vector mode intrinsics (512-bit vectors) +//! - v128.rs: 128-byte vector mode intrinsics (1024-bit vectors) +//! +//! Both modules are available unconditionally, but require the appropriate +//! target features to actually use the intrinsics. +//! +//! Usage: +//! cd crates/stdarch-gen-hexagon +//! cargo run +//! # Output is written to ../core_arch/src/hexagon/v64.rs and v128.rs + +use regex::Regex; +use std::collections::{HashMap, HashSet}; +use std::fs::File; +use std::io::Write; +use std::path::Path; + +/// Mappings from HVX intrinsics to architecture-independent SIMD intrinsics. +/// These intrinsics have equivalent semantics and can be lowered to the generic form. +fn get_simd_intrinsic_mappings() -> HashMap<&'static str, &'static str> { + let mut map = HashMap::new(); + // Bitwise operations (element-size independent) + map.insert("vxor", "simd_xor"); + map.insert("vand", "simd_and"); + map.insert("vor", "simd_or"); + // Word (32-bit) arithmetic operations + map.insert("vaddw", "simd_add"); + map.insert("vsubw", "simd_sub"); + map +} + +/// The tracking issue number for the stdarch_hexagon feature +const TRACKING_ISSUE: &str = "151523"; + +/// HVX vector length mode +#[derive(Debug, Clone, Copy, PartialEq)] +enum VectorMode { + /// 64-byte vectors (512 bits) + V64, + /// 128-byte vectors (1024 bits) + V128, +} + +impl VectorMode { + fn bytes(&self) -> u32 { + match self { + VectorMode::V64 => 64, + VectorMode::V128 => 128, + } + } + + fn bits(&self) -> u32 { + self.bytes() * 8 + } + + fn lanes(&self) -> u32 { + self.bytes() / 4 // 32-bit lanes + } + + fn target_feature(&self) -> &'static str { + match self { + VectorMode::V64 => "hvx-length64b", + VectorMode::V128 => "hvx-length128b", + } + } +} + +/// LLVM version the header file is from (for reference) +/// Source: https://github.com/llvm/llvm-project/blob/llvmorg-22.1.0-rc1/clang/lib/Headers/hvx_hexagon_protos.h +const LLVM_VERSION: &str = "22.1.0-rc1"; + +/// Maximum HVX architecture version supported by rustc +/// Check with: rustc --target=hexagon-unknown-linux-musl --print target-features +const MAX_SUPPORTED_ARCH: u32 = 79; + +/// Local header file path (checked into the repository) +const HEADER_FILE: &str = "hvx_hexagon_protos.h"; + +/// Intrinsic information parsed from the LLVM header +#[derive(Debug, Clone)] +struct IntrinsicInfo { + /// The Q6_* intrinsic name (e.g., "Q6_V_vadd_VV") + q6_name: String, + /// The LLVM builtin name without prefix (e.g., "V6_vaddb") + builtin_name: String, + /// The short instruction name for assert_instr (e.g., "vaddb") + instr_name: String, + /// The assembly syntax from the comment + asm_syntax: String, + /// Instruction type + instr_type: String, + /// Execution slots + exec_slots: String, + /// Minimum HVX architecture version required + min_arch: u32, + /// Return type + return_type: RustType, + /// Parameters (name, type) + params: Vec<(String, RustType)>, + /// Whether this is a compound intrinsic (multiple builtins) + is_compound: bool, + /// For compound intrinsics: the parsed expression tree + compound_expr: Option, +} + +/// Expression tree for compound intrinsics +#[derive(Debug, Clone)] +enum CompoundExpr { + /// A call to a builtin: (builtin_name without V6_ prefix, arguments) + BuiltinCall(String, Vec), + /// A parameter reference by name + Param(String), + /// An integer literal (like -1) + IntLiteral(i32), +} + +/// Rust type mappings +#[derive(Debug, Clone, PartialEq)] +enum RustType { + HvxVector, + HvxVectorPair, + HvxVectorPred, + I32, + MutPtrHvxVector, + Unit, +} + +impl RustType { + fn from_c_type(c_type: &str) -> Option { + match c_type.trim() { + "HVX_Vector" => Some(RustType::HvxVector), + "HVX_VectorPair" => Some(RustType::HvxVectorPair), + "HVX_VectorPred" => Some(RustType::HvxVectorPred), + "Word32" => Some(RustType::I32), + "HVX_Vector*" => Some(RustType::MutPtrHvxVector), + "void" => Some(RustType::Unit), + _ => None, + } + } + + fn to_rust_str(&self) -> &'static str { + match self { + RustType::HvxVector => "HvxVector", + RustType::HvxVectorPair => "HvxVectorPair", + RustType::HvxVectorPred => "HvxVectorPred", + RustType::I32 => "i32", + RustType::MutPtrHvxVector => "*mut HvxVector", + RustType::Unit => "()", + } + } + + fn to_extern_str(&self) -> &'static str { + match self { + RustType::HvxVector => "HvxVector", + RustType::HvxVectorPair => "HvxVectorPair", + RustType::HvxVectorPred => "HvxVectorPred", + RustType::I32 => "i32", + RustType::MutPtrHvxVector => "*mut HvxVector", + RustType::Unit => "()", + } + } +} + +/// Parse a compound macro expression into an expression tree +fn parse_compound_expr(expr: &str) -> Option { + let expr = expr.trim(); + + // Try to match an integer literal (like -1) + if let Ok(n) = expr.parse::() { + return Some(CompoundExpr::IntLiteral(n)); + } + + // Try to match a simple parameter name (Vu, Vv, Rt, Qs, Qt, Qx, Vx, etc.) + // These are typically short identifiers in the macro + if expr.len() <= 3 + && expr.chars().all(|c| c.is_ascii_alphanumeric() || c == '_') + && !expr.contains("__") + { + return Some(CompoundExpr::Param(expr.to_lowercase())); + } + + // Check if it's wrapped in extra parens first + if expr.starts_with('(') && expr.ends_with(')') { + // Check if these parens wrap the entire expression + let inner = &expr[1..expr.len() - 1]; + // Count depth: if after removing outer parens the expression is balanced, + // the outer parens were enclosing everything + if is_balanced_parens(inner) { + // But we also need to verify these aren't part of a function call + // If the inner expression is balanced and the whole thing starts with ( + // and ends with ), it's a paren wrapper + let result = parse_compound_expr(inner); + if result.is_some() { + return result; + } + } + } + + // Try to match __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_xxx)(args) + // The args portion may contain nested calls, so we need to find the matching paren + if expr.starts_with("__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_") { + // Find the end of the builtin name (after V6_) + let prefix = "__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_"; + let after_prefix = &expr[prefix.len()..]; + if let Some(paren_pos) = after_prefix.find(')') { + let builtin_name = &after_prefix[..paren_pos]; + let rest = &after_prefix[paren_pos + 1..]; // Skip the closing ) of the WRAP + // rest should now be "(args)" + if rest.starts_with('(') && rest.ends_with(')') { + let args_str = &rest[1..rest.len() - 1]; + let args = parse_compound_args(args_str)?; + return Some(CompoundExpr::BuiltinCall(builtin_name.to_string(), args)); + } + } + } + + // Try to match __builtin_HEXAGON_V6_xxx(args) without wrap + if expr.starts_with("__builtin_HEXAGON_V6_") { + let prefix = "__builtin_HEXAGON_V6_"; + let after_prefix = &expr[prefix.len()..]; + if let Some(paren_pos) = after_prefix.find('(') { + let builtin_name = &after_prefix[..paren_pos]; + let rest = &after_prefix[paren_pos..]; + if rest.starts_with('(') && rest.ends_with(')') { + let args_str = &rest[1..rest.len() - 1]; + let args = parse_compound_args(args_str)?; + return Some(CompoundExpr::BuiltinCall(builtin_name.to_string(), args)); + } + } + } + + None +} + +/// Check if parentheses are balanced in a string +fn is_balanced_parens(s: &str) -> bool { + let mut depth = 0; + for c in s.chars() { + match c { + '(' => depth += 1, + ')' => { + depth -= 1; + if depth < 0 { + return false; + } + } + _ => {} + } + } + depth == 0 +} + +/// Parse comma-separated arguments, respecting nested parentheses +fn parse_compound_args(args_str: &str) -> Option> { + let mut args = Vec::new(); + let mut current = String::new(); + let mut depth = 0; + + for c in args_str.chars() { + match c { + '(' => { + depth += 1; + current.push(c); + } + ')' => { + depth -= 1; + current.push(c); + } + ',' if depth == 0 => { + let arg = current.trim().to_string(); + if !arg.is_empty() { + args.push(parse_compound_expr(&arg)?); + } + current.clear(); + } + _ => current.push(c), + } + } + + // Don't forget the last argument + let arg = current.trim().to_string(); + if !arg.is_empty() { + args.push(parse_compound_expr(&arg)?); + } + + Some(args) +} + +/// Extract all builtin names used in a compound expression +fn collect_builtins_from_expr(expr: &CompoundExpr, builtins: &mut HashSet) { + match expr { + CompoundExpr::BuiltinCall(name, args) => { + builtins.insert(name.clone()); + for arg in args { + collect_builtins_from_expr(arg, builtins); + } + } + CompoundExpr::Param(_) | CompoundExpr::IntLiteral(_) => {} + } +} + +/// Read the local HVX header file +fn read_header(crate_dir: &Path) -> Result { + let header_path = crate_dir.join(HEADER_FILE); + println!("Reading HVX header from: {}", header_path.display()); + println!(" (LLVM version: {})", LLVM_VERSION); + + std::fs::read_to_string(&header_path).map_err(|e| { + format!( + "Failed to read header file {}: {}", + header_path.display(), + e + ) + }) +} + +/// Parse a C function prototype to extract return type and parameters +fn parse_prototype(prototype: &str) -> Option<(RustType, Vec<(String, RustType)>)> { + // Pattern: ReturnType FunctionName(ParamType1 Param1, ParamType2 Param2, ...) + let proto_re = Regex::new(r"(\w+(?:\*)?)\s+Q6_\w+\(([^)]*)\)").unwrap(); + + if let Some(caps) = proto_re.captures(prototype) { + let return_type_str = caps[1].trim(); + let params_str = &caps[2]; + + let return_type = RustType::from_c_type(return_type_str)?; + + let mut params = Vec::new(); + if !params_str.trim().is_empty() { + // Pattern: Type Name or Type* Name + let param_re = Regex::new(r"(\w+\*?)\s+(\w+)").unwrap(); + for param in params_str.split(',') { + let param = param.trim(); + if let Some(pcaps) = param_re.captures(param) { + let ptype_str = pcaps[1].trim(); + let pname = pcaps[2].to_lowercase(); + if let Some(ptype) = RustType::from_c_type(ptype_str) { + params.push((pname, ptype)); + } else { + return None; // Unknown type + } + } + } + } + + Some((return_type, params)) + } else { + None + } +} + +/// Parse the LLVM header file to extract intrinsic information +fn parse_header(content: &str) -> Vec { + let mut intrinsics = Vec::new(); + + let arch_re = Regex::new(r"#if __HVX_ARCH__ >= (\d+)").unwrap(); + + // Regex to extract the simple builtin name from a macro body + // Match: __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_xxx)(args) + let simple_builtin_re = + Regex::new(r"__BUILTIN_VECTOR_WRAP\(__builtin_HEXAGON_(\w+)\)\([^)]*\)\s*$").unwrap(); + + // Also handle builtins without VECTOR_WRAP + let simple_builtin_re2 = Regex::new(r"__builtin_HEXAGON_(\w+)\([^)]*\)\s*$").unwrap(); + + // Regex to extract Q6 name from #define + let q6_name_re = Regex::new(r"#define\s+(Q6_\w+)").unwrap(); + + // Regex to extract macro expression body + let macro_expr_re = Regex::new(r"#define\s+Q6_\w+\([^)]*\)\s+(.+)").unwrap(); + + let lines: Vec<&str> = content.lines().collect(); + let mut current_arch: u32 = 60; + let mut i = 0; + + while i < lines.len() { + // Track architecture version + if let Some(caps) = arch_re.captures(lines[i]) { + if let Ok(arch) = caps[1].parse() { + current_arch = arch; + } + } + + // Look for Assembly Syntax comment block + if lines[i].contains("Assembly Syntax:") { + let mut asm_syntax = String::new(); + let mut prototype = String::new(); + let mut instr_type = String::new(); + let mut exec_slots = String::new(); + + // Parse the comment block + let mut j = i; + while j < lines.len() && !lines[j].starts_with("#define") { + let line = lines[j]; + if line.contains("Assembly Syntax:") { + if let Some(pos) = line.find("Assembly Syntax:") { + asm_syntax = line[pos + 16..].trim().to_string(); + } + } else if line.contains("C Intrinsic Prototype:") { + if let Some(pos) = line.find("C Intrinsic Prototype:") { + prototype = line[pos + 22..].trim().to_string(); + } + } else if line.contains("Instruction Type:") { + if let Some(pos) = line.find("Instruction Type:") { + instr_type = line[pos + 17..].trim().to_string(); + } + } else if line.contains("Execution Slots:") { + if let Some(pos) = line.find("Execution Slots:") { + exec_slots = line[pos + 16..].trim().to_string(); + } + } + j += 1; + } + + // Now find the #define line + while j < lines.len() && !lines[j].starts_with("#define") { + j += 1; + } + + if j < lines.len() { + let define_line = lines[j]; + + // Extract Q6 name and check if it's simple or compound + if let Some(caps) = q6_name_re.captures(define_line) { + let q6_name = caps[1].to_string(); + + // Get the full macro body (handle line continuations) + let mut macro_body = define_line.to_string(); + let mut k = j; + while macro_body.trim_end().ends_with('\\') && k + 1 < lines.len() { + k += 1; + macro_body.push_str(lines[k]); + } + + // Try to extract simple builtin name + let builtin_name = simple_builtin_re + .captures(¯o_body) + .or_else(|| simple_builtin_re2.captures(¯o_body)) + .map(|bcaps| bcaps[1].to_string()); + + // Check if it's a compound intrinsic (multiple __builtin calls) + let builtin_count = macro_body.matches("__builtin_HEXAGON_").count(); + let is_compound = builtin_count > 1; + + // Parse prototype + if let Some((return_type, params)) = parse_prototype(&prototype) { + if is_compound { + // For compound intrinsics, parse the expression + // Extract the macro body after the parameter list + if let Some(expr_caps) = macro_expr_re.captures(¯o_body) { + let expr_str = expr_caps[1].trim().replace(['\n', '\\'], " "); + let expr_str = expr_str.trim(); + + if let Some(compound_expr) = parse_compound_expr(expr_str) { + // For compound intrinsics, we use the outermost builtin + // as the "primary" for the instruction name + let (primary_builtin, instr_name) = match &compound_expr { + CompoundExpr::BuiltinCall(name, _) => { + (name.clone(), name.clone()) + } + _ => continue, + }; + + intrinsics.push(IntrinsicInfo { + q6_name, + builtin_name: format!("V6_{}", primary_builtin), + instr_name, + asm_syntax, + instr_type, + exec_slots, + min_arch: current_arch, + return_type, + params, + is_compound: true, + compound_expr: Some(compound_expr), + }); + } + } + } else if let Some(builtin) = builtin_name { + // Extract short instruction name + let instr_name = builtin + .strip_prefix("V6_") + .map(|s| s.to_string()) + .unwrap_or_else(|| builtin.clone()); + + intrinsics.push(IntrinsicInfo { + q6_name, + builtin_name: builtin, + instr_name, + asm_syntax, + instr_type, + exec_slots, + min_arch: current_arch, + return_type, + params, + is_compound: false, + compound_expr: None, + }); + } + } + } + } + i = j; + } + i += 1; + } + + intrinsics +} + +/// Convert Q6 name to Rust function name (lowercase with underscores) +fn q6_to_rust_name(q6_name: &str) -> String { + // Q6_V_hi_W -> q6_v_hi_w + q6_name.to_lowercase() +} + +/// Generate the module documentation +fn generate_module_doc(mode: VectorMode) -> String { + format!( + r#"//! Hexagon HVX {bytes}-byte vector mode intrinsics +//! +//! This module provides intrinsics for the Hexagon Vector Extensions (HVX) +//! in {bytes}-byte vector mode ({bits}-bit vectors). +//! +//! HVX is a wide vector extension designed for high-performance signal processing. +//! [Hexagon HVX Programmer's Reference Manual](https://docs.qualcomm.com/doc/80-N2040-61) +//! +//! ## Vector Types +//! +//! In {bytes}-byte mode: +//! - `HvxVector` is {bits} bits ({bytes} bytes) containing {lanes} x 32-bit values +//! - `HvxVectorPair` is {pair_bits} bits ({pair_bytes} bytes) +//! - `HvxVectorPred` is {bits} bits ({bytes} bytes) for predicate operations +//! +//! To use this module, compile with `-C target-feature=+{target_feature}`. +//! +//! ## Architecture Versions +//! +//! Different intrinsics require different HVX architecture versions. Use the +//! appropriate target feature to enable the required version: +//! - HVX v60: `-C target-feature=+hvxv60` (basic HVX operations) +//! - HVX v62: `-C target-feature=+hvxv62` +//! - HVX v65: `-C target-feature=+hvxv65` (includes floating-point support) +//! - HVX v66: `-C target-feature=+hvxv66` +//! - HVX v68: `-C target-feature=+hvxv68` +//! - HVX v69: `-C target-feature=+hvxv69` +//! - HVX v73: `-C target-feature=+hvxv73` +//! - HVX v79: `-C target-feature=+hvxv79` +//! +//! Each version includes all features from previous versions. +"#, + bytes = mode.bytes(), + bits = mode.bits(), + lanes = mode.lanes(), + pair_bytes = mode.bytes() * 2, + pair_bits = mode.bits() * 2, + target_feature = mode.target_feature(), + ) +} + +/// Generate the type definitions for a specific vector mode +fn generate_types(mode: VectorMode) -> String { + let lanes = mode.lanes(); + let pair_lanes = lanes * 2; + let bits = mode.bits(); + let bytes = mode.bytes(); + let pair_bits = bits * 2; + let pair_bytes = bytes * 2; + + format!( + r#" +#![allow(non_camel_case_types)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use crate::intrinsics::simd::{{simd_add, simd_and, simd_or, simd_sub, simd_xor}}; + +// HVX type definitions for {bytes}-byte vector mode +types! {{ + #![unstable(feature = "stdarch_hexagon", issue = "{TRACKING_ISSUE}")] + + /// HVX vector type ({bits} bits / {bytes} bytes) + /// + /// This type represents a single HVX vector register containing {lanes} x 32-bit values. + pub struct HvxVector({lanes} x i32); + + /// HVX vector pair type ({pair_bits} bits / {pair_bytes} bytes) + /// + /// This type represents a pair of HVX vector registers, often used for + /// operations that produce double-width results. + pub struct HvxVectorPair({pair_lanes} x i32); + + /// HVX vector predicate type ({bits} bits / {bytes} bytes) + /// + /// This type represents a predicate vector used for conditional operations. + /// Each bit corresponds to a lane in the vector. + pub struct HvxVectorPred({lanes} x i32); +}} +"#, + bytes = bytes, + bits = bits, + lanes = lanes, + pair_bits = pair_bits, + pair_bytes = pair_bytes, + pair_lanes = pair_lanes, + TRACKING_ISSUE = TRACKING_ISSUE, + ) +} + +/// Builtin signature information for extern declarations +struct BuiltinSignature { + /// The V6_ prefixed name + full_name: String, + /// The short name (without V6_) + short_name: String, + /// Return type + return_type: RustType, + /// Parameter types + param_types: Vec, +} + +/// Get known signatures for builtins used in compound operations +/// These are the helper builtins that don't have their own Q6_ wrapper +fn get_compound_helper_signatures() -> HashMap { + let mut map = HashMap::new(); + + // vandvrt: HVX_Vector -> i32 -> HVX_Vector + // Converts predicate to vector representation. LLVM uses HVX_Vector for both. + map.insert( + "vandvrt".to_string(), + BuiltinSignature { + full_name: "V6_vandvrt".to_string(), + short_name: "vandvrt".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::I32], + }, + ); + + // vandqrt: HVX_Vector -> i32 -> HVX_Vector + // Converts vector representation back to predicate. LLVM uses HVX_Vector for both. + map.insert( + "vandqrt".to_string(), + BuiltinSignature { + full_name: "V6_vandqrt".to_string(), + short_name: "vandqrt".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::I32], + }, + ); + + // vandvrt_acc: HVX_Vector -> HVX_Vector -> i32 -> HVX_Vector + map.insert( + "vandvrt_acc".to_string(), + BuiltinSignature { + full_name: "V6_vandvrt_acc".to_string(), + short_name: "vandvrt_acc".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32], + }, + ); + + // vandqrt_acc: HVX_Vector -> HVX_Vector -> i32 -> HVX_Vector + map.insert( + "vandqrt_acc".to_string(), + BuiltinSignature { + full_name: "V6_vandqrt_acc".to_string(), + short_name: "vandqrt_acc".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32], + }, + ); + + // pred_and: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_and".to_string(), + BuiltinSignature { + full_name: "V6_pred_and".to_string(), + short_name: "pred_and".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_and_n: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_and_n".to_string(), + BuiltinSignature { + full_name: "V6_pred_and_n".to_string(), + short_name: "pred_and_n".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_or: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_or".to_string(), + BuiltinSignature { + full_name: "V6_pred_or".to_string(), + short_name: "pred_or".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_or_n: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_or_n".to_string(), + BuiltinSignature { + full_name: "V6_pred_or_n".to_string(), + short_name: "pred_or_n".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_xor: HVX_Vector -> HVX_Vector -> HVX_Vector + map.insert( + "pred_xor".to_string(), + BuiltinSignature { + full_name: "V6_pred_xor".to_string(), + short_name: "pred_xor".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // pred_not: HVX_Vector -> HVX_Vector + map.insert( + "pred_not".to_string(), + BuiltinSignature { + full_name: "V6_pred_not".to_string(), + short_name: "pred_not".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector], + }, + ); + + // pred_scalar2: i32 -> HVX_Vector + map.insert( + "pred_scalar2".to_string(), + BuiltinSignature { + full_name: "V6_pred_scalar2".to_string(), + short_name: "pred_scalar2".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::I32], + }, + ); + + // Conditional store operations + map.insert( + "vS32b_qpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_qpred_ai".to_string(), + short_name: "vS32b_qpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vS32b_nqpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_nqpred_ai".to_string(), + short_name: "vS32b_nqpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vS32b_nt_qpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_nt_qpred_ai".to_string(), + short_name: "vS32b_nt_qpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vS32b_nt_nqpred_ai".to_string(), + BuiltinSignature { + full_name: "V6_vS32b_nt_nqpred_ai".to_string(), + short_name: "vS32b_nt_nqpred_ai".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::MutPtrHvxVector, + RustType::HvxVector, + ], + }, + ); + + // Conditional accumulation operations + for (suffix, _elem) in [("b", "byte"), ("h", "halfword"), ("w", "word")] { + // vaddbq, vaddhq, vaddwq + map.insert( + format!("vadd{}q", suffix), + BuiltinSignature { + full_name: format!("V6_vadd{}q", suffix), + short_name: format!("vadd{}q", suffix), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + // vaddbnq, vaddhnq, vaddwnq + map.insert( + format!("vadd{}nq", suffix), + BuiltinSignature { + full_name: format!("V6_vadd{}nq", suffix), + short_name: format!("vadd{}nq", suffix), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + + // Comparison operations with accumulation + // veqb_and, veqb_or, veqb_xor, etc. + for elem in ["b", "h", "w", "ub", "uh", "uw"] { + for op in ["and", "or", "xor"] { + // veq*_and, veq*_or, veq*_xor + map.insert( + format!("veq{}_{}", elem, op), + BuiltinSignature { + full_name: format!("V6_veq{}_{}", elem, op), + short_name: format!("veq{}_{}", elem, op), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + // vgt*_and, vgt*_or, vgt*_xor + map.insert( + format!("vgt{}_{}", elem, op), + BuiltinSignature { + full_name: format!("V6_vgt{}_{}", elem, op), + short_name: format!("vgt{}_{}", elem, op), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + } + + // Floating-point comparison operations (hf = half-float, sf = single-float) + for elem in ["hf", "sf"] { + // Basic comparison: vgt* + map.insert( + format!("vgt{}", elem), + BuiltinSignature { + full_name: format!("V6_vgt{}", elem), + short_name: format!("vgt{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + for op in ["and", "or", "xor"] { + // vgt*_and, vgt*_or, vgt*_xor + map.insert( + format!("vgt{}_{}", elem, op), + BuiltinSignature { + full_name: format!("V6_vgt{}_{}", elem, op), + short_name: format!("vgt{}_{}", elem, op), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + } + + // Prefix operations with predicate + for elem in ["b", "h", "w"] { + map.insert( + format!("vprefixq{}", elem), + BuiltinSignature { + full_name: format!("V6_vprefixq{}", elem), + short_name: format!("vprefixq{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector], + }, + ); + } + + // Scatter operations with predicate + map.insert( + "vscattermhq".to_string(), + BuiltinSignature { + full_name: "V6_vscattermhq".to_string(), + short_name: "vscattermhq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vscattermhwq".to_string(), + BuiltinSignature { + full_name: "V6_vscattermhwq".to_string(), + short_name: "vscattermhwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVectorPair, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vscattermwq".to_string(), + BuiltinSignature { + full_name: "V6_vscattermwq".to_string(), + short_name: "vscattermwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // Add with carry saturation + map.insert( + "vaddcarrysat".to_string(), + BuiltinSignature { + full_name: "V6_vaddcarrysat".to_string(), + short_name: "vaddcarrysat".to_string(), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // Gather operations with predicate + map.insert( + "vgathermhq".to_string(), + BuiltinSignature { + full_name: "V6_vgathermhq".to_string(), + short_name: "vgathermhq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::MutPtrHvxVector, + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + ], + }, + ); + + map.insert( + "vgathermhwq".to_string(), + BuiltinSignature { + full_name: "V6_vgathermhwq".to_string(), + short_name: "vgathermhwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::MutPtrHvxVector, + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVectorPair, + ], + }, + ); + + map.insert( + "vgathermwq".to_string(), + BuiltinSignature { + full_name: "V6_vgathermwq".to_string(), + short_name: "vgathermwq".to_string(), + return_type: RustType::Unit, + param_types: vec![ + RustType::MutPtrHvxVector, + RustType::HvxVector, + RustType::I32, + RustType::I32, + RustType::HvxVector, + ], + }, + ); + + // Basic comparison operations (without accumulation) + for elem in ["b", "h", "w", "ub", "uh", "uw"] { + // vgt* - greater than + map.insert( + format!("vgt{}", elem), + BuiltinSignature { + full_name: format!("V6_vgt{}", elem), + short_name: format!("vgt{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + // veq* - equal + map.insert( + format!("veq{}", elem), + BuiltinSignature { + full_name: format!("V6_veq{}", elem), + short_name: format!("veq{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + } + + // Conditional subtraction operations (vsub*q, vsub*nq) + for elem in ["b", "h", "w"] { + map.insert( + format!("vsub{}q", elem), + BuiltinSignature { + full_name: format!("V6_vsub{}q", elem), + short_name: format!("vsub{}q", elem), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + map.insert( + format!("vsub{}nq", elem), + BuiltinSignature { + full_name: format!("V6_vsub{}nq", elem), + short_name: format!("vsub{}nq", elem), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + } + + // vmux - vector mux (select based on predicate) + map.insert( + "vmux".to_string(), + BuiltinSignature { + full_name: "V6_vmux".to_string(), + short_name: "vmux".to_string(), + return_type: RustType::HvxVector, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // vswap - vector swap based on predicate + map.insert( + "vswap".to_string(), + BuiltinSignature { + full_name: "V6_vswap".to_string(), + short_name: "vswap".to_string(), + return_type: RustType::HvxVectorPair, + param_types: vec![ + RustType::HvxVector, + RustType::HvxVector, + RustType::HvxVector, + ], + }, + ); + + // shuffeq operations - take vectors (internal pred representation) and return vector + for elem in ["h", "w"] { + map.insert( + format!("shuffeq{}", elem), + BuiltinSignature { + full_name: format!("V6_shuffeq{}", elem), + short_name: format!("shuffeq{}", elem), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + } + + // Predicate AND with vector operations + map.insert( + "vandvqv".to_string(), + BuiltinSignature { + full_name: "V6_vandvqv".to_string(), + short_name: "vandvqv".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + map.insert( + "vandvnqv".to_string(), + BuiltinSignature { + full_name: "V6_vandvnqv".to_string(), + short_name: "vandvnqv".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector], + }, + ); + + // vandnqrt and vandnqrt_acc + map.insert( + "vandnqrt".to_string(), + BuiltinSignature { + full_name: "V6_vandnqrt".to_string(), + short_name: "vandnqrt".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::I32], + }, + ); + + map.insert( + "vandnqrt_acc".to_string(), + BuiltinSignature { + full_name: "V6_vandnqrt_acc".to_string(), + short_name: "vandnqrt_acc".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::HvxVector, RustType::HvxVector, RustType::I32], + }, + ); + + // pred_scalar2v2 + map.insert( + "pred_scalar2v2".to_string(), + BuiltinSignature { + full_name: "V6_pred_scalar2v2".to_string(), + short_name: "pred_scalar2v2".to_string(), + return_type: RustType::HvxVector, + param_types: vec![RustType::I32], + }, + ); + + map +} + +/// Generate extern declarations for all intrinsics for a specific vector mode +fn generate_extern_block(intrinsics: &[IntrinsicInfo], mode: VectorMode) -> String { + let mut output = String::new(); + + // Collect unique builtins to avoid duplicates + let mut seen_builtins: HashSet = HashSet::new(); + let mut decls: Vec<(String, String, RustType, Vec)> = Vec::new(); + + // First, add simple intrinsics + for info in intrinsics.iter().filter(|i| !i.is_compound) { + if seen_builtins.contains(&info.builtin_name) { + continue; + } + seen_builtins.insert(info.builtin_name.clone()); + + let param_types: Vec = info.params.iter().map(|(_, t)| t.clone()).collect(); + decls.push(( + info.builtin_name.clone(), + info.instr_name.clone(), + info.return_type.clone(), + param_types, + )); + } + + // Then, collect all builtins used in compound expressions + let helper_sigs = get_compound_helper_signatures(); + let mut compound_builtins: HashSet = HashSet::new(); + + for info in intrinsics.iter().filter(|i| i.is_compound) { + if let Some(ref expr) = info.compound_expr { + collect_builtins_from_expr(expr, &mut compound_builtins); + } + } + + // Add compound helper builtins + let mut missing_builtins = Vec::new(); + for builtin_name in compound_builtins { + let full_name = format!("V6_{}", builtin_name); + if seen_builtins.contains(&full_name) { + continue; + } + seen_builtins.insert(full_name.clone()); + + if let Some(sig) = helper_sigs.get(&builtin_name) { + decls.push(( + sig.full_name.clone(), + sig.short_name.clone(), + sig.return_type.clone(), + sig.param_types.clone(), + )); + } else { + missing_builtins.push(builtin_name); + } + } + + // Report missing builtins (for development purposes) + if !missing_builtins.is_empty() { + eprintln!("Warning: Missing helper signatures for compound builtins:"); + for name in &missing_builtins { + eprintln!(" - {}", name); + } + } + + // Sort by builtin name for consistent output + decls.sort_by(|a, b| a.0.cmp(&b.0)); + + // Generate intrinsic declarations for the specified mode + output.push_str(&format!( + "// LLVM intrinsic declarations for {}-byte vector mode\n", + mode.bytes() + )); + output.push_str("#[allow(improper_ctypes)]\n"); + output.push_str("unsafe extern \"unadjusted\" {\n"); + + for (builtin_name, instr_name, return_type, param_types) in &decls { + let base_link = builtin_name.replace('_', "."); + // 128-byte mode uses .128B suffix, 64-byte mode doesn't + let link_name = if builtin_name.starts_with("V6_") && mode == VectorMode::V128 { + format!("llvm.hexagon.{}.128B", base_link) + } else { + format!("llvm.hexagon.{}", base_link) + }; + + let params_str = if param_types.is_empty() { + String::new() + } else { + param_types + .iter() + .map(|t| format!("_: {}", t.to_extern_str())) + .collect::>() + .join(", ") + }; + + let return_str = if *return_type == RustType::Unit { + " -> ()".to_string() + } else { + format!(" -> {}", return_type.to_extern_str()) + }; + + output.push_str(&format!( + " #[link_name = \"{}\"]\n fn {}({}){};\n", + link_name, instr_name, params_str, return_str + )); + } + + output.push_str("}\n"); + output +} + +/// Generate Rust code for a compound expression +/// `params` maps parameter names to their types in the function signature +/// Get the type of an expression +fn get_expr_type( + expr: &CompoundExpr, + params: &HashMap, + helper_sigs: &HashMap, +) -> Option { + match expr { + CompoundExpr::BuiltinCall(name, _) => { + helper_sigs.get(name).map(|sig| sig.return_type.clone()) + } + CompoundExpr::Param(name) => params.get(name).cloned(), + CompoundExpr::IntLiteral(_) => Some(RustType::I32), + } +} + +fn generate_compound_expr_code( + expr: &CompoundExpr, + params: &HashMap, + helper_sigs: &HashMap, +) -> String { + match expr { + CompoundExpr::BuiltinCall(name, args) => { + // Get the expected parameter types for this builtin + let expected_types = helper_sigs + .get(name) + .map(|sig| sig.param_types.clone()) + .unwrap_or_default(); + + let args_code: Vec = args + .iter() + .enumerate() + .map(|(i, arg)| { + let arg_code = generate_compound_expr_code(arg, params, helper_sigs); + + // Check if we need to transmute this argument + let expected_type = expected_types.get(i); + let actual_type = get_expr_type(arg, params, helper_sigs); + + // If the builtin expects HvxVector but the arg is HvxVectorPred, transmute + if expected_type == Some(&RustType::HvxVector) + && actual_type == Some(RustType::HvxVectorPred) + { + format!( + "core::mem::transmute::({})", + arg_code + ) + } else { + arg_code + } + }) + .collect(); + format!("{}({})", name, args_code.join(", ")) + } + CompoundExpr::Param(name) => name.clone(), + CompoundExpr::IntLiteral(n) => n.to_string(), + } +} + +/// Get the primary instruction name from a compound expression (innermost significant op) +fn get_compound_primary_instr(expr: &CompoundExpr) -> Option { + match expr { + CompoundExpr::BuiltinCall(name, args) => { + // For vandqrt wrapper, look inside + if name == "vandqrt" && !args.is_empty() { + if let Some(inner) = get_compound_primary_instr(&args[0]) { + return Some(inner); + } + } + // For store operations, use the store name + if name.starts_with("vS32b") { + return Some(name.clone()); + } + // For conditional accumulation, use the add name + if name.starts_with("vadd") && (name.ends_with("q") || name.ends_with("nq")) { + return Some(name.clone()); + } + // For predicate operations + if name.starts_with("pred_") { + return Some(name.clone()); + } + // For comparison operations with accumulation + if (name.starts_with("veq") || name.starts_with("vgt")) + && (name.ends_with("_and") || name.ends_with("_or") || name.ends_with("_xor")) + { + return Some(name.clone()); + } + Some(name.clone()) + } + _ => None, + } +} + +/// Get override implementations for specific compound intrinsics. +/// Some C macros rely on implicit type conversions that don't work with +/// our stricter Rust types, so we provide corrected implementations. +fn get_compound_overrides() -> HashMap<&'static str, &'static str> { + let mut map = HashMap::new(); + + // Q6_V_vand_QR: takes pred, returns vec + // Use transmute to convert pred to vec for LLVM, call vandvrt + map.insert( + "Q6_V_vand_QR", + "vandvrt(core::mem::transmute::(qu), rt)", + ); + + // Q6_V_vandor_VQR: takes vec and pred, returns vec + map.insert( + "Q6_V_vandor_VQR", + "vandvrt_acc(vx, core::mem::transmute::(qu), rt)", + ); + + // Q6_Q_vand_VR: takes vec, returns pred + map.insert( + "Q6_Q_vand_VR", + "core::mem::transmute::(vandqrt(vu, rt))", + ); + + // Q6_Q_vandor_QVR: takes pred and vec, returns pred + map.insert( + "Q6_Q_vandor_QVR", + "core::mem::transmute::(vandqrt_acc(core::mem::transmute::(qx), vu, rt))", + ); + + map +} + +/// Generate wrapper functions for all intrinsics +fn generate_functions(intrinsics: &[IntrinsicInfo]) -> String { + let mut output = String::new(); + let simd_mappings = get_simd_intrinsic_mappings(); + + // Generate simple intrinsics + for info in intrinsics.iter().filter(|i| !i.is_compound) { + let rust_name = q6_to_rust_name(&info.q6_name); + + // Generate doc comment + output.push_str(&format!("/// `{}`\n", info.asm_syntax)); + output.push_str("///\n"); + output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type)); + output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots)); + + // Generate attributes + output.push_str("#[inline(always)]\n"); + output.push_str(&format!( + "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n", + info.min_arch + )); + + // Check if we should use simd intrinsic instead + let use_simd = simd_mappings.get(info.instr_name.as_str()); + + // assert_instr uses the original instruction name + output.push_str(&format!( + "#[cfg_attr(test, assert_instr({}))]\n", + info.instr_name + )); + + output.push_str(&format!( + "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n", + TRACKING_ISSUE + )); + + // Generate function signature + let params_str = info + .params + .iter() + .map(|(name, ty)| format!("{}: {}", name, ty.to_rust_str())) + .collect::>() + .join(", "); + + let return_str = if info.return_type == RustType::Unit { + String::new() + } else { + format!(" -> {}", info.return_type.to_rust_str()) + }; + + output.push_str(&format!( + "pub unsafe fn {}({}){} {{\n", + rust_name, params_str, return_str + )); + + // Generate function body + let args_str = info + .params + .iter() + .map(|(name, _)| name.as_str()) + .collect::>() + .join(", "); + + if let Some(simd_fn) = use_simd { + // Use architecture-independent simd intrinsic + output.push_str(&format!(" {}({})\n", simd_fn, args_str)); + } else { + // Use the LLVM intrinsic + output.push_str(&format!(" {}({})\n", info.instr_name, args_str)); + } + + output.push_str("}\n\n"); + } + + // Generate compound intrinsics + let helper_sigs = get_compound_helper_signatures(); + let overrides = get_compound_overrides(); + for info in intrinsics.iter().filter(|i| i.is_compound) { + if let Some(ref compound_expr) = info.compound_expr { + let rust_name = q6_to_rust_name(&info.q6_name); + + // Get the primary instruction for assert_instr + let _primary_instr = get_compound_primary_instr(compound_expr) + .unwrap_or_else(|| info.instr_name.clone()); + + // Generate doc comment + output.push_str(&format!("/// `{}`\n", info.asm_syntax)); + output.push_str("///\n"); + output.push_str( + "/// This is a compound operation composed of multiple HVX instructions.\n", + ); + if !info.instr_type.is_empty() { + output.push_str(&format!("/// Instruction Type: {}\n", info.instr_type)); + } + if !info.exec_slots.is_empty() { + output.push_str(&format!("/// Execution Slots: {}\n", info.exec_slots)); + } + + // Generate attributes + output.push_str("#[inline(always)]\n"); + output.push_str(&format!( + "#[cfg_attr(target_arch = \"hexagon\", target_feature(enable = \"hvxv{}\"))]\n", + info.min_arch + )); + + // For compound ops, we skip assert_instr since they emit multiple instructions + // output.push_str(&format!( + // "#[cfg_attr(test, assert_instr({}))]\n", + // primary_instr + // )); + + output.push_str(&format!( + "#[unstable(feature = \"stdarch_hexagon\", issue = \"{}\")]\n", + TRACKING_ISSUE + )); + + // Generate function signature + let params_str = info + .params + .iter() + .map(|(name, ty)| format!("{}: {}", name, ty.to_rust_str())) + .collect::>() + .join(", "); + + let return_str = if info.return_type == RustType::Unit { + String::new() + } else { + format!(" -> {}", info.return_type.to_rust_str()) + }; + + output.push_str(&format!( + "pub unsafe fn {}({}){} {{\n", + rust_name, params_str, return_str + )); + + // Check if we have an override for this intrinsic + let body = if let Some(override_body) = overrides.get(info.q6_name.as_str()) { + override_body.to_string() + } else { + // Build param type map for expression code generation + let param_types: HashMap = info.params.iter().cloned().collect(); + // Generate function body from compound expression + let expr_body = + generate_compound_expr_code(compound_expr, ¶m_types, &helper_sigs); + + // Check if we need to transmute the result + let expr_return_type = get_expr_type(compound_expr, ¶m_types, &helper_sigs); + if info.return_type == RustType::HvxVectorPred + && expr_return_type == Some(RustType::HvxVector) + { + format!( + "core::mem::transmute::({})", + expr_body + ) + } else { + expr_body + } + }; + output.push_str(&format!(" {}\n", body)); + + output.push_str("}\n\n"); + } + } + + output +} + +/// Generate a module file for a specific vector mode +fn generate_module_file( + intrinsics: &[IntrinsicInfo], + output_path: &Path, + mode: VectorMode, +) -> Result<(), String> { + let mut output = + File::create(output_path).map_err(|e| format!("Failed to create output: {}", e))?; + + writeln!(output, "{}", generate_module_doc(mode)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_types(mode)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_extern_block(intrinsics, mode)).map_err(|e| e.to_string())?; + writeln!(output, "{}", generate_functions(intrinsics)).map_err(|e| e.to_string())?; + + // Ensure file is flushed before running rustfmt + drop(output); + + // Run rustfmt on the generated file + let status = std::process::Command::new("rustfmt") + .arg(output_path) + .status() + .map_err(|e| format!("Failed to run rustfmt: {}", e))?; + + if !status.success() { + return Err("rustfmt failed".to_string()); + } + + Ok(()) +} + +fn main() -> Result<(), String> { + println!("=== Hexagon HVX Code Generator ===\n"); + + // Get the crate directory first (needed for both reading header and writing output) + let crate_dir = std::env::var("CARGO_MANIFEST_DIR") + .map(std::path::PathBuf::from) + .unwrap_or_else(|_| std::env::current_dir().unwrap()); + + // Read and parse the local LLVM header + println!("Step 1: Reading LLVM HVX header..."); + let header_content = read_header(&crate_dir)?; + println!(" Read {} bytes", header_content.len()); + + println!("\nStep 2: Parsing intrinsic definitions..."); + let all_intrinsics = parse_header(&header_content); + println!(" Found {} intrinsic definitions", all_intrinsics.len()); + + // Filter out intrinsics requiring architecture versions not yet supported by rustc + let intrinsics: Vec<_> = all_intrinsics + .into_iter() + .filter(|i| i.min_arch <= MAX_SUPPORTED_ARCH) + .collect(); + let filtered_count = intrinsics.len(); + println!( + " Filtered to {} intrinsics (max supported: hvxv{})", + filtered_count, MAX_SUPPORTED_ARCH + ); + + // Count simple vs compound + let simple_count = intrinsics.iter().filter(|i| !i.is_compound).count(); + let compound_count = intrinsics.iter().filter(|i| i.is_compound).count(); + println!(" Simple intrinsics: {}", simple_count); + println!(" Compound intrinsics: {}", compound_count); + + // Print some sample intrinsics for verification + println!("\n Sample simple intrinsics:"); + for info in intrinsics.iter().filter(|i| !i.is_compound).take(5) { + println!( + " {} -> {} ({})", + info.q6_name, info.builtin_name, info.asm_syntax + ); + } + + println!("\n Sample compound intrinsics:"); + for info in intrinsics.iter().filter(|i| i.is_compound).take(5) { + println!(" {} ({})", info.q6_name, info.asm_syntax); + } + + // Count architecture versions + let mut arch_counts: HashMap = HashMap::new(); + for info in &intrinsics { + *arch_counts.entry(info.min_arch).or_insert(0) += 1; + } + println!("\n By architecture version:"); + let mut archs: Vec<_> = arch_counts.iter().collect(); + archs.sort_by_key(|(k, _)| *k); + for (arch, count) in archs { + println!(" HVX v{}: {} intrinsics", arch, count); + } + + // Generate output files + let hexagon_dir = crate_dir.join("../core_arch/src/hexagon"); + + // Generate v64.rs (64-byte vector mode) + let v64_path = hexagon_dir.join("v64.rs"); + println!("\nStep 3: Generating v64.rs (64-byte mode)..."); + generate_module_file(&intrinsics, &v64_path, VectorMode::V64)?; + println!(" Output: {}", v64_path.display()); + + // Generate v128.rs (128-byte vector mode) + let v128_path = hexagon_dir.join("v128.rs"); + println!("\nStep 4: Generating v128.rs (128-byte mode)..."); + generate_module_file(&intrinsics, &v128_path, VectorMode::V128)?; + println!(" Output: {}", v128_path.display()); + + println!("\n=== Results ==="); + println!( + " Generated {} simple wrapper functions per module", + simple_count + ); + println!( + " Generated {} compound wrapper functions per module", + compound_count + ); + println!( + " Total: {} functions per module", + simple_count + compound_count + ); + println!(" Output files: v64.rs, v128.rs"); + + Ok(()) +} diff --git a/stdarch/crates/stdarch-gen-loongarch/lasx.spec b/stdarch/crates/stdarch-gen-loongarch/lasx.spec index e3bdfcb5e9faa..ac4203a03f207 100644 --- a/stdarch/crates/stdarch-gen-loongarch/lasx.spec +++ b/stdarch/crates/stdarch-gen-loongarch/lasx.spec @@ -2426,7 +2426,7 @@ data-types = V8SI, V4DI, V4DI /// lasx_xvorn_v name = lasx_xvorn_v asm-fmts = xd, xj, xk -data-types = V32QI, V32QI, V32QI +data-types = UV32QI, UV32QI, UV32QI /// lasx_xvldi name = lasx_xvldi @@ -3703,3 +3703,93 @@ name = lasx_xvrepli_w asm-fmts = xd, si10 data-types = V8SI, HI +/// lasx_cast_128_s +name = lasx_cast_128_s +asm-fmts = xd, vj +data-types = V8SF, V4SF + +/// lasx_cast_128_d +name = lasx_cast_128_d +asm-fmts = xd, vj +data-types = V4DF, V2DF + +/// lasx_cast_128 +name = lasx_cast_128 +asm-fmts = xd, vj +data-types = V4DI, V2DI + +/// lasx_concat_128_s +name = lasx_concat_128_s +asm-fmts = xd, vj, vk +data-types = V8SF, V4SF, V4SF + +/// lasx_concat_128_d +name = lasx_concat_128_d +asm-fmts = xd, vj, vk +data-types = V4DF, V2DF, V2DF + +/// lasx_concat_128 +name = lasx_concat_128 +asm-fmts = xd, vj, vk +data-types = V4DI, V2DI, V2DI + +/// lasx_extract_128_lo_s +name = lasx_extract_128_lo_s +asm-fmts = vd, xj +data-types = V4SF, V8SF + +/// lasx_extract_128_hi_s +name = lasx_extract_128_hi_s +asm-fmts = vd, xj +data-types = V4SF, V8SF + +/// lasx_extract_128_lo_d +name = lasx_extract_128_lo_d +asm-fmts = vd, xj +data-types = V2DF, V4DF + +/// lasx_extract_128_hi_d +name = lasx_extract_128_hi_d +asm-fmts = vd, xj +data-types = V2DF, V4DF + +/// lasx_extract_128_lo +name = lasx_extract_128_lo +asm-fmts = vd, xj +data-types = V2DI, V4DI + +/// lasx_extract_128_hi +name = lasx_extract_128_hi +asm-fmts = vd, xj +data-types = V2DI, V4DI + +/// lasx_insert_128_lo_s +name = lasx_insert_128_lo_s +asm-fmts = xd, xj, vk +data-types = V8SF, V8SF, V4SF + +/// lasx_insert_128_hi_s +name = lasx_insert_128_hi_s +asm-fmts = xd, xj, vk +data-types = V8SF, V8SF, V4SF + +/// lasx_insert_128_lo_d +name = lasx_insert_128_lo_d +asm-fmts = xd, xj, vk +data-types = V4DF, V4DF, V2DF + +/// lasx_insert_128_hi_d +name = lasx_insert_128_hi_d +asm-fmts = xd, xj, vk +data-types = V4DF, V4DF, V2DF + +/// lasx_insert_128_lo +name = lasx_insert_128_lo +asm-fmts = xd, xj, vk +data-types = V4DI, V4DI, V2DI + +/// lasx_insert_128_hi +name = lasx_insert_128_hi +asm-fmts = xd, xj, vk +data-types = V4DI, V4DI, V2DI + diff --git a/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h b/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h index c525b6106b897..02bb97918d95d 100644 --- a/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h +++ b/stdarch/crates/stdarch-gen-loongarch/lasxintrin.h @@ -1,10 +1,10 @@ /* - * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lasxintrin.h;hb=61f1001f2f4ab9128e5eb6e9a4adbbb0f9f0bc75 + * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lasxintrin.h;hb=c2013267642fea4a6e89b826940c8aa80a76089d */ /* LARCH Loongson ASX intrinsics include file. - Copyright (C) 2018-2024 Free Software Foundation, Inc. + Copyright (C) 2018-2025 Free Software Foundation, Inc. This file is part of GCC. @@ -27,6 +27,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ +#include + #ifndef _GCC_LOONGSON_ASXINTRIN_H #define _GCC_LOONGSON_ASXINTRIN_H 1 @@ -3568,11 +3570,11 @@ __m256i __lasx_xvssrln_w_d (__m256i _1, __m256i _2) } /* Assembly instruction format: xd, xj, xk. */ -/* Data types in instruction templates: V32QI, V32QI, V32QI. */ +/* Data types in instruction templates: UV32QI, UV32QI, UV32QI. */ extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m256i __lasx_xvorn_v (__m256i _1, __m256i _2) { - return (__m256i)__builtin_lasx_xvorn_v ((v32i8)_1, (v32i8)_2); + return (__m256i)__builtin_lasx_xvorn_v ((v32u8)_1, (v32u8)_2); } /* Assembly instruction format: xd, i13. */ @@ -5372,5 +5374,159 @@ __m256i __lasx_xvfcmp_sun_s (__m256 _1, __m256 _2) #define __lasx_xvrepli_w(/*si10*/ _1) \ ((__m256i)__builtin_lasx_xvrepli_w ((_1))) +#if defined (__loongarch_asx_sx_conv) +/* Add builtin interfaces for 128 and 256 vector conversions. + For the assembly instruction format of some functions of the following vector + conversion, it is not described exactly in accordance with the format of the + generated assembly instruction. + In the front end of the Rust language, different built-in functions are called + by analyzing the format of assembly instructions. The data types of instructions + are all defined based on the interfaces of the defined functions, in the + following order: output, input... . */ +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_cast_128_s (__m128 _1) +{ + return (__m256)__builtin_lasx_cast_128_s ((v4f32)_1); +} + +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_cast_128_d (__m128d _1) +{ + return (__m256d)__builtin_lasx_cast_128_d ((v2f64)_1); +} + +/* Assembly instruction format: xd, vj. */ +/* Data types in instruction templates: V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_cast_128 (__m128i _1) +{ + return (__m256i)__builtin_lasx_cast_128 ((v2i64)_1); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V8SF, V4SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_concat_128_s (__m128 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_concat_128_s ((v4f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V4DF, V2DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_concat_128_d (__m128d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_concat_128_d ((v2f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, vj, vk. */ +/* Data types in instruction templates: V4DI, V2DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_concat_128 (__m128i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_concat_128 ((v2i64)_1, (v2i64)_2); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V4SF, V8SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128 __lasx_extract_128_lo_s (__m256 _1) +{ + return (__m128)__builtin_lasx_extract_128_lo_s ((v8f32)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V4SF, V8SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128 __lasx_extract_128_hi_s (__m256 _1) +{ + return (__m128)__builtin_lasx_extract_128_hi_s ((v8f32)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DF, V4DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128d __lasx_extract_128_lo_d (__m256d _1) +{ + return (__m128d)__builtin_lasx_extract_128_lo_d ((v4f64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DF, V4DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128d __lasx_extract_128_hi_d (__m256d _1) +{ + return (__m128d)__builtin_lasx_extract_128_hi_d ((v4f64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DI, V4DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128i __lasx_extract_128_lo (__m256i _1) +{ + return (__m128i)__builtin_lasx_extract_128_lo ((v4i64)_1); +} + +/* Assembly instruction format: vd, xj. */ +/* Data types in instruction templates: V2DI, V4DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m128i __lasx_extract_128_hi (__m256i _1) +{ + return (__m128i)__builtin_lasx_extract_128_hi ((v4i64)_1); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V8SF, V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_insert_128_lo_s (__m256 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_insert_128_lo_s ((v8f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V8SF, V8SF, V4SF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256 __lasx_insert_128_hi_s (__m256 _1, __m128 _2) +{ + return (__m256)__builtin_lasx_insert_128_hi_s ((v8f32)_1, (v4f32)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DF, V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_insert_128_lo_d (__m256d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_insert_128_lo_d ((v4f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DF, V4DF, V2DF. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256d __lasx_insert_128_hi_d (__m256d _1, __m128d _2) +{ + return (__m256d)__builtin_lasx_insert_128_hi_d ((v4f64)_1, (v2f64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DI, V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_insert_128_lo (__m256i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_insert_128_lo ((v4i64)_1, (v2i64)_2); +} + +/* Assembly instruction format: xd, xj, vk. */ +/* Data types in instruction templates: V4DI, V4DI, V2DI. */ +extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__m256i __lasx_insert_128_hi (__m256i _1, __m128i _2) +{ + return (__m256i)__builtin_lasx_insert_128_hi ((v4i64)_1, (v2i64)_2); +} + +#endif /* defined(__loongarch_asx_sx_conv). */ #endif /* defined(__loongarch_asx). */ #endif /* _GCC_LOONGSON_ASXINTRIN_H. */ diff --git a/stdarch/crates/stdarch-gen-loongarch/lsx.spec b/stdarch/crates/stdarch-gen-loongarch/lsx.spec index dc835770d566e..b5497b6e6207e 100644 --- a/stdarch/crates/stdarch-gen-loongarch/lsx.spec +++ b/stdarch/crates/stdarch-gen-loongarch/lsx.spec @@ -3286,7 +3286,7 @@ data-types = V4SI, V2DI, V2DI /// lsx_vorn_v name = lsx_vorn_v asm-fmts = vd, vj, vk -data-types = V16QI, V16QI, V16QI +data-types = UV16QI, UV16QI, UV16QI /// lsx_vldi name = lsx_vldi diff --git a/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h b/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h index 943f2df913e4d..66b7c7e2187ac 100644 --- a/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h +++ b/stdarch/crates/stdarch-gen-loongarch/lsxintrin.h @@ -1,10 +1,10 @@ /* - * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lsxintrin.h;hb=61f1001f2f4ab9128e5eb6e9a4adbbb0f9f0bc75 + * https://gcc.gnu.org/git/?p=gcc.git;a=blob_plain;f=gcc/config/loongarch/lsxintrin.h;hb=6441eb6dc020faae0672ea724dfdb38c6a9bf6a1 */ /* LARCH Loongson SX intrinsics include file. - Copyright (C) 2018-2024 Free Software Foundation, Inc. + Copyright (C) 2018-2025 Free Software Foundation, Inc. This file is part of GCC. @@ -4749,11 +4749,11 @@ __m128i __lsx_vssrln_w_d (__m128i _1, __m128i _2) } /* Assembly instruction format: vd, vj, vk. */ -/* Data types in instruction templates: V16QI, V16QI, V16QI. */ +/* Data types in instruction templates: UV16QI, UV16QI, UV16QI. */ extern __inline __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __m128i __lsx_vorn_v (__m128i _1, __m128i _2) { - return (__m128i)__builtin_lsx_vorn_v ((v16i8)_1, (v16i8)_2); + return (__m128i)__builtin_lsx_vorn_v ((v16u8)_1, (v16u8)_2); } /* Assembly instruction format: vd, i13. */ diff --git a/stdarch/crates/stdarch-gen-loongarch/src/main.rs b/stdarch/crates/stdarch-gen-loongarch/src/main.rs index 5076064ffcdd3..10b87c70e9ede 100644 --- a/stdarch/crates/stdarch-gen-loongarch/src/main.rs +++ b/stdarch/crates/stdarch-gen-loongarch/src/main.rs @@ -157,7 +157,7 @@ fn gen_bind(in_file: String, ext_name: &str) -> io::Result<()> { // ``` use crate::mem::transmute; -use super::types::*; +use super::super::*; "# )); @@ -1551,6 +1551,10 @@ fn gen_test_body( format!( " printf(\"\\n {current_name}{as_params};\\n assert_eq!(r, transmute(o));\\n\"{as_args});" ) + } else if current_name.starts_with("lasx_cast_128") { + format!( + " printf(\"\\n assert_eq!(r.as_array()[0..2], transmute::<_, i64x4>({current_name}{as_params}).as_array()[0..2]);\\n\"{as_args});" + ) } else { format!( " printf(\"\\n assert_eq!(r, transmute({current_name}{as_params}));\\n\"{as_args});" diff --git a/stdarch/examples/Cargo.toml b/stdarch/examples/Cargo.toml index 61451edee841c..c4fc4c7e374c8 100644 --- a/stdarch/examples/Cargo.toml +++ b/stdarch/examples/Cargo.toml @@ -23,6 +23,11 @@ path = "hex.rs" name = "connect5" path = "connect5.rs" +# Hexagon-only: requires --target hexagon-unknown-linux-musl +[[bin]] +name = "gaussian" +path = "gaussian.rs" + [[example]] name = "wasm" crate-type = ["cdylib"] diff --git a/stdarch/examples/gaussian.rs b/stdarch/examples/gaussian.rs new file mode 100644 index 0000000000000..dea16f797aca6 --- /dev/null +++ b/stdarch/examples/gaussian.rs @@ -0,0 +1,351 @@ +//! Hexagon HVX Gaussian 3x3 blur example +//! +//! This example demonstrates the use of Hexagon HVX intrinsics to implement +//! a 3x3 Gaussian blur filter on unsigned 8-bit images. +//! +//! The 3x3 Gaussian kernel is: +//! 1 2 1 +//! 2 4 2 / 16 +//! 1 2 1 +//! +//! This is a separable filter: `[1 2 1]^T * [1 2 1] / 16`. +//! +//! On Hexagon targets, this implementation uses `HvxVectorPair` for widening +//! arithmetic to achieve full precision in the Gaussian computation, avoiding +//! the approximation errors of byte-averaging approaches. On other targets, +//! it runs a reference implementation in pure Rust. +//! +//! # Building and Running (Hexagon) +//! +//! To build (requires Hexagon toolchain): +//! +//! RUSTFLAGS="-C target-feature=+hvxv62,+hvx-length128b \ +//! -C linker=hexagon-unknown-linux-musl-clang" \ +//! cargo +nightly build -p stdarch_examples --bin gaussian \ +//! --target hexagon-unknown-linux-musl \ +//! -Zbuild-std -Zbuild-std-features=llvm-libunwind +//! +//! To run under QEMU: +//! +//! qemu-hexagon -L /target/hexagon-unknown-linux-musl \ +//! target/hexagon-unknown-linux-musl/debug/gaussian +//! +//! # Building and Running (Other targets) +//! +//! cargo +nightly run -p stdarch_examples --bin gaussian + +#![cfg_attr(target_arch = "hexagon", feature(stdarch_hexagon))] +#![cfg_attr(target_arch = "hexagon", feature(hexagon_target_feature))] +#![allow( + unsafe_op_in_unsafe_fn, + clippy::unwrap_used, + clippy::print_stdout, + clippy::missing_docs_in_private_items, + clippy::cast_possible_wrap, + clippy::cast_ptr_alignment +)] + +/// Image width - must be multiple of HVX vector length on Hexagon +const WIDTH: usize = 256; +const HEIGHT: usize = 16; + +// ============================================================================ +// Hexagon HVX implementation +// ============================================================================ + +#[cfg(target_arch = "hexagon")] +mod hvx { + #[cfg(not(target_feature = "hvx-length128b"))] + use core_arch::arch::hexagon::v64::*; + #[cfg(target_feature = "hvx-length128b")] + use core_arch::arch::hexagon::v128::*; + + /// Vector length in bytes for HVX 128-byte mode + #[cfg(target_feature = "hvx-length128b")] + const VLEN: usize = 128; + + /// Vector length in bytes for HVX 64-byte mode + #[cfg(not(target_feature = "hvx-length128b"))] + const VLEN: usize = 64; + + /// Vertical 1-2-1 filter pass using HvxVectorPair widening arithmetic + /// + /// Computes: dst[x] = (row_above[x] + 2*center[x] + row_below[x] + 2) >> 2 + /// + /// Uses HvxVectorPair to widen u8 to u16 for precise arithmetic, avoiding + /// the rounding errors of byte-averaging approximations. + /// + /// # Safety + /// + /// - `src` must point to the center row with valid data at -stride and +stride + /// - `dst` must point to a valid output buffer for `width` bytes + /// - `width` must be a multiple of VLEN + /// - All pointers must be HVX-aligned (128-byte for 128B mode) + #[target_feature(enable = "hvxv62")] + unsafe fn vertical_121_pass(src: *const u8, stride: isize, width: usize, dst: *mut u8) { + let inp0 = src.offset(-stride) as *const HvxVector; + let inp1 = src as *const HvxVector; + let inp2 = src.offset(stride) as *const HvxVector; + let outp = dst as *mut HvxVector; + + let n_chunks = width / VLEN; + for i in 0..n_chunks { + let above = *inp0.add(i); + let center = *inp1.add(i); + let below = *inp2.add(i); + + // Widen above + below to 16-bit using HvxVectorPair + // q6_wh_vadd_vubvub: adds two u8 vectors, producing u16 results in a pair + let above_plus_below: HvxVectorPair = q6_wh_vadd_vubvub(above, below); + + // Widen center * 2 (add center to itself) + let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(center, center); + + // Add them: (above + below) + (center * 2) = above + 2*center + below + let sum: HvxVectorPair = q6_wh_vadd_whwh(above_plus_below, center_x2); + + // Extract high and low vectors from the pair (each contains u16 values) + let sum_lo = q6_v_lo_w(sum); // Lower 64 elements as i16 + let sum_hi = q6_v_hi_w(sum); // Upper 64 elements as i16 + + // Arithmetic right shift by 2 (divide by 4) with rounding + // Add 2 for rounding before shift: (sum + 2) >> 2 + let two = q6_vh_vsplat_r(2); + let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two); + let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two); + let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two); + let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two); + + // Pack back to u8 with saturation: takes hi and lo halfword vectors, + // saturates to u8, and interleaves them back to original order + let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo); + + *outp.add(i) = result; + } + } + + /// Horizontal 1-2-1 filter pass using HvxVectorPair widening arithmetic + /// + /// Computes: dst[x] = (src[x-1] + 2*src[x] + src[x+1] + 2) >> 2 + /// + /// Uses `valign` and `vlalign` to shift vectors by 1 byte for neighbor access, + /// then HvxVectorPair for precise widening arithmetic. + /// + /// # Safety + /// + /// - `src` and `dst` must point to valid buffers of `width` bytes + /// - `width` must be a multiple of VLEN + /// - All pointers must be HVX-aligned + #[target_feature(enable = "hvxv62")] + unsafe fn horizontal_121_pass(src: *const u8, width: usize, dst: *mut u8) { + let inp = src as *const HvxVector; + let outp = dst as *mut HvxVector; + + let n_chunks = width / VLEN; + let mut prev = q6_v_vzero(); + + for i in 0..n_chunks { + let curr = *inp.add(i); + let next = if i + 1 < n_chunks { + *inp.add(i + 1) + } else { + q6_v_vzero() + }; + + // Left neighbor (x-1): shift curr right by 1 byte, filling from prev + let left = q6_v_vlalign_vvr(curr, prev, 1); + + // Right neighbor (x+1): shift curr left by 1 byte, filling from next + let right = q6_v_valign_vvr(next, curr, 1); + + // Widen left + right to 16-bit + let left_plus_right: HvxVectorPair = q6_wh_vadd_vubvub(left, right); + + // Widen center * 2 + let center_x2: HvxVectorPair = q6_wh_vadd_vubvub(curr, curr); + + // Add: left + 2*center + right + let sum: HvxVectorPair = q6_wh_vadd_whwh(left_plus_right, center_x2); + + // Extract high and low vectors + let sum_lo = q6_v_lo_w(sum); + let sum_hi = q6_v_hi_w(sum); + + // Arithmetic right shift by 2 with rounding + let two = q6_vh_vsplat_r(2); + let sum_lo_rounded = q6_vh_vadd_vhvh(sum_lo, two); + let sum_hi_rounded = q6_vh_vadd_vhvh(sum_hi, two); + let shifted_lo = q6_vh_vasr_vhvh(sum_lo_rounded, two); + let shifted_hi = q6_vh_vasr_vhvh(sum_hi_rounded, two); + + // Pack back to u8 with saturation + let result = q6_vub_vsat_vhvh(shifted_hi, shifted_lo); + + *outp.add(i) = result; + + prev = curr; + } + } + + /// Apply Gaussian 3x3 blur to an entire image using separable filtering + /// + /// Two-pass approach: + /// 1. Vertical pass: apply 1-2-1 filter across rows + /// 2. Horizontal pass: apply 1-2-1 filter across columns + /// + /// Combined effect: 3x3 Gaussian kernel [1 2 1; 2 4 2; 1 2 1] / 16 + /// + /// # Safety + /// + /// - `src` and `dst` must point to valid image buffers of `stride * height` bytes + /// - `tmp` must point to a valid temporary buffer of `width` bytes, HVX-aligned + /// - `width` must be a multiple of VLEN and >= VLEN + /// - `stride` must be >= `width` + /// - All buffers must be HVX-aligned (128-byte for 128B mode) + #[target_feature(enable = "hvxv62")] + pub unsafe fn gaussian3x3u8( + src: *const u8, + stride: usize, + width: usize, + height: usize, + dst: *mut u8, + tmp: *mut u8, + ) { + let stride_i = stride as isize; + + // Process interior rows (skip first and last which lack vertical neighbors) + for y in 1..height - 1 { + let row_src = src.offset(y as isize * stride_i); + let row_dst = dst.offset(y as isize * stride_i); + + // Pass 1: vertical 1-2-1 into tmp + vertical_121_pass(row_src, stride_i, width, tmp); + + // Pass 2: horizontal 1-2-1 from tmp into dst + horizontal_121_pass(tmp, width, row_dst); + } + } +} + +// ============================================================================ +// Reference implementation (works on all targets) +// ============================================================================ + +/// Reference implementation of Gaussian 3x3 blur +/// +/// Kernel: +/// 1 2 1 +/// 2 4 2 / 16 +/// 1 2 1 +fn gaussian3x3u8_reference(src: &[u8], stride: usize, width: usize, height: usize, dst: &mut [u8]) { + for y in 1..height - 1 { + for x in 1..width - 1 { + // Compute column sums (vertical 1-2-1 weights) + let mut col = [0u32; 3]; + for i in 0..3 { + col[i] = 1 * src[(y - 1) * stride + x - 1 + i] as u32 + + 2 * src[y * stride + x - 1 + i] as u32 + + 1 * src[(y + 1) * stride + x - 1 + i] as u32; + } + // Apply horizontal 1-2-1 weights and normalize + // (1*col[0] + 2*col[1] + 1*col[2] + 8) / 16 + dst[y * stride + x] = ((1 * col[0] + 2 * col[1] + 1 * col[2] + 8) >> 4) as u8; + } + } +} + +/// Generate deterministic test pattern +fn generate_test_pattern(buf: &mut [u8], width: usize, height: usize) { + for y in 0..height { + for x in 0..width { + buf[y * width + x] = ((x + y * 7) % 256) as u8; + } + } +} + +// ============================================================================ +// Main: runs HVX + reference on Hexagon, reference-only on other targets +// ============================================================================ + +#[cfg(target_arch = "hexagon")] +fn main() { + // Aligned buffers for HVX + #[repr(align(128))] + struct AlignedBuf([u8; N]); + + let mut src = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]); + let mut dst_hvx = AlignedBuf::<{ WIDTH * HEIGHT }>([0u8; WIDTH * HEIGHT]); + let mut tmp = AlignedBuf::<{ WIDTH }>([0u8; WIDTH]); + let mut dst_ref = vec![0u8; WIDTH * HEIGHT]; + + // Generate test pattern + generate_test_pattern(&mut src.0, WIDTH, HEIGHT); + + // Run HVX implementation + unsafe { + hvx::gaussian3x3u8( + src.0.as_ptr(), + WIDTH, + WIDTH, + HEIGHT, + dst_hvx.0.as_mut_ptr(), + tmp.0.as_mut_ptr(), + ); + } + + // Run reference + gaussian3x3u8_reference(&src.0, WIDTH, WIDTH, HEIGHT, &mut dst_ref); + + // Verify HVX matches reference (allowing small rounding differences) + let mut max_diff = 0i32; + for y in 1..HEIGHT - 1 { + for x in 1..WIDTH - 1 { + let idx = y * WIDTH + x; + let diff = (dst_hvx.0[idx] as i32 - dst_ref[idx] as i32).abs(); + max_diff = max_diff.max(diff); + // Allow up to 1 LSB difference due to rounding + assert!( + diff <= 1, + "HVX differs from reference at ({}, {}): hvx={}, ref={}, diff={}", + x, + y, + dst_hvx.0[idx], + dst_ref[idx], + diff + ); + } + } + + println!( + "Gaussian 3x3 HVX test passed! Max difference from reference: {}", + max_diff + ); +} + +#[cfg(not(target_arch = "hexagon"))] +fn main() { + let mut src = vec![0u8; WIDTH * HEIGHT]; + let mut dst = vec![0u8; WIDTH * HEIGHT]; + + // Generate test pattern + generate_test_pattern(&mut src, WIDTH, HEIGHT); + + // Run reference implementation + gaussian3x3u8_reference(&src, WIDTH, WIDTH, HEIGHT, &mut dst); + + // Verify output is non-trivial (blurred values differ from input) + let mut changed = 0; + for y in 1..HEIGHT - 1 { + for x in 1..WIDTH - 1 { + let idx = y * WIDTH + x; + if src[idx] != dst[idx] { + changed += 1; + } + } + } + + println!( + "Gaussian 3x3 reference test passed! {} pixels changed by blur", + changed + ); +} diff --git a/stdarch/rust-version b/stdarch/rust-version index ccc0b55d4dc55..b22c6c3869c62 100644 --- a/stdarch/rust-version +++ b/stdarch/rust-version @@ -1 +1 @@ -873d4682c7d285540b8f28bfe637006cef8918a6 +139651428df86cf88443295542c12ea617cbb587 diff --git a/test/src/formatters/junit.rs b/test/src/formatters/junit.rs index 74d99e0f1270e..2772222a05c9a 100644 --- a/test/src/formatters/junit.rs +++ b/test/src/formatters/junit.rs @@ -1,5 +1,5 @@ +use std::io; use std::io::prelude::Write; -use std::io::{self}; use std::time::Duration; use super::OutputFormatter; diff --git a/test/src/lib.rs b/test/src/lib.rs index d554807bbde70..f3dbd3d0556ab 100644 --- a/test/src/lib.rs +++ b/test/src/lib.rs @@ -24,7 +24,7 @@ #![feature(staged_api)] #![feature(process_exitcode_internals)] #![feature(panic_can_unwind)] -#![feature(test)] +#![cfg_attr(test, feature(test))] #![feature(thread_spawn_hook)] #![allow(internal_features)] #![warn(rustdoc::unescaped_backticks)] diff --git a/test/src/term.rs b/test/src/term.rs index d9880a776406d..1e4c7bc879cf7 100644 --- a/test/src/term.rs +++ b/test/src/term.rs @@ -12,8 +12,8 @@ #![deny(missing_docs)] +use std::io; use std::io::prelude::*; -use std::io::{self}; pub(crate) use terminfo::TerminfoTerminal; #[cfg(windows)] diff --git a/unwind/src/lib.rs b/unwind/src/lib.rs index cff2aa7b08b93..cce6ca748cccd 100644 --- a/unwind/src/lib.rs +++ b/unwind/src/lib.rs @@ -1,15 +1,14 @@ #![no_std] #![unstable(feature = "panic_unwind", issue = "32837")] #![feature(cfg_emscripten_wasm_eh)] -#![feature(cfg_select)] #![feature(link_cfg)] #![feature(staged_api)] -#![cfg_attr(not(target_env = "msvc"), feature(libc))] #![cfg_attr( all(target_family = "wasm", any(not(target_os = "emscripten"), emscripten_wasm_eh)), - feature(link_llvm_intrinsics, simd_wasm64) + feature(link_llvm_intrinsics, simd_wasm64, asm_experimental_arch) )] #![allow(internal_features)] +#![allow(unused_features)] #![deny(unsafe_op_in_unsafe_fn)] // Force libc to be included even if unused. This is required by many platforms. diff --git a/unwind/src/wasm.rs b/unwind/src/wasm.rs index 2bff306af293f..37d93bdbb67dd 100644 --- a/unwind/src/wasm.rs +++ b/unwind/src/wasm.rs @@ -2,6 +2,30 @@ #![allow(nonstandard_style)] +// Define the __cpp_exception tag that LLVM's wasm exception handling requires. +// In particular it is required to use either of: +// 1. the wasm_throw llvm intrinsic, or +// 2. the Rust try intrinsic. +// +// This must be provided since LLVM commit +// aee99e8015daa9f53ab1fd4e5b24cc4c694bdc4a which changed the tag from being +// weakly defined in each object file to being an external reference that must +// be linked from somewhere. +// +// We only define this for wasm32-unknown-unknown because on Emscripten/WASI +// targets, this symbol should be defined by the external toolchain. In +// particular, defining this on Emscripten would break Emscripten dynamic +// libraries. +#[cfg(all(target_os = "unknown", panic = "unwind"))] +core::arch::global_asm!( + ".globl __cpp_exception", + #[cfg(target_pointer_width = "64")] + ".tagtype __cpp_exception i64", + #[cfg(target_pointer_width = "32")] + ".tagtype __cpp_exception i32", + "__cpp_exception:", +); + #[repr(C)] #[derive(Debug, Copy, Clone, PartialEq)] pub enum _Unwind_Reason_Code { @@ -73,7 +97,7 @@ pub unsafe fn _Unwind_RaiseException(exception: *mut _Unwind_Exception) -> _Unwi // corresponds with llvm::WebAssembly::Tag::CPP_EXCEPTION // in llvm-project/llvm/include/llvm/CodeGen/WasmEHFuncInfo.h const CPP_EXCEPTION_TAG: i32 = 0; - wasm_throw(CPP_EXCEPTION_TAG, exception.cast()) + unsafe { wasm_throw(CPP_EXCEPTION_TAG, exception.cast()) } } _ => { let _ = exception;