From bf5e00602569c9b84b1f4a315cbaf5dc388e01bf Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Fri, 7 Aug 2026 17:05:29 +0530 Subject: [PATCH 1/5] PENDING: arm64: dts: qcom: Add iris video codec node for Nord Add iris video-codec node to nord-embedded.dtsi with clocks, resets, power-domains, IOMMU mappings and OPP table. List qcom,glymur-iris as a fallback compatible so the node matches the existing glymur platform data. Signed-off-by: Priyanka Gujjula Signed-off-by: Gourav Kumar --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 109 ++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi index 0d1c561b1f9e..6d08b829681d 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -1242,6 +1242,115 @@ #power-domain-cells = <1>; }; + iris: video-codec@aa00000 { + compatible = "qcom,nord-iris", "qcom,glymur-iris"; + reg = <0x0 0x0aa00000 0x0 0x000f0000>; + + clocks = <&nwgcc NW_GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&nwgcc NW_GCC_VIDEO_AXI0C_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, + <&nwgcc NW_GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVS1_CLK>, + <&videocc VIDEO_CC_MVS1_FREERUN_CLK>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun", + "iface2", + "vcodec1_core", + "vcodec1_core_freerun"; + + dma-coherent; + + interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_MVP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = ; + + iommus = <&apps_smmu_1 0x0960 0x0020>, /* Video VM0 XTENSA non-secure non-pixel */ + <&apps_smmu_1 0x0943 0x0000>, /* Video VM0 VCODEC non-secure pixel */ + <&apps_smmu_1 0x0944 0x0000>, /* Video VM0 VCODEC non-secure bitstream */ + <&apps_smmu_1 0x0940 0x0020>; /* Video VM0 VCODEC non-secure non-pixel */ + + memory-region = <&video_mem>; + + operating-points-v2 = <&iris_opp_table>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&videocc VIDEO_CC_MVS1_GDSC>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx", + "vcodec1"; + + resets = <&nwgcc NW_GCC_VIDEO_AXI0_CLK_ARES>, + <&nwgcc NW_GCC_VIDEO_AXI0C_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>, + <&nwgcc NW_GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>; + reset-names = "bus0", + "bus1", + "core", + "vcodec0_core", + "bus2", + "vcodec1_core"; + + /* + * IRIS firmware is signed by vendors, only + * enable on boards where the proper signed firmware + * is available. + */ + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000 240000000 360000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-435000000 { + opp-hz = /bits/ 64 <435000000 435000000 652500000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000 480000000 720000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533333333 { + opp-hz = /bits/ 64 <533333333 533333333 800000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000 560000000 840000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + videocc: clock-controller@aaf0000 { compatible = "qcom,nord-videocc"; reg = <0x0 0x0aaf0000 0x0 0x10000>; From 103e0fea42c8ea270809f286f77b87d755aea935 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Mon, 10 Aug 2026 16:53:22 +0530 Subject: [PATCH 2/5] PENDING: arm64: dts: qcom: nord: Enable iris video-codec node on rrd and ride-sx Enable the iris video-codec node for the rrd and ride-sx boards, and set firmware-name explicitly to the glymur video firmware since Nord reuses glymur's firmware. Signed-off-by: Priyanka Gujjula Signed-off-by: Gourav Kumar --- arch/arm64/boot/dts/qcom/nord-ride-sx.dts | 6 ++++++ arch/arm64/boot/dts/qcom/nord-rrd.dts | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-ride-sx.dts b/arch/arm64/boot/dts/qcom/nord-ride-sx.dts index b8839e1b8642..77100338ad44 100644 --- a/arch/arm64/boot/dts/qcom/nord-ride-sx.dts +++ b/arch/arm64/boot/dts/qcom/nord-ride-sx.dts @@ -569,6 +569,12 @@ status = "okay"; }; +&iris { + firmware-name = "qcom/vpu/vpu36_p4_s7.mbn"; + + status = "okay"; +}; + &qupv3_0 { firmware-name = "qcom/nord/qupv3fw.elf"; diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qcom/nord-rrd.dts index ddc534e2214b..62b60d669cb7 100644 --- a/arch/arm64/boot/dts/qcom/nord-rrd.dts +++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts @@ -521,6 +521,12 @@ }; }; +&iris { + firmware-name = "qcom/vpu/vpu36_p4_s7.mbn"; + + status = "okay"; +}; + &qupv3_0 { firmware-name = "qcom/nord/qupv3fw.elf"; From 53211b290c7c4a83404e8f85ebc2874bcf2f09f6 Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Mon, 17 Aug 2026 21:12:16 +0530 Subject: [PATCH 3/5] PENDING: dt-bindings: media: qcom,glymur-iris: Add qcom,nord-iris fallback Nord's iris node uses "qcom,nord-iris", "qcom,glymur-iris" as its compatible list, reusing Glymur's iris data via the DT fallback compatible. Add this combination in the schema alongside the existing qcom,glymur-iris-only case. Signed-off-by: Gourav Kumar --- .../devicetree/bindings/media/qcom,glymur-iris.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml index 3c5305b688ec..1774a4511c8f 100644 --- a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml @@ -15,7 +15,11 @@ description: properties: compatible: - const: qcom,glymur-iris + oneOf: + - items: + - const: qcom,nord-iris + - const: qcom,glymur-iris + - const: qcom,glymur-iris clocks: maxItems: 9 From 9db5114d2d307211421f6bfb5d86ef232b740a0f Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Mon, 10 Aug 2026 16:53:28 +0530 Subject: [PATCH 4/5] PENDING: soc: qcom: ubwc_config: Add Nord UBWC config entry Map qcom,nord to glymur_data in qcom_ubwc_configs[], since Nord shares Glymur's UBWC capabilities. Signed-off-by: Gourav Kumar --- drivers/soc/qcom/ubwc_config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 01dca97e2671..f1dae46f1b58 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -259,6 +259,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { { .compatible = "qcom,msm8976", .data = &no_ubwc_data }, { .compatible = "qcom,msm8996", .data = &msm8998_data }, { .compatible = "qcom,msm8998", .data = &msm8998_data }, + { .compatible = "qcom,nord", .data = &glymur_data }, { .compatible = "qcom,qcm2290", .data = &qcm2290_data, }, { .compatible = "qcom,qcm6490", .data = &sc7280_data, }, { .compatible = "qcom,qcs8300", .data = &sc8280xp_data, }, From a6fdb5c17f1369ffe17141d82a09c24fafb8146c Mon Sep 17 00:00:00 2001 From: Gourav Kumar Date: Mon, 10 Aug 2026 17:05:37 +0530 Subject: [PATCH 5/5] PENDING: media: iris: Double encoder ARP buffer size for Nord On Nord, dynamic single-session core switching (F1) is enabled by default in firmware, unlike Glymur where it is hardcoded off via a SoC check. With F1 enabled, firmware reserves internal sub-allocations out of the ARP buffer for both vcodec cores even for a single active session (uBufferCount:2), so the buffer sized for one core's worth of resources is exhausted mid-allocation and encoder session init fails: encSetInternalBuffers: uBufferCount:2 VenusVencAllocFromInternalBuffer: ... buffer_size shrinks to 8192 encSetInternalBuffers: TK: goto bailout VenusVencFWSessonInit: failed in internal buffer allocation venc_c2Start: Send HFI_CMD_START error response for port 0 Double the ARP buffer size for qcom,nord-iris so firmware has enough room to reserve resources for both cores. This is a workaround until firmware is fixed to not require double the ARP size for a single active session. Signed-off-by: Gourav Kumar --- drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c index ca03d6570513..dbc5e581a0ca 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -3,6 +3,8 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include + #include "iris_instance.h" #include "iris_vpu_buffer.h" #include "iris_hfi_gen1_defines.h" @@ -1808,6 +1810,10 @@ u32 hfi_buffer_dpb_enc_ar50lt(u32 frame_width, u32 frame_height, bool is_ten_bit static u32 iris_vpu_enc_arp_size(struct iris_inst *inst) { + /* TODO: remove once firmware no longer needs 2x ARP size on Nord */ + if (of_device_is_compatible(inst->core->dev->of_node, "qcom,nord-iris")) + return 2 * HFI_BUFFER_ARP_ENC; + return HFI_BUFFER_ARP_ENC; }