🔗 https://github.com/Raghavan-04/Custom_Audio_SOC
🔗 https://github.com/Raghavan-04/Hardware_Accelerator
Interactive Web-Based SystemVerilog Schematic Visualizer & EDA Workbench
- Synthesizes IEEE 1364/1800 SystemVerilog into formal gate netlists via Yosys and FastAPI.
- Implements semantic Level of Detail (LOD) zooming, transitioning from macro blocks to gate-level primitives.
- Uses ELK (Eclipse Layout Kernel) for layered topological placement, greedy feedback cycle-breaking, and Manhattan channel routing.
- Real-time silicon utilization telemetry HUD (Registers, MUXes, ALUs, Comparators).
🔗 https://gitroll.io/profile/ux6xlPz2j34NorYAdef641TEA9ru1