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1. microTheia microTheia Public

   Event-based, general-purpose machine vision ASIC

   Python 2

2. asic_spi_cdc_sram_wrapper asic_spi_cdc_sram_wrapper Public

   ASIC subsystem for type 0 SPI port utilizing register based CDC that drains into/from GF180 SRAM macro-based FIFO buffers

   SystemVerilog

3. VLSIDA/HighTide VLSIDA/HighTide Public

   Verilog 36 13

4. x320-stm-usb x320-stm-usb Public

   adding ability to stream evt data from sensor to host over usb

   C

5. VLSIDA/bsg_fakeram VLSIDA/bsg_fakeram Public

   Forked from bespoke-silicon-group/bsg_fakeram

   fakeram generator for use by researchers who do not have access to commercial ram generators

   Python 2 2