feat(ecc): add EC_MUL and SETUP_EC_MUL opcodes - #3103
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Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights. Commit: f1e0ecf |
`openvm_pairing::bls12_381` is behind the `bls12_381` feature, so building the examples with default features failed to resolve the import. Add the `required-features` entry the other bls examples already carry. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
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Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights. Commit: c859c16 |
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Code reviewNo issues found. Checked for bugs and CLAUDE.md compliance. |
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Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights. Commit: 4926b40 |
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Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights. Commit: 6b08efd |
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Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights. Commit: 989fac1 |
shuklaayush
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August 20, 2026 20:02
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unfortunately this causes a blowup in recursion time so i'm going to close it for now |
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This PR adds ecmul opcode:
The scalar must be odd, nonzero, and below the subgroup order.
The guest-side
mul_scalarwrappers handle even scalar case scenarios.SETUP_EC_MULfollows the same pattern as the other Weierstrass setups: its point operand carries(modulus, a), which the chip pins against its configuration.The reason for choosing odd scalars is so that the scalar can be represented as
2B + 1. The base point must be a non-identity point on the curve, in the prime-order subgroup, and the subgroup order must satisfyn ≡ 1 (mod 4).EC_MUL follows this formula where
σᵢ = 2bᵢ − 1:The formula above works because:
As result, one instruction spans 128 trace rows (we pack two steps per row and fuse the IO row
with the last row).
To bind the digits to the actual operand, the header threads a bit accumulator for
Bacross therows. The final row reconstructs
2B + 1and checks it byte-by-byte against the scalar read frommemory.
The row layout is header / field expression / IO. The point accumulator is threaded between rows
by transition constraint rather than through memory, and all memory traffic sits on the final row:
one point read, one scalar read, one point write per instruction.
On secp256k1 the chip is 1711 columns wide, 128 rows, 219k cells per scalar multiplication.
On the guest side,
msm_via_ec_mulcomputes MSM as oneEC_MULper base, andIntrinsicCurve::msmfor all four curves routes through it. An ECDSA verify/recover is now twoEC_MULs and one add. The generic Pippengermsmstays for G2 and external callers or custom defined.Resolves INT-8898, INT-9082