Tx eq settings

aal/src/lib.rs

@@ -8,7 +8,9 @@ use std::hash::Hash;
 
 use thiserror::Error;
 
-use common::ports::{PortFec, PortMedia, PortPrbsMode, PortSpeed, TxEq};
+use common::ports::{
+    PortFec, PortMedia, PortPrbsMode, PortSpeed, TxEq, TxEqSwHw,
+};
 use common::table::TableType;
 
 pub use dpd_types::table::{TableEntryAction, TableEntryKey};
@@ -245,13 +247,35 @@ pub trait AsicOps {
         settings: &TxEq,
     ) -> AsicResult<()>;
 
+    /// Read the current transceiver equalization settings on this port.
+    /// Returns an ordered iterator mapping each lane to its [`TxEqSwHw`] settings.
+    ///
+    /// - The outer error indicates failure accessing the port.
+    /// - The iterator error indicates failure accessing the specific lane.
+    fn port_tx_eq_get(
+        &self,
+        port_hdl: PortHdl,
+    ) -> AsicResult<impl ExactSizeIterator<Item = AsicResult<TxEqSwHw>>>;
+
     /// For the given connector, return a list of all of its channels which have
     /// not yet been assigned to a logical port.
     fn connector_avail_channels(
         &self,
         connector: Connector,
     ) -> AsicResult<Vec<u8>>;
 
+    /// Returns the tx equalization settings configured for this
+    /// connector in the SDE board map.
+    ///
+    /// These aren't necessarily the _current_ tx eq settings if runtime
+    /// modifications have been made.
+    ///
+    /// Returns an iterator mapping each u8 channel to its settings.
+    fn connector_tx_eq_defaults(
+        &self,
+        connector: Connector,
+    ) -> impl ExactSizeIterator<Item = AsicResult<(u8, TxEq)>>;
+
     /// Get sidecar identifiers of the device being managed.
     fn get_sidecar_identifiers(&self) -> AsicResult<impl SidecarIdentifiers>;
 

asic/src/chaos/mod.rs

@@ -529,6 +529,23 @@ impl AsicOps for Handle {
         Ok(())
     }
 
+    fn connector_tx_eq_defaults(
+        &self,
+        _: Connector,
+    ) -> impl ExactSizeIterator<Item = AsicResult<(u8, common::ports::TxEq)>>
+    {
+        std::iter::empty()
+    }
+
+    fn port_tx_eq_get(
+        &self,
+        _: PortHdl,
+    ) -> AsicResult<
+        impl ExactSizeIterator<Item = AsicResult<common::ports::TxEqSwHw>>,
+    > {
+        Ok(std::iter::empty())
+    }
+
     fn port_prbs_set(
         &self,
         _port_hdl: PortHdl,

asic/src/softnpu/mod.rs

@@ -133,11 +133,6 @@ impl Handle {
         })
     }
 
-    pub fn port_tx_eq_get(&self, port_hdl: PortHdl) -> AsicResult<i32> {
-        let ports = self.ports.lock().unwrap();
-        Ok(get_port(&ports, port_hdl)?.tx_eq)
-    }
-
     pub fn is_model(&self) -> bool {
         true
     }
@@ -292,10 +287,33 @@ impl AsicOps for Handle {
         tx_eq: &TxEq,
     ) -> AsicResult<()> {
         let mut ports = self.ports.lock().unwrap();
-        get_port_mut(&mut ports, port_hdl)?.tx_eq = tx_eq.main.unwrap_or(0);
+        get_port_mut(&mut ports, port_hdl)?.tx_eq = tx_eq.main;
         Ok(())
     }
 
+    fn port_tx_eq_get(
+        &self,
+        port_hdl: PortHdl,
+    ) -> AsicResult<
+        impl ExactSizeIterator<Item = AsicResult<common::ports::TxEqSwHw>>,
+    > {
+        let tx_eq_main =
+            self::get_port(&self.ports.lock().unwrap(), port_hdl)?.tx_eq;
+        let tx_eq = TxEq { main: tx_eq_main, ..Default::default() };
+
+        let lanes = self.port_get_lane_cnt(port_hdl)?;
+
+        Ok((0..lanes)
+            .map(move |_| Ok(common::ports::TxEqSwHw { hw: tx_eq, sw: tx_eq })))
+    }
+
+    fn connector_tx_eq_defaults(
+        &self,
+        _: Connector,
+    ) -> impl ExactSizeIterator<Item = AsicResult<(u8, TxEq)>> {
+        std::iter::once(Ok((0, TxEq::default())))
+    }
+
     fn port_autoneg_set(
         &self,
         _port_hdl: PortHdl,

asic/src/tofino_asic/imported_bf_functions

@@ -15,6 +15,7 @@ bf_drv_device_type_get
 
 # Board-related
 bf_bd_is_this_port_internal
+bf_bd_port_serdes_tx_params_get
 
 # multicast manager calls
 bf_mc_init

asic/src/tofino_asic/mod.rs

@@ -317,8 +317,35 @@ impl AsicOps for Handle {
         port_hdl: PortHdl,
         settings: &TxEq,
     ) -> AsicResult<()> {
-        let settings = serdes::TxEqSettings::from(*settings);
-        serdes::port_tx_eq_set(self, port_hdl, &settings)
+        serdes::port_tx_eq_set(self, port_hdl, settings)
+    }
+
+    fn port_tx_eq_get(
+        &self,
+        port_hdl: PortHdl,
+    ) -> AsicResult<impl ExactSizeIterator<Item = AsicResult<TxEqSwHw>>> {
+        let lanes = serdes::lane_count(self, port_hdl)?;
+        let lanes = u8::try_from(lanes).map_err(|e| {
+            AsicError::Internal(format!(
+                "Any reasonable lane count should fit in a u8. Found lanes = {lanes:?}: {e:?}"
+            ))
+        })?;
+
+        Ok((0..lanes)
+            .map(move |lane| serdes::lane_tx_eq_get(self, port_hdl, lane)))
+    }
+
+    fn connector_tx_eq_defaults(
+        &self,
+        connector: Connector,
+    ) -> impl ExactSizeIterator<Item = AsicResult<(u8, TxEq)>> {
+        (0..tofino_common::ports::CHANNELS_PER_SWITCH_PORT).map(
+            move |channel| {
+                let tx_eq =
+                    serdes::connector_tx_eq_default(self, connector, channel)?;
+                Ok((channel, tx_eq))
+            },
+        )
     }
 }
 
@@ -472,6 +499,17 @@ impl Handle {
     pub fn clear_qsfp_state(&self) {
         qsfp::clear_transceiver_tx();
     }
+
+    /// Returns the board map ID of the given connector or an error
+    /// if ID couldn't be determined.
+    pub fn connector_id(&self, conn: Connector) -> AsicResult<u32> {
+        match (conn, self.eth_connector_id) {
+            (Connector::QSFP(id), _) | (Connector::CPU, Some(id)) => Ok(id),
+            (Connector::CPU, None) => {
+                Err(AsicError::InvalidArg("no CPU ports found".to_string()))
+            }
+        }
+    }
 }
 
 pub fn sde_error(ctx: impl ToString, err: bf_status_t) -> AsicError {

asic/src/tofino_asic/ports.rs

@@ -108,16 +108,11 @@ impl FrontPortHandle {
 
     /// Given a PortHdl, return the front-panel port it maps to
     pub fn from_port_hdl(hdl: &Handle, port_hdl: PortHdl) -> AsicResult<Self> {
-        let connector = match port_hdl.connector {
-            Connector::CPU => match hdl.eth_connector_id {
-                Some(id) => Ok(id),
-                None => {
-                    Err(AsicError::InvalidArg("no CPU ports found".to_string()))
-                }
-            },
-            Connector::QSFP(c) => Ok(c),
-        }?;
-        Ok(FrontPortHandle::new(hdl.dev_id, connector, port_hdl.channel))
+        Ok(FrontPortHandle::new(
+            hdl.dev_id,
+            hdl.connector_id(port_hdl.connector)?,
+            port_hdl.channel,
+        ))
     }
 
     /// Get the first front-panel port.  Whether this is actually "first" in any