arm64: dts: qcom: sm8750: Add Pakala (Adreno 830) GPU DT nodes - #1702
arm64: dts: qcom: sm8750: Add Pakala (Adreno 830) GPU DT nodes#1702quic-ksanadhy wants to merge 19 commits into
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amd_ntb_link_disable() prints "Enabling Link" which is misleading. Update the message to reflect that the link is being disabled. Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
…hare BAR When BAR_PEER_SPAD and BAR_CONFIG share one PCI BAR, the module teardown path ends up calling pci_iounmap() on the same iomem with some offset, which is unnecessary and triggers a kernel warning like the following: Trying to vunmap() nonexistent vm area (0000000069a5ffe8) WARNING: mm/vmalloc.c:3470 at vunmap+0x58/0x68, CPU#5: modprobe/2937 [...] Call trace: vunmap+0x58/0x68 (P) iounmap+0x34/0x48 pci_iounmap+0x2c/0x40 ntb_epf_pci_remove+0x44/0x80 [ntb_hw_epf] pci_device_remove+0x48/0xf8 device_remove+0x50/0x88 device_release_driver_internal+0x1c8/0x228 driver_detach+0x50/0xb0 bus_remove_driver+0x74/0x100 driver_unregister+0x34/0x68 pci_unregister_driver+0x34/0xa0 ntb_epf_pci_driver_exit+0x14/0xfe0 [ntb_hw_epf] [...] Fix it by unmapping only when PEER_SPAD and CONFIG use difference bars. Cc: stable@vger.kernel.org Fixes: e75d5ae ("NTB: epf: Allow more flexibility in the memory BAR map method") Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Koichiro Den <den@valinux.co.jp> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
Correct a function name and function parameter name to avoid kernel-doc warnings: Warning: include/linux/ntb.h:575 expecting prototype for ntb_default_port_count(). Prototype was for ntb_default_peer_port_count() instead Warning: include/linux/ntb.h:590 function parameter 'pidx' not described in 'ntb_default_peer_port_number' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Acked-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
The current list initialisation depends on the well hidden two zeros in the PCI_VDEVICE macro. Instead use a named initialisation that is more robust and easier to understand. Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Link: https://lore.kernel.org/all/20260204-enable-ctcu-and-etr-v3-3-0bb95c590ae1@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…nel nt37801 The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states VDDI=1.65V~1.95V, so set sufficient voltage for panel nt37801. Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com> Link: https://lore.kernel.org/all/20260323102229.1546504-1-quic_amakhija@quicinc.com/ Signed-off-by: Arpit Saini <arpisain@qti.qualcomm.com>
The Inline Crypto Engine (ICE) exists as a standalone DT node, but the UFS node lacks the required qcom,ice phandle reference. Add the qcom,ice property to explicitly associate the UFS controller with its ICE instance. Fixes: d288abc ("arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC") Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/lkml/20260429-sm8750_ice_dt_fix-v1-1-2540dc337082@oss.qualcomm.com/ Signed-off-by: Kumar Kartik <kkartik@qti.qualcomm.com>
Add PSCI SYSTEM_RESET2 reboot-modes for sm8750-mtp and sm8750-qrd for use by the psci-reboot-mode driver. The following modes are defined: - bootloader: reboot into fastboot mode for fastboot flashing. - edl: reboot into emergency download mode for image loading via the Firehose protocol. Link: https://lore.kernel.org/r/20260529-psci_sys_reset-dt-changes-for-pakala-v2-1-1964ebf1924c@oss.qualcomm.com Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Add node for the SM8750 camera subsystem. Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260618-pakala-camera-v2-1-9fbb729fd242@oss.qualcomm.com/
Qualcomm SM8750 SoC has three Camera Control Interface (CCI). Each controller contains two I2C hosts. Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260618-pakala-camera-v2-2-9fbb729fd242@oss.qualcomm.com/
Define pinctrl definitions to enable camera master clocks on SM8750. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260618-pakala-camera-v2-3-9fbb729fd242@oss.qualcomm.com/
The traceNoC node used the "qcom,coresight-tnoc", "arm,primecell" compatible, which places the device on the AMBA bus. To bind an AMBA device, the bus reads the peripheral and component ID registers (PID/CID) at the top of the device's register block and matches them against the primecell ID. The traceNoC exposes the CID registers, but the Component ID value returned by the hardware is 0x00000000 instead of a valid AMBA Component ID, so the match never succeeds, the AMBA probe fails, and the device is left stuck in deferred probe indefinitely. Drop the "arm,primecell" entry and use the standalone "qcom,coresight-tnoc" compatible, which binds via the platform driver by compatible string and does not rely on the component ID register at all. This lets the device probe on hardware that does not return a valid CID, while remaining an Aggregator TNOC that retains ATID functionality. Link: https://lore.kernel.org/all/20260710-fix-tracenoc-probe-issue-v6-4-41eb36fef8d9@oss.qualcomm.com/ Fixes: ebd1eb3 ("arm64: qcom: dts: sm8750: add coresight nodes") Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add Battery Current Limiting (BCL) hardware monitor node for pmih0108 PMIC. The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-qcom-bcl-hwmon-v2-9-febe2805e17b@oss.qualcomm.com
PR #1702 — validate-patchPR: #1702
Final Summary
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PR #1702 — checker-log-analyzerPR: #1702
Detailed report: Full report
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🔨 Build Failure Analysis — PR #1702PR: #1702
VerdictThis is not a compilation failure. The build failed during the merge phase before any compilation could occur. The PR itself contains no changes (empty patch), but the merge conflicts suggest the PR branch is based on an incompatible baseline compared to the integration branch (tag 📎 Detailed analysis: |
🔨 Build Failure Analysis — PR #1702PR: #1702
VerdictThis is not a compilation failure. The build failed during the git merge phase when attempting to integrate PR #1702 (branch 📎 Detailed analysis: Full report |
Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this is simply a separate block housing the GX GDSC) nodes, required to power up the graphics-related hardware. Make use of it by enabling the associated IOMMU as well. The GPU itself needs some more work and will be enabled later. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/lkml/20260714-gpucc_dt_v6-v6-1-16bf5289572d@oss.qualcomm.com/#r
Adreno 830 GPU present in SM8750 chipset belongs to the A8x family of Adreno GPU. It is similar to Adreno 840 GPU with some meaningful differences like GMEM size, register file size etc. Describe A830 GPU and GMU nodes in SM8750 devicetree. Also, add the qfprom node to describe the GPU speedbin fuse register. Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/lkml/20260809-pakala-gpu-v1-1-207ad1fac1c7@oss.qualcomm.com/T/#m6fbc0b228215096af09673f94e53b4680182f9f8
Unlike the CPU, the GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when reaching 105°C. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> https://lore.kernel.org/lkml/20260809-pakala-gpu-v1-1-207ad1fac1c7@oss.qualcomm.com/T/#m6fbc0b228215096af09673f94e53b4680182f9f8
Enable GPU for sm8750-mtp platform and provide path for zap shader. Upstream-Status: Pending Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/lkml/20260809-pakala-gpu-v1-1-207ad1fac1c7@oss.qualcomm.com/T/#m6fbc0b228215096af09673f94e53b4680182f9f8
Enable GPU for sm8750-qrd platform and provide path for zap shader. Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/lkml/20260809-pakala-gpu-v1-1-207ad1fac1c7@oss.qualcomm.com/T/#m6fbc0b228215096af09673f94e53b4680182f9f8
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Add Device Tree support for the Adreno 830 GPU on the Pakala (SM8750) SoC.
CRs-Fixed: 4647429