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Add Coresight nodes for Nord - #968

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Komal Bajaj (Komal-Bajaj) merged 2 commits into
qualcomm-linux:staging/nordfrom
jiegan0107:staging/nord
Aug 18, 2026
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Add Coresight nodes for Nord#968
Komal Bajaj (Komal-Bajaj) merged 2 commits into
qualcomm-linux:staging/nordfrom
jiegan0107:staging/nord

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Add the CoreSight trace topology for the Qualcomm Nord SoC: CTCU, STM, TPDM/TPDA sources and aggregators, funnels, replicators, TMC ETR/ETF sinks, TNoC/ITNoC nodes and per-subsystem CTIs. This wires up trace sources for SOCCP, BCV/IMH/DPM, GCC, QM, DL_NOC, the CDSP NSP0-3 clusters, DLMM, EVA, MDSS0/1, LPASS and the AOSS SWAO priority TPDMs, plus the DDR0-3 channel and LLCC TPDMs, all funneled through the tn_ag aggregator into the main CoreSight funnel and out to the AOSS sink.

The CTCU device for nord shares the same configurations as SA8775p. Add
a fallback to enable the CTCU for nord to utilize the compatible of the
SA8775p.

Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the CoreSight trace topology for the Qualcomm Nord SoC: CTCU, STM,
TPDM/TPDA sources and aggregators, funnels, replicators, TMC ETR/ETF
sinks, TNoC/ITNoC nodes and per-subsystem CTIs. This wires up trace
sources for SOCCP, BCV/IMH/DPM, GCC, QM, DL_NOC, the CDSP NSP0-3
clusters, DLMM, EVA, MDSS0/1, LPASS and the AOSS SWAO priority TPDMs,
plus the DDR0-3 channel and LLCC TPDMs, all funneled through the
tn_ag aggregator into the main CoreSight funnel and out to the AOSS
sink.

Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
label = "cti_ddr3";
};

apps_smmu_0: iommu@15a00000 {

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please put nodes in sorted order

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cti@12621000 should before iommu@15a00000.

node with address should sort with address lower->higher. 12621000 < 15a00000

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Great, thanks.

<GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>;
};

apps_smmu_1: iommu@15c00000 {

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please put nodes in sorted order. apps_smmu nodes should come before cti.

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same to previous reply

@apateriy-qcom apateriy-qcom left a comment

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gave some review comments

@jiegan0107 Jie Gan (jiegan0107) left a comment

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not an issue, sorted with correct order

label = "cti_ddr3";
};

apps_smmu_0: iommu@15a00000 {

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cti@12621000 should before iommu@15a00000.

node with address should sort with address lower->higher. 12621000 < 15a00000

<GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>;
};

apps_smmu_1: iommu@15c00000 {

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same to previous reply

roshs189 added a commit to roshs189/meta-qcom that referenced this pull request Aug 18, 2026
Bumps SRCREV/SRCBRANCH to staging/nord@e4786033a93d5cf971a05e11d8046647f740708b
so the build picks up the board's device tree, which lives on the PR's topic
branch rather than the recipe's default pinned revision.

Signed-off-by: Roshan Sivakumar <roshs@qti.qualcomm.com>
@Komal-Bajaj
Komal Bajaj (Komal-Bajaj) merged commit 8626fe0 into qualcomm-linux:staging/nord Aug 18, 2026
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3 participants