Add Coresight nodes for Nord - #968
Merged
Komal Bajaj (Komal-Bajaj) merged 2 commits intoAug 18, 2026
Merged
Conversation
The CTCU device for nord shares the same configurations as SA8775p. Add a fallback to enable the CTCU for nord to utilize the compatible of the SA8775p. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the CoreSight trace topology for the Qualcomm Nord SoC: CTCU, STM, TPDM/TPDA sources and aggregators, funnels, replicators, TMC ETR/ETF sinks, TNoC/ITNoC nodes and per-subsystem CTIs. This wires up trace sources for SOCCP, BCV/IMH/DPM, GCC, QM, DL_NOC, the CDSP NSP0-3 clusters, DLMM, EVA, MDSS0/1, LPASS and the AOSS SWAO priority TPDMs, plus the DDR0-3 channel and LLCC TPDMs, all funneled through the tn_ag aggregator into the main CoreSight funnel and out to the AOSS sink. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
| label = "cti_ddr3"; | ||
| }; | ||
|
|
||
| apps_smmu_0: iommu@15a00000 { |
There was a problem hiding this comment.
please put nodes in sorted order
Author
There was a problem hiding this comment.
cti@12621000 should before iommu@15a00000.
node with address should sort with address lower->higher. 12621000 < 15a00000
| <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; | ||
| }; | ||
|
|
||
| apps_smmu_1: iommu@15c00000 { |
There was a problem hiding this comment.
please put nodes in sorted order. apps_smmu nodes should come before cti.
Author
There was a problem hiding this comment.
same to previous reply
Jie Gan (jiegan0107)
left a comment
Author
There was a problem hiding this comment.
not an issue, sorted with correct order
| label = "cti_ddr3"; | ||
| }; | ||
|
|
||
| apps_smmu_0: iommu@15a00000 { |
Author
There was a problem hiding this comment.
cti@12621000 should before iommu@15a00000.
node with address should sort with address lower->higher. 12621000 < 15a00000
| <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; | ||
| }; | ||
|
|
||
| apps_smmu_1: iommu@15c00000 { |
Author
There was a problem hiding this comment.
same to previous reply
roshs189
added a commit
to roshs189/meta-qcom
that referenced
this pull request
Aug 18, 2026
Bumps SRCREV/SRCBRANCH to staging/nord@e4786033a93d5cf971a05e11d8046647f740708b so the build picks up the board's device tree, which lives on the PR's topic branch rather than the recipe's default pinned revision. Signed-off-by: Roshan Sivakumar <roshs@qti.qualcomm.com>
Komal Bajaj (Komal-Bajaj)
approved these changes
Aug 18, 2026
Komal Bajaj (Komal-Bajaj)
merged commit Aug 18, 2026
8626fe0
into
qualcomm-linux:staging/nord
1 of 2 checks passed
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Add the CoreSight trace topology for the Qualcomm Nord SoC: CTCU, STM, TPDM/TPDA sources and aggregators, funnels, replicators, TMC ETR/ETF sinks, TNoC/ITNoC nodes and per-subsystem CTIs. This wires up trace sources for SOCCP, BCV/IMH/DPM, GCC, QM, DL_NOC, the CDSP NSP0-3 clusters, DLMM, EVA, MDSS0/1, LPASS and the AOSS SWAO priority TPDMs, plus the DDR0-3 channel and LLCC TPDMs, all funneled through the tn_ag aggregator into the main CoreSight funnel and out to the AOSS sink.