A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)

A High-performance Timing Analysis Tool for VLSI Systems

ASIC implementation flow infrastructure, successor to OpenLane

Python framework for designing & analyzing superconducting quantum chips. Lite-by-default, headless-friendly, EDA-grade.

[NeurIPS 2024] ReEvo: Large Language Models as Hyper-Heuristics with Reflective Evolution

CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

Open-source MCP server for Altium Designer, with an optional KiCad backend. 300+ tools for schematic, PCB, library and project automation: design review, audits, rendering, auto-placement, panelization, and an autonomous design-plan executor. Altium over a persistent DelphiScript bridge, KiCad over its IPC API. Apache-2.0.

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

A powerful Python framework for orchestrating AI agents and managing complex LLM-driven tasks with ease.

🤖 Intelligent AI-powered PCB design automation tool using machine learning for component placement, routing optimization, and signal integrity analysis. Supports KiCad, Altium Designer, and Eagle CAD integration.

A Standalone Structural Verilog Parser

VLSI EDA Global Router

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

RL_PCB is a novel learning-based method for optimising the placement of circuit components on a Printed Circuit Board (PCB).

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

design and verification of asynchronous circuits

A standalone structural (gate-level) verilog parser

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.