This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
This repository include all the codes and constraints used in the development of the Master Thesis: "Development of a Differential Absorption Lidar System based on a SoC-FPGA for Carbon Dioxide Sensing" by Victor Ricardo Aguilera Sanchez
Digital Design and Computer Organisation Mini-project
A hands-on introduction to Verilog, a hardware description language. It's packed with code examples covering everything from basic logic gates and counters to complex designs like finite state machines (for elevators and railway crossings), various memory types (asynchronous, synchronous, dual-port), and even PRBS generators and FIFOs.
A web-application with tools for generating pseudorandom binary sequences, performing analysis, and visualizing results with graphs and charts.
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