#
riscv-processor
Here are 3 public repositories matching this topic...
Performance evaluation of Stage0 (PCGen & Branch Predictor) variants in SHAKTI C-Class RISC-V core RTL — CEG Fabless Internship 2025
rtl bluespec risc-v coremark branch-predictor shakti iit-madras annauniversity c-class riscv-processor
-
Updated
Apr 13, 2026
A RISC-V processor implemented in SystemVerilog featuring Single-Cycle, Multi-Cycle, and 5-Stage Pipeline architectures.
pipeline riscv systemverilog computer-architecture risc-v digital-design computer-organization processor-design hardware-design riscv-processor
-
Updated
Jul 23, 2026 - SystemVerilog
Improve this page
Add a description, image, and links to the riscv-processor topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the riscv-processor topic, visit your repo's landing page and select "manage topics."